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src/cpu/core_full/ea_lookup.h
00001 /*
00002  *  Copyright (C) 2002-2013  The DOSBox Team
00003  *
00004  *  This program is free software; you can redistribute it and/or modify
00005  *  it under the terms of the GNU General Public License as published by
00006  *  the Free Software Foundation; either version 2 of the License, or
00007  *  (at your option) any later version.
00008  *
00009  *  This program is distributed in the hope that it will be useful,
00010  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
00011  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
00012  *  GNU General Public License for more details.
00013  *
00014  *  You should have received a copy of the GNU General Public License
00015  *  along with this program; if not, write to the Free Software
00016  *  Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
00017  */
00018 
00019 {
00020         EAPoint seg_base;
00021         Bit16u off;
00022         switch ((inst.rm_mod<<3)|inst.rm_eai) {
00023         case 0x00:
00024                 off=reg_bx+reg_si;
00025                 seg_base=SegBase(ds);
00026                 break;
00027         case 0x01:
00028                 off=reg_bx+reg_di;
00029                 seg_base=SegBase(ds);
00030                 break;
00031         case 0x02:
00032                 off=reg_bp+reg_si;
00033                 seg_base=SegBase(ss);
00034                 break;
00035         case 0x03:
00036                 off=reg_bp+reg_di;
00037                 seg_base=SegBase(ss);
00038                 break;
00039         case 0x04:
00040                 off=reg_si;
00041                 seg_base=SegBase(ds);
00042                 break;
00043         case 0x05:
00044                 off=reg_di;
00045                 seg_base=SegBase(ds);
00046                 break;
00047         case 0x06:
00048                 off=Fetchw();
00049                 seg_base=SegBase(ds);
00050                 break;
00051         case 0x07:
00052                 off=reg_bx;
00053                 seg_base=SegBase(ds);
00054                 break;
00055 
00056         case 0x08:
00057                 off=reg_bx+reg_si+Fetchbs();
00058                 seg_base=SegBase(ds);
00059                 break;
00060         case 0x09:
00061                 off=reg_bx+reg_di+Fetchbs();
00062                 seg_base=SegBase(ds);
00063                 break;
00064         case 0x0a:
00065                 off=reg_bp+reg_si+Fetchbs();
00066                 seg_base=SegBase(ss);
00067                 break;
00068         case 0x0b:
00069                 off=reg_bp+reg_di+Fetchbs();
00070                 seg_base=SegBase(ss);
00071                 break;
00072         case 0x0c:
00073                 off=reg_si+Fetchbs();
00074                 seg_base=SegBase(ds);
00075                 break;
00076         case 0x0d:
00077                 off=reg_di+Fetchbs();
00078                 seg_base=SegBase(ds);
00079                 break;
00080         case 0x0e:
00081                 off=reg_bp+Fetchbs();
00082                 seg_base=SegBase(ss);
00083                 break;
00084         case 0x0f:
00085                 off=reg_bx+Fetchbs();
00086                 seg_base=SegBase(ds);
00087                 break;
00088         
00089         case 0x10:
00090                 off=reg_bx+reg_si+Fetchws();
00091                 seg_base=SegBase(ds);
00092                 break;
00093         case 0x11:
00094                 off=reg_bx+reg_di+Fetchws();
00095                 seg_base=SegBase(ds);
00096                 break;
00097         case 0x12:
00098                 off=reg_bp+reg_si+Fetchws();
00099                 seg_base=SegBase(ss);
00100                 break;
00101         case 0x13:
00102                 off=reg_bp+reg_di+Fetchws();
00103                 seg_base=SegBase(ss);
00104                 break;
00105         case 0x14:
00106                 off=reg_si+Fetchws();
00107                 seg_base=SegBase(ds);
00108                 break;
00109         case 0x15:
00110                 off=reg_di+Fetchws();
00111                 seg_base=SegBase(ds);
00112                 break;
00113         case 0x16:
00114                 off=reg_bp+Fetchws();
00115                 seg_base=SegBase(ss);
00116                 break;
00117         case 0x17:
00118                 off=reg_bx+Fetchws();
00119                 seg_base=SegBase(ds);
00120                 break;
00121         default:
00122                 off=seg_base=0;
00123                 break;
00124         }
00125         inst.rm_off=off;
00126         if (inst.prefix & PREFIX_SEG) {
00127                 inst.rm_eaa=inst.seg.base+off;
00128         } else {
00129                 inst.rm_eaa=seg_base+off;
00130         }
00131 } else  {
00132 
00133 
00134 #define SIB(MODE)       {                                                                                               \
00135         Bitu sib=Fetchb();                                                                                              \
00136         switch (sib&7) {                                                                                                \
00137         case 0:seg_base=SegBase(ds);off=reg_eax;break;                                  \
00138         case 1:seg_base=SegBase(ds);off=reg_ecx;break;                                  \
00139         case 2:seg_base=SegBase(ds);off=reg_edx;break;                                  \
00140         case 3:seg_base=SegBase(ds);off=reg_ebx;break;                                  \
00141         case 4:seg_base=SegBase(ss);off=reg_esp;break;                                  \
00142         case 5:if (!MODE) {     seg_base=SegBase(ds);off=Fetchd();break;        \
00143                    } else { seg_base=SegBase(ss);off=reg_ebp;break;}            \
00144         case 6:seg_base=SegBase(ds);off=reg_esi;break;                                  \
00145         case 7:seg_base=SegBase(ds);off=reg_edi;break;                                  \
00146         }                                                                                                                               \
00147         off+=*SIBIndex[(sib >> 3) &7] << (sib >> 6);                                    \
00148 };                                                                                                                                      
00149         static Bit32u SIBZero=0;
00150         static Bit32u * SIBIndex[8]= { &reg_eax,&reg_ecx,&reg_edx,&reg_ebx,&SIBZero,&reg_ebp,&reg_esi,&reg_edi };
00151         EAPoint seg_base;
00152         Bit32u off;
00153 
00154         switch ((inst.rm_mod<<3)|inst.rm_eai) {
00155         case 0x00:
00156                 off=reg_eax;
00157                 seg_base=SegBase(ds);
00158                 break;
00159         case 0x01:
00160                 off=reg_ecx;
00161                 seg_base=SegBase(ds);
00162                 break;
00163         case 0x02:
00164                 off=reg_edx;
00165                 seg_base=SegBase(ds);
00166                 break;
00167         case 0x03:
00168                 off=reg_ebx;
00169                 seg_base=SegBase(ds);
00170                 break;
00171         case 0x04:
00172                 SIB(0);
00173                 break;
00174         case 0x05:
00175                 off=Fetchd();
00176                 seg_base=SegBase(ds);
00177                 break;
00178         case 0x06:
00179                 off=reg_esi;
00180                 seg_base=SegBase(ds);
00181                 break;
00182         case 0x07:
00183                 off=reg_edi;
00184                 seg_base=SegBase(ds);
00185                 break;
00186         
00187         case 0x08:
00188                 off=reg_eax+(Bit32u)Fetchbs();
00189                 seg_base=SegBase(ds);
00190                 break;
00191         case 0x09:
00192                 off=reg_ecx+(Bit32u)Fetchbs();
00193                 seg_base=SegBase(ds);
00194                 break;
00195         case 0x0a:
00196                 off=reg_edx+(Bit32u)Fetchbs();
00197                 seg_base=SegBase(ds);
00198                 break;
00199         case 0x0b:
00200                 off=reg_ebx+(Bit32u)Fetchbs();
00201                 seg_base=SegBase(ds);
00202                 break;
00203         case 0x0c:
00204                 SIB(1);
00205                 off+=(Bit32u)Fetchbs();
00206                 break;
00207         case 0x0d:
00208                 off=reg_ebp+(Bit32u)Fetchbs();
00209                 seg_base=SegBase(ss);
00210                 break;
00211         case 0x0e:
00212                 off=reg_esi+(Bit32u)Fetchbs();
00213                 seg_base=SegBase(ds);
00214                 break;
00215         case 0x0f:
00216                 off=reg_edi+(Bit32u)Fetchbs();
00217                 seg_base=SegBase(ds);
00218                 break;
00219 
00220         case 0x10:
00221                 off=reg_eax+(Bit32u)Fetchds();
00222                 seg_base=SegBase(ds);
00223                 break;
00224         case 0x11:
00225                 off=reg_ecx+(Bit32u)Fetchds();
00226                 seg_base=SegBase(ds);
00227                 break;
00228         case 0x12:
00229                 off=reg_edx+(Bit32u)Fetchds();
00230                 seg_base=SegBase(ds);
00231                 break;
00232         case 0x13:
00233                 off=reg_ebx+(Bit32u)Fetchds();
00234                 seg_base=SegBase(ds);
00235                 break;
00236         case 0x14:
00237                 SIB(1);
00238                 off+=(Bit32u)Fetchds();
00239                 break;
00240         case 0x15:
00241                 off=reg_ebp+(Bit32u)Fetchds();
00242                 seg_base=SegBase(ss);
00243                 break;
00244         case 0x16:
00245                 off=reg_esi+(Bit32u)Fetchds();
00246                 seg_base=SegBase(ds);
00247                 break;
00248         case 0x17:
00249                 off=reg_edi+(Bit32u)Fetchds();
00250                 seg_base=SegBase(ds);
00251                 break;
00252         default:
00253                 off=seg_base=0;
00254                 break;
00255         }
00256         inst.rm_off=off;
00257         if (inst.prefix & PREFIX_SEG) {
00258                 inst.rm_eaa=inst.seg.base+off;
00259         } else {
00260                 inst.rm_eaa=seg_base+off;
00261         }
00262 }