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src/ints/int10_modes.cpp
00001 /*
00002  *  Copyright (C) 2002-2015  The DOSBox Team
00003  *
00004  *  This program is free software; you can redistribute it and/or modify
00005  *  it under the terms of the GNU General Public License as published by
00006  *  the Free Software Foundation; either version 2 of the License, or
00007  *  (at your option) any later version.
00008  *
00009  *  This program is distributed in the hope that it will be useful,
00010  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
00011  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
00012  *  GNU General Public License for more details.
00013  *
00014  *  You should have received a copy of the GNU General Public License
00015  *  along with this program; if not, write to the Free Software
00016  *  Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
00017  */
00018 
00019 
00020 #include <string.h>
00021 
00022 #include "dosbox.h"
00023 #include "mem.h"
00024 #include "inout.h"
00025 #include "int10.h"
00026 #include "mouse.h"
00027 #include "vga.h"
00028 #include "bios.h"
00029 #include "programs.h"
00030 
00031 #define SEQ_REGS 0x05
00032 #define GFX_REGS 0x09
00033 #define ATT_REGS 0x15
00034 
00035 extern bool int10_vesa_map_as_128kb;
00036 extern bool allow_vesa_lowres_modes;
00037 extern bool vesa12_modes_32bpp;
00038 extern bool allow_vesa_32bpp;
00039 extern bool allow_vesa_24bpp;
00040 extern bool allow_vesa_16bpp;
00041 extern bool allow_vesa_15bpp;
00042 extern bool allow_vesa_8bpp;
00043 extern bool allow_vesa_4bpp;
00044 extern bool allow_vesa_tty;
00045 
00046 VideoModeBlock ModeList_VGA[]={
00047 /* mode  ,type     ,sw  ,sh  ,tw ,th ,cw,ch ,pt,pstart  ,plength,htot,vtot,hde,vde special flags */
00048 { 0x000  ,M_TEXT   ,360 ,400 ,40 ,25 ,9 ,16 ,8 ,0xB8000 ,0x0800 ,50  ,449 ,40 ,400 ,_EGA_HALF_CLOCK     },
00049 { 0x001  ,M_TEXT   ,360 ,400 ,40 ,25 ,9 ,16 ,8 ,0xB8000 ,0x0800 ,50  ,449 ,40 ,400 ,_EGA_HALF_CLOCK     },
00050 { 0x002  ,M_TEXT   ,720 ,400 ,80 ,25 ,9 ,16 ,8 ,0xB8000 ,0x1000 ,100 ,449 ,80 ,400 ,0   },
00051 { 0x003  ,M_TEXT   ,720 ,400 ,80 ,25 ,9 ,16 ,8 ,0xB8000 ,0x1000 ,100 ,449 ,80 ,400 ,0   },
00052 { 0x004  ,M_CGA4   ,320 ,200 ,40 ,25 ,8 ,8  ,1 ,0xB8000 ,0x4000 ,50  ,449 ,40 ,400 ,_EGA_HALF_CLOCK     | _DOUBLESCAN | _REPEAT1},
00053 { 0x005  ,M_CGA4   ,320 ,200 ,40 ,25 ,8 ,8  ,1 ,0xB8000 ,0x4000 ,50  ,449 ,40 ,400 ,_EGA_HALF_CLOCK     | _DOUBLESCAN | _REPEAT1},
00054 { 0x006  ,M_CGA2   ,640 ,200 ,80 ,25 ,8 ,8  ,1 ,0xB8000 ,0x4000 ,100 ,449 ,80 ,400 ,_DOUBLESCAN | _REPEAT1},
00055 { 0x007  ,M_TEXT   ,720 ,400 ,80 ,25 ,9 ,16 ,8 ,0xB0000 ,0x1000 ,100 ,449 ,80 ,400 ,0   },
00056 
00057 { 0x00D  ,M_EGA    ,320 ,200 ,40 ,25 ,8 ,8  ,8 ,0xA0000 ,0x2000 ,50  ,449 ,40 ,400 ,_EGA_HALF_CLOCK     | _DOUBLESCAN   },
00058 { 0x00E  ,M_EGA    ,640 ,200 ,80 ,25 ,8 ,8  ,4 ,0xA0000 ,0x4000 ,100 ,449 ,80 ,400 ,_DOUBLESCAN },
00059 { 0x00F  ,M_EGA    ,640 ,350 ,80 ,25 ,8 ,14 ,2 ,0xA0000 ,0x8000 ,100 ,449 ,80 ,350 ,0   },/*was EGA_2*/
00060 { 0x010  ,M_EGA    ,640 ,350 ,80 ,25 ,8 ,14 ,2 ,0xA0000 ,0x8000 ,100 ,449 ,80 ,350 ,0   },
00061 { 0x011  ,M_EGA    ,640 ,480 ,80 ,30 ,8 ,16 ,1 ,0xA0000 ,0xA000 ,100 ,525 ,80 ,480 ,0   },/*was EGA_2 */
00062 { 0x012  ,M_EGA    ,640 ,480 ,80 ,30 ,8 ,16 ,1 ,0xA0000 ,0xA000 ,100 ,525 ,80 ,480 ,0   },
00063 { 0x013  ,M_VGA    ,320 ,200 ,40 ,25 ,8 ,8  ,1 ,0xA0000 ,0x2000 ,100 ,449 ,80 ,400 ,_REPEAT1   },
00064 
00065 { 0x054  ,M_TEXT   ,1056,344, 132,43, 8,  8, 1 ,0xB8000 ,0x4000, 160, 449, 132,344, 0   },
00066 { 0x055  ,M_TEXT   ,1056,400, 132,25, 8, 16, 1 ,0xB8000 ,0x2000, 160, 449, 132,400, 0   },
00067 
00068 /* Alias of mode 101 */
00069 { 0x069  ,M_LIN8   ,640 ,480 ,80 ,30 ,8 ,16 ,1 ,0xA0000 ,0x10000,100 ,525 ,80 ,480 ,0   },
00070 /* Alias of mode 102 */
00071 { 0x06A  ,M_LIN4   ,800 ,600 ,100,37 ,8 ,16 ,1 ,0xA0000 ,0x10000,128 ,663 ,100,600 ,0   },
00072 
00073 /* Follow vesa 1.2 for first 0x20 */
00074 { 0x100  ,M_LIN8   ,640 ,400 ,80 ,25 ,8 ,16 ,1 ,0xA0000 ,0x10000,100 ,449 ,80 ,400 ,0   },
00075 { 0x101  ,M_LIN8   ,640 ,480 ,80 ,30 ,8 ,16 ,1 ,0xA0000 ,0x10000,100 ,525 ,80 ,480 , _VGA_PIXEL_DOUBLE },
00076 { 0x102  ,M_LIN4   ,800 ,600 ,100,37 ,8 ,16 ,1 ,0xA0000 ,0x10000,132 ,628 ,100,600 ,0   },
00077 { 0x103  ,M_LIN8   ,800 ,600 ,100,37 ,8 ,16 ,1 ,0xA0000 ,0x10000,132 ,628 ,100,600 ,0   },
00078 { 0x104  ,M_LIN4   ,1024,768 ,128,48 ,8 ,16 ,1 ,0xA0000 ,0x10000,168 ,806 ,128,768 ,0   },
00079 { 0x105  ,M_LIN8   ,1024,768 ,128,48 ,8 ,16 ,1 ,0xA0000 ,0x10000,168 ,806 ,128,768 ,0   },
00080 { 0x106  ,M_LIN4   ,1280,1024,160,64 ,8 ,16 ,1 ,0xA0000 ,0x10000,212 ,1066,160,1024,0   },
00081 { 0x107  ,M_LIN8   ,1280,1024,160,64 ,8 ,16 ,1 ,0xA0000 ,0x10000,212 ,1066,160,1024,0   },
00082 
00083 /* VESA text modes */ 
00084 { 0x108  ,M_TEXT   ,640 ,480,  80,60, 8,  8 ,2 ,0xB8000 ,0x4000, 100 ,525 ,80 ,480 ,0   },
00085 { 0x109  ,M_TEXT   ,1056,400, 132,25, 8, 16, 1 ,0xB8000 ,0x2000, 160, 449, 132,400, 0   },
00086 { 0x10A  ,M_TEXT   ,1056,688, 132,43, 8,  8, 1 ,0xB8000 ,0x4000, 160, 449, 132,344, 0   },
00087 { 0x10B  ,M_TEXT   ,1056,400, 132,50, 8,  8, 1 ,0xB8000 ,0x4000, 160, 449, 132,400, 0   },
00088 { 0x10C  ,M_TEXT   ,1056,480, 132,60, 8,  8, 2 ,0xB8000 ,0x4000, 160, 531, 132,480, 0   },
00089 
00090 /* VESA higher color modes.
00091  * Note v1.2 of the VESA BIOS extensions explicitly states modes 0x10F, 0x112, 0x115, 0x118 are 8:8:8 (24-bit) not 8:8:8:8 (32-bit).
00092  * This also fixes COMA "Parhaat" 1997 demo, by offering a true 24bpp mode so that it doesn't try to draw 24bpp on a 32bpp VESA linear framebuffer.
00093  * NTS: The 24bpp modes listed here will not be available to the DOS game/demo if the user says that the VBE 1.2 modes are 32bpp,
00094  *      instead the redefinitions in the next block will apply to allow M_LIN32. To use the 24bpp modes here, you must set 'vesa vbe 1.2 modes are 32bpp=false' */
00095 { 0x10D  ,M_LIN15  ,320 ,200 ,40 ,25 ,8 ,8  ,1 ,0xA0000 ,0x10000,100 ,449 ,80 ,400 , _REPEAT1 },
00096 { 0x10E  ,M_LIN16  ,320 ,200 ,40 ,25 ,8 ,8  ,1 ,0xA0000 ,0x10000,100 ,449 ,80 ,400 , _REPEAT1 },
00097 { 0x10F  ,M_LIN24  ,320 ,200 ,40 ,25 ,8 ,8  ,1 ,0xA0000 ,0x10000,50  ,449 ,40 ,400 , _REPEAT1 },
00098 { 0x110  ,M_LIN15  ,640 ,480 ,80 ,30 ,8 ,16 ,1 ,0xA0000 ,0x10000,200 ,525 ,160,480 ,0   },
00099 { 0x111  ,M_LIN16  ,640 ,480 ,80 ,30 ,8 ,16 ,1 ,0xA0000 ,0x10000,200 ,525 ,160,480 ,0   },
00100 { 0x112  ,M_LIN24  ,640 ,480 ,80 ,30 ,8 ,16 ,1 ,0xA0000 ,0x10000,100 ,525 ,80 ,480 ,0   },
00101 { 0x113  ,M_LIN15  ,800 ,600 ,100,37 ,8 ,16 ,1 ,0xA0000 ,0x10000,264 ,628 ,200,600 ,0   },
00102 { 0x114  ,M_LIN16  ,800 ,600 ,100,37 ,8 ,16 ,1 ,0xA0000 ,0x10000,264 ,628 ,200,600 ,0   },
00103 { 0x115  ,M_LIN24  ,800 ,600 ,100,37 ,8 ,16 ,1 ,0xA0000 ,0x10000,132 ,628 ,100,600 ,0   },
00104 { 0x116  ,M_LIN15  ,1024,768 ,128,48 ,8 ,16 ,1 ,0xA0000 ,0x10000,336 ,806 ,256,768 ,0   },
00105 { 0x117  ,M_LIN16  ,1024,768 ,128,48 ,8 ,16 ,1 ,0xA0000 ,0x10000,336 ,806 ,256,768 ,0   },
00106 { 0x118  ,M_LIN24  ,1024,768 ,128,48 ,8 ,16 ,1 ,0xA0000 ,0x10000,168 ,806 ,128,768 ,0   },
00107 
00108 /* But of course... there are other demos that assume mode 0x10F is 32bpp!
00109  * So we have another definition of those modes that overlaps some of the same mode numbers above.
00110  * This allows "Phenomena" demo to use 32bpp 320x200 mode if you set 'vesa vbe 1.2 modes are 32bpp=true'.
00111  * The code will allow either this block's mode 0x10F (LIN32), or the previous block's mode 0x10F (LIN24), but not both. */
00112 { 0x10F  ,M_LIN32  ,320 ,200 ,40 ,25 ,8 ,8  ,1 ,0xA0000 ,0x10000,50  ,449 ,40 ,400 , _REPEAT1 },
00113 { 0x112  ,M_LIN32  ,640 ,480 ,80 ,30 ,8 ,16 ,1 ,0xA0000 ,0x10000,100 ,525 ,80 ,480 ,0   },
00114 { 0x115  ,M_LIN32  ,800 ,600 ,100,37 ,8 ,16 ,1 ,0xA0000 ,0x10000,132 ,628 ,100,600 ,0   },
00115 { 0x118  ,M_LIN32  ,1024,768 ,128,48 ,8 ,16 ,1 ,0xA0000 ,0x10000,168 ,806 ,128,768 ,0   },
00116 
00117 /* RGBX 8:8:8:8 modes. These were once the M_LIN32 modes DOSBox mapped to 0x10F-0x11B prior to implementing M_LIN24. */
00118 { 0x210  ,M_LIN32  ,320 ,200 ,40 ,25 ,8 ,8  ,1 ,0xA0000 ,0x10000,50  ,449 ,40 ,400 , _REPEAT1 },
00119 { 0x211  ,M_LIN32  ,640 ,480 ,80 ,30 ,8 ,16 ,1 ,0xA0000 ,0x10000,100 ,525 ,80 ,480 ,0   },
00120 { 0x212  ,M_LIN32  ,800 ,600 ,100,37 ,8 ,16 ,1 ,0xA0000 ,0x10000,132 ,628 ,100,600 ,0   },
00121 { 0x214  ,M_LIN32  ,1024,768 ,128,48 ,8 ,16 ,1 ,0xA0000 ,0x10000,168 ,806 ,128,768 ,0   },
00122 
00123 { 0x215  ,M_LIN24  ,320 ,200 ,40 ,25 ,8 ,8  ,1 ,0xA0000 ,0x10000,50  ,449 ,40 ,400 , _REPEAT1 },
00124 { 0x216  ,M_LIN24  ,640 ,480 ,80 ,30 ,8 ,16 ,1 ,0xA0000 ,0x10000,100 ,525 ,80 ,480 ,0   },
00125 { 0x217  ,M_LIN24  ,800 ,600 ,100,37 ,8 ,16 ,1 ,0xA0000 ,0x10000,132 ,628 ,100,600 ,0   },
00126 { 0x218  ,M_LIN24  ,1024,768 ,128,48 ,8 ,16 ,1 ,0xA0000 ,0x10000,168 ,806 ,128,768 ,0   },
00127 
00128 /* those should be interlaced but ok */
00129 { 0x119  ,M_LIN15  ,1280,1024,160,64 ,8 ,16 ,1 ,0xA0000 ,0x10000,424 ,1066,320,1024,0   },
00130 { 0x11A  ,M_LIN16  ,1280,1024,160,64 ,8 ,16 ,1 ,0xA0000 ,0x10000,424 ,1066,320,1024,0   },
00131 
00132 { 0x11C  ,M_LIN8   ,640 ,350 ,80 ,25 ,8 ,14 ,2 ,0xA0000 ,0x10000,100 ,449 ,80 ,350 ,0   },
00133 // special mode for Birth demo by Incognita
00134 { 0x11D  ,M_LIN15  ,640 ,350 ,80 ,25 ,8 ,14 ,1 ,0xA0000 ,0x10000,200 ,449 ,160,350 ,0   },
00135 { 0x11F  ,M_LIN16  ,640 ,350 ,80 ,25 ,8 ,14 ,1 ,0xA0000 ,0x10000,200 ,449 ,160,350 ,0   },
00136 { 0x120  ,M_LIN8   ,1600,1200,200,75 ,8 ,16 ,1 ,0xA0000 ,0x10000,264 ,1240,200,1200,0   },
00137 { 0x142  ,M_LIN32  ,640 ,350 ,80 ,25 ,8 ,14 ,2 ,0xA0000 ,0x10000 ,100 ,449 ,80 ,350 ,0  },
00138 
00139 // FIXME: Find an old S3 Trio and dump the VESA modelist, then arrange this modelist to match
00140 { 0x150  ,M_LIN8   ,320 ,480 ,40 ,60 ,8 ,8  ,1 ,0xA0000 ,0x10000,100 ,525 ,80 ,480 , _S3_PIXEL_DOUBLE  },
00141 { 0x151  ,M_LIN8   ,320 ,240 ,40 ,30 ,8 ,8  ,1 ,0xA0000 ,0x10000,100 ,525 ,80 ,480 , _S3_PIXEL_DOUBLE | _REPEAT1 },
00142 { 0x152  ,M_LIN8   ,320 ,400 ,40 ,50 ,8 ,8  ,1 ,0xA0000 ,0x10000,100 ,449 ,80 ,400 , _S3_PIXEL_DOUBLE  },
00143 // For S3 Trio emulation this mode must exist as mode 0x153 else RealTech "Countdown" will crash
00144 // if you select VGA 320x200 with S3 acceleration.
00145 { 0x153  ,M_LIN8   ,320 ,200 ,40 ,25 ,8 ,8  ,1 ,0xA0000 ,0x10000,100 ,449 ,80 ,400 , _S3_PIXEL_DOUBLE | _REPEAT1 },
00146 
00147 { 0x15C ,M_LIN8,    512 ,384 ,64 ,48 ,8, 8  ,1 ,0xA0000 ,0x10000,168 ,806 ,128,768 , _S3_PIXEL_DOUBLE | _DOUBLESCAN },
00148 { 0x159 ,M_LIN8,    400 ,300 ,50 ,37 ,8 ,8  ,1 ,0xA0000 ,0x10000,132 ,628 ,100,600 , _S3_PIXEL_DOUBLE | _DOUBLESCAN },
00149 { 0x15D ,M_LIN16,   512 ,384 ,64 ,48 ,8, 16 ,1 ,0xA0000 ,0x10000,168 ,806 ,128,768 , _S3_PIXEL_DOUBLE | _DOUBLESCAN },
00150 { 0x15A ,M_LIN16,   400 ,300 ,50 ,37 ,8 ,16 ,1 ,0xA0000 ,0x10000,132 ,628 ,100,600 , _S3_PIXEL_DOUBLE | _DOUBLESCAN },
00151 
00152 { 0x160  ,M_LIN15  ,320 ,240 ,40 ,30 ,8 ,8  ,1 ,0xA0000 ,0x10000,100 ,525 , 80 ,480 , _REPEAT1 },
00153 { 0x161  ,M_LIN15  ,320 ,400 ,40 ,50 ,8 ,8  ,1 ,0xA0000 ,0x10000,100 ,449 , 80 ,400 ,0 },
00154 { 0x162  ,M_LIN15  ,320 ,480 ,40 ,60 ,8 ,8  ,1 ,0xA0000 ,0x10000,100 ,525 , 80 ,480 ,0 },
00155 { 0x165  ,M_LIN15  ,640 ,400 ,80 ,25 ,8 ,16 ,1 ,0xA0000 ,0x10000,200 ,449 ,160 ,400 ,0   },
00156 
00157 // hack: 320x200x16bpp for "Process" demo (1997) with apparently hard-coded VBE mode
00158 { 0x136  ,M_LIN16  ,320 ,240 ,40 ,30 ,8 ,8  ,1 ,0xA0000 ,0x10000,100 ,525 , 80 ,480 , _REPEAT1 },
00159 
00160 // hack: 320x480x256-color alias for Habitual demo. doing this removes the need to run S3VBE20.EXE before running the demo.
00161 //       the reason it has to be this particular video mode is because HABITUAL.EXE does not query modes, it simply assumes
00162 //       that mode 0x166 is this particular mode and errors out if it can't set it.
00163 { 0x166  ,M_LIN8   ,320 ,480 ,40 ,60 ,8 ,8  ,1 ,0xA0000 ,0x10000,100 ,525 ,80 ,480 , _S3_PIXEL_DOUBLE  },
00164 
00165 { 0x170  ,M_LIN16  ,320 ,240 ,40 ,30 ,8 ,8  ,1 ,0xA0000 ,0x10000,100 ,525 , 80 ,480 , _REPEAT1 },
00166 { 0x171  ,M_LIN16  ,320 ,400 ,40 ,50 ,8 ,8  ,1 ,0xA0000 ,0x10000,100 ,449 , 80 ,400 ,0 },
00167 { 0x172  ,M_LIN16  ,320 ,480 ,40 ,60 ,8 ,8  ,1 ,0xA0000 ,0x10000,100 ,525 , 80 ,480 ,0 },
00168 { 0x175  ,M_LIN16  ,640 ,400 ,80 ,25 ,8 ,16 ,1 ,0xA0000 ,0x10000,200 ,449 ,160 ,400 ,0   },
00169 
00170 { 0x190  ,M_LIN32  ,320 ,240 ,40 ,30 ,8 ,8  ,1 ,0xA0000 ,0x10000, 50 ,525 ,40 ,480 , _REPEAT1 },
00171 { 0x191  ,M_LIN32  ,320 ,400 ,40 ,50 ,8 ,8  ,1 ,0xA0000 ,0x10000, 50 ,449 ,40 ,400 ,0 },
00172 { 0x192  ,M_LIN32  ,320 ,480 ,40 ,60 ,8 ,8  ,1 ,0xA0000 ,0x10000, 50 ,525 ,40 ,480 ,0 },
00173 
00174 // S3 specific modes
00175 { 0x207  ,M_LIN8        ,1152,864,160,64 ,8 ,16 ,1 ,0xA0000 ,0x10000,182 ,948 ,144,864 ,0       },
00176 { 0x209  ,M_LIN15       ,1152,864,160,64 ,8 ,16 ,1 ,0xA0000 ,0x10000,364 ,948 ,288,864 ,0       },
00177 { 0x20A  ,M_LIN16       ,1152,864,160,64 ,8 ,16 ,1 ,0xA0000 ,0x10000,364 ,948 ,288,864 ,0       },
00178 { 0x20B  ,M_LIN32       ,1152, 864,160,64 ,8 ,16 ,1 ,0xA0000 ,0x10000,182 ,948 ,144,864 ,0      },
00179 { 0x213  ,M_LIN32   ,640 ,400,80 ,25 ,8 ,16 ,1 ,0xA0000 ,0x10000,100 ,449 ,80 ,400 ,0   },
00180 
00181 // Some custom modes
00182 
00183 // 720x480 3:2 modes
00184 { 0x21B  ,M_LIN4   ,720 ,480 ,90 ,30 ,8 ,16 ,1 ,0xA0000 ,0x10000,132 ,525 ,90  ,480 ,0  },
00185 { 0x21C  ,M_LIN8   ,720 ,480 ,90 ,30 ,8 ,16 ,1 ,0xA0000 ,0x10000,132 ,525 ,90  ,480 ,0  },
00186 { 0x21D  ,M_LIN15  ,720 ,480 ,90 ,30 ,8 ,16 ,1 ,0xA0000 ,0x10000,264 ,525 ,180 ,480 ,0  },
00187 { 0x21E  ,M_LIN16  ,720 ,480 ,90 ,30 ,8 ,16 ,1 ,0xA0000 ,0x10000,264 ,525 ,180 ,480 ,0  },
00188 { 0x21F  ,M_LIN32  ,720 ,480 ,90 ,30 ,8 ,16 ,1 ,0xA0000 ,0x10000,132 ,525 ,90  ,480 ,0  },
00189 
00190 // 848x480 16:9 modes
00191 { 0x220  ,M_LIN4   ,848 ,480 ,106,30 ,8 ,16 ,1 ,0xA0000 ,0x10000,132 ,525 ,106 ,480 ,0  },
00192 { 0x221  ,M_LIN8   ,848 ,480 ,106,30 ,8 ,16 ,1 ,0xA0000 ,0x10000,132 ,525 ,106 ,480 ,0  },
00193 { 0x222  ,M_LIN15  ,848 ,480 ,106,30 ,8 ,16 ,1 ,0xA0000 ,0x10000,264 ,525 ,212 ,480 ,0  },
00194 { 0x223  ,M_LIN16  ,848 ,480 ,106,30 ,8 ,16 ,1 ,0xA0000 ,0x10000,264 ,525 ,212 ,480 ,0  },
00195 { 0x224  ,M_LIN32  ,848 ,480 ,106,30 ,8 ,16 ,1 ,0xA0000 ,0x10000,132 ,525 ,106 ,480 ,0  },
00196 
00197 // 1280x800 8:5 modes
00198 { 0x225  ,M_LIN4   ,1280,800 ,160,50 ,8 ,16 ,1 ,0xA0000 ,0x10000,200 ,880 ,160 ,800 ,0  },
00199 { 0x226  ,M_LIN8   ,1280,800 ,160,50 ,8 ,16 ,1 ,0xA0000 ,0x10000,200 ,880 ,160 ,800 ,0  },
00200 { 0x227  ,M_LIN15  ,1280,800 ,160,50 ,8 ,16 ,1 ,0xA0000 ,0x10000,400 ,880 ,320 ,800 ,0  },
00201 { 0x228  ,M_LIN16  ,1280,800 ,160,50 ,8 ,16 ,1 ,0xA0000 ,0x10000,400 ,880 ,320 ,800 ,0  },
00202 { 0x229  ,M_LIN32  ,1280,800 ,160,50 ,8 ,16 ,1 ,0xA0000 ,0x10000,200 ,880 ,160 ,800 ,0  },
00203 { 0x300  ,M_LIN24  ,1280,800 ,160,50 ,8 ,16 ,1 ,0xA0000 ,0x10000,200 ,880 ,160 ,800 ,0  },
00204 
00205 // 1280x960 4:3 modes
00206 { 0x22a  ,M_LIN4   ,1280,960 ,160,60 ,8 ,16 ,1 ,0xA0000 ,0x10000,200 ,1020,160 ,960 ,0  },
00207 { 0x22b  ,M_LIN8   ,1280,960 ,160,60 ,8 ,16 ,1 ,0xA0000 ,0x10000,200 ,1020,160 ,960 ,0  },
00208 { 0x22c  ,M_LIN15  ,1280,960 ,160,60 ,8 ,16 ,1 ,0xA0000 ,0x10000,400 ,1020,320 ,960 ,0  },
00209 { 0x22d  ,M_LIN16  ,1280,960 ,160,60 ,8 ,16 ,1 ,0xA0000 ,0x10000,400 ,1020,320 ,960 ,0  },
00210 { 0x22e  ,M_LIN32  ,1280,960 ,160,60 ,8 ,16 ,1 ,0xA0000 ,0x10000,200 ,1020,160 ,960 ,0  },
00211 { 0x301  ,M_LIN24  ,1280,960 ,160,60 ,8 ,16 ,1 ,0xA0000 ,0x10000,200 ,1020,160 ,960 ,0  },
00212 
00213 // 1280x1024 5:4 rest
00214 { 0x22f  ,M_LIN32  ,1280,1024,160,64 ,8 ,16 ,1 ,0xA0000 ,0x10000,212 ,1066,160,1024,0   },
00215 { 0x302  ,M_LIN24  ,1280,1024,160,64 ,8 ,16 ,1 ,0xA0000 ,0x10000,212 ,1066,160,1024,0   },
00216 
00217 // 1400x1050 4:3 - 4bpp requires a hdisplayend value that is even, so round up
00218 { 0x250  ,M_LIN4   ,1400,1050,175,66 ,8 ,16 ,1 ,0xA0000 ,0x10000,220 ,1100,176 ,1050,0  },
00219 { 0x230  ,M_LIN8   ,1400,1050,175,66 ,8 ,16 ,1 ,0xA0000 ,0x10000,220 ,1100,175 ,1050,0  },
00220 { 0x231  ,M_LIN15  ,1400,1050,175,66 ,8 ,16 ,1 ,0xA0000 ,0x10000,440 ,1100,350 ,1050,0  },
00221 { 0x232  ,M_LIN16  ,1400,1050,175,66 ,8 ,16 ,1 ,0xA0000 ,0x10000,440 ,1100,350 ,1050,0  },
00222 { 0x233  ,M_LIN32  ,1400,1050,175,66 ,8 ,16 ,1 ,0xA0000 ,0x10000,220 ,1100,175 ,1050,0  },
00223 { 0x303  ,M_LIN24  ,1400,1050,175,66 ,8 ,16 ,1 ,0xA0000 ,0x10000,220 ,1100,175 ,1050,0  },
00224 
00225 // 1440x900 8:5 modes
00226 { 0x234  ,M_LIN4   ,1440, 900,180,56 ,8 ,16 ,1 ,0xA0000 ,0x10000,220 , 980,180 , 900,0  },
00227 { 0x235  ,M_LIN8   ,1440, 900,180,56 ,8 ,16 ,1 ,0xA0000 ,0x10000,220 , 980,180 , 900,0  },
00228 { 0x236  ,M_LIN15  ,1440, 900,180,56 ,8 ,16 ,1 ,0xA0000 ,0x10000,440 , 980,360 , 900,0  },
00229 { 0x237  ,M_LIN16  ,1440, 900,180,56 ,8 ,16 ,1 ,0xA0000 ,0x10000,440 , 980,360 , 900,0  },
00230 { 0x238  ,M_LIN32  ,1440, 900,180,56 ,8 ,16 ,1 ,0xA0000 ,0x10000,220 , 980,180 , 900,0  },
00231 
00232 // 1600x1200 4:3 rest - 32bpp needs more than 4 megs
00233 { 0x239  ,M_LIN4   ,1600,1200,200,75 ,8 ,16 ,1 ,0xA0000 ,0x10000,264 ,1240,200, 1200,0  },
00234 { 0x23a  ,M_LIN15  ,1600,1200,200,75 ,8 ,16 ,1 ,0xA0000 ,0x10000,500 ,1240,400 ,1200,0  },
00235 { 0x23b  ,M_LIN16  ,1600,1200,200,75 ,8 ,16 ,1 ,0xA0000 ,0x10000,500 ,1240,400 ,1200,0  },
00236 { 0x23c  ,M_LIN32  ,1600,1200,200,75 ,8 ,16 ,1 ,0xA0000 ,0x10000,264 ,1240,200 ,1200,0  },
00237 
00238 // 1280x720 16:9 modes
00239 { 0x23D  ,M_LIN4   ,1280,720 ,160,45 ,8 ,16 ,1 ,0xA0000 ,0x10000,176 ,792 ,160 ,720 ,0  },
00240 { 0x23E  ,M_LIN8   ,1280,720 ,160,45 ,8 ,16 ,1 ,0xA0000 ,0x10000,176 ,792 ,160 ,720 ,0  },
00241 { 0x23F  ,M_LIN15  ,1280,720 ,160,45 ,8 ,16 ,1 ,0xA0000 ,0x10000,352 ,792 ,320 ,720 ,0  },
00242 { 0x240  ,M_LIN16  ,1280,720 ,160,45 ,8 ,16 ,1 ,0xA0000 ,0x10000,352 ,792 ,320 ,720 ,0  },
00243 { 0x241  ,M_LIN32  ,1280,720 ,160,45 ,8 ,16 ,1 ,0xA0000 ,0x10000,176 ,792 ,160 ,720 ,0  },
00244 { 0x303  ,M_LIN24  ,1280,720 ,160,45 ,8 ,16 ,1 ,0xA0000 ,0x10000,176 ,792 ,160 ,720 ,0  },
00245 
00246 // 1920x1080 16:9 modes
00247 { 0x242  ,M_LIN4   ,1920,1080,240,67 ,8 ,16 ,1 ,0xA0000 ,0x10000,264 ,1188,240 ,1080,0  },
00248 { 0x243  ,M_LIN8   ,1920,1080,240,67 ,8 ,16 ,1 ,0xA0000 ,0x10000,264 ,1188,240 ,1080,0  },
00249 { 0x244  ,M_LIN15  ,1920,1080,240,67 ,8 ,16 ,1 ,0xA0000 ,0x10000,528 ,1188,480 ,1080,0  },
00250 { 0x245  ,M_LIN16  ,1920,1080,240,67 ,8 ,16 ,1 ,0xA0000 ,0x10000,528 ,1188,480 ,1080,0  },
00251 { 0x246  ,M_LIN32  ,1920,1080,240,67 ,8 ,16 ,1 ,0xA0000 ,0x10000,264 ,1188,240 ,1080,0  },
00252 { 0x304  ,M_LIN24  ,1920,1080,240,67 ,8 ,16 ,1 ,0xA0000 ,0x10000,264 ,1188,240 ,1080,0  },
00253 
00254 // 960x720 4:3 modes
00255 { 0x247  ,M_LIN4   ,960,720 ,160,45 ,8 ,16 ,1 ,0xA0000 ,0x10000,144 ,792 ,120 ,720 ,0   },
00256 { 0x248  ,M_LIN8   ,960,720 ,160,45 ,8 ,16 ,1 ,0xA0000 ,0x10000,144 ,792 ,120 ,720 ,0   },
00257 { 0x249  ,M_LIN15  ,960,720 ,160,45 ,8 ,16 ,1 ,0xA0000 ,0x10000,288 ,792 ,240 ,720 ,0  },
00258 { 0x24A  ,M_LIN16  ,960,720 ,160,45 ,8 ,16 ,1 ,0xA0000 ,0x10000,288 ,792 ,240 ,720 ,0  },
00259 { 0x24B  ,M_LIN32  ,960,720 ,160,45 ,8 ,16 ,1 ,0xA0000 ,0x10000,144 ,792 ,120 ,720 ,0  },
00260 
00261 // 1440x1080 16:9 modes
00262 { 0x24C  ,M_LIN4   ,1440,1080,240,67 ,8 ,16 ,1 ,0xA0000 ,0x10000,200 ,1188,180 ,1080,0  },
00263 { 0x24D  ,M_LIN8   ,1440,1080,240,67 ,8 ,16 ,1 ,0xA0000 ,0x10000,200 ,1188,180 ,1080,0  },
00264 { 0x24E  ,M_LIN15  ,1440,1080,240,67 ,8 ,16 ,1 ,0xA0000 ,0x10000,400 ,1188,360 ,1080,0  },
00265 { 0x24F  ,M_LIN16  ,1440,1080,240,67 ,8 ,16 ,1 ,0xA0000 ,0x10000,400 ,1188,360 ,1080,0  },
00266 { 0x2F0  ,M_LIN32  ,1440,1080,240,67 ,8 ,16 ,1 ,0xA0000 ,0x10000,200 ,1188,180 ,1080,0  },
00267 
00268 {0xFFFF  ,M_ERROR  ,0   ,0   ,0  ,0  ,0 ,0  ,0 ,0x00000 ,0x0000 ,0   ,0   ,0  ,0   ,0   },
00269 };
00270 
00271 VideoModeBlock ModeList_VGA_Text_200lines[]={
00272 /* mode  ,type     ,sw  ,sh  ,tw ,th ,cw,ch ,pt,pstart  ,plength,htot,vtot,hde,vde special flags */
00273 { 0x000  ,M_TEXT   ,320 ,200 ,40 ,25 ,8 , 8 ,8 ,0xB8000 ,0x0800 ,50  ,449 ,40 ,400 ,_EGA_HALF_CLOCK | _DOUBLESCAN},
00274 { 0x001  ,M_TEXT   ,320 ,200 ,40 ,25 ,8 , 8 ,8 ,0xB8000 ,0x0800 ,50  ,449 ,40 ,400 ,_EGA_HALF_CLOCK | _DOUBLESCAN},
00275 { 0x002  ,M_TEXT   ,640 ,200 ,80 ,25 ,8 , 8 ,8 ,0xB8000 ,0x1000 ,100 ,449 ,80 ,400 ,_DOUBLESCAN },
00276 { 0x003  ,M_TEXT   ,640 ,200 ,80 ,25 ,8 , 8 ,8 ,0xB8000 ,0x1000 ,100 ,449 ,80 ,400 ,_DOUBLESCAN }
00277 };
00278 
00279 VideoModeBlock ModeList_VGA_Text_350lines[]={
00280 /* mode  ,type     ,sw  ,sh  ,tw ,th ,cw,ch ,pt,pstart  ,plength,htot,vtot,hde,vde special flags */
00281 { 0x000  ,M_TEXT   ,320 ,350 ,40 ,25 ,8 ,14 ,8 ,0xB8000 ,0x0800 ,50  ,449 ,40 ,350 ,_EGA_HALF_CLOCK     },
00282 { 0x001  ,M_TEXT   ,320 ,350 ,40 ,25 ,8 ,14 ,8 ,0xB8000 ,0x0800 ,50  ,449 ,40 ,350 ,_EGA_HALF_CLOCK     },
00283 { 0x002  ,M_TEXT   ,640 ,350 ,80 ,25 ,8 ,14 ,8 ,0xB8000 ,0x1000 ,100 ,449 ,80 ,350 ,0   },
00284 { 0x003  ,M_TEXT   ,640 ,350 ,80 ,25 ,8 ,14 ,8 ,0xB8000 ,0x1000 ,100 ,449 ,80 ,350 ,0   },
00285 { 0x007  ,M_TEXT   ,720 ,350 ,80 ,25 ,9 ,14 ,8 ,0xB0000 ,0x1000 ,100 ,449 ,80 ,350 ,0   }
00286 };
00287 
00288 VideoModeBlock ModeList_VGA_Tseng[]={
00289 /* mode  ,type     ,sw  ,sh  ,tw ,th ,cw,ch ,pt,pstart  ,plength,htot,vtot,hde,vde special flags */
00290 { 0x000  ,M_TEXT   ,360 ,400 ,40 ,25 ,9 ,16 ,8 ,0xB8000 ,0x0800 ,50  ,449 ,40 ,400 ,_EGA_HALF_CLOCK     },
00291 { 0x001  ,M_TEXT   ,360 ,400 ,40 ,25 ,9 ,16 ,8 ,0xB8000 ,0x0800 ,50  ,449 ,40 ,400 ,_EGA_HALF_CLOCK     },
00292 { 0x002  ,M_TEXT   ,720 ,400 ,80 ,25 ,9 ,16 ,8 ,0xB8000 ,0x1000 ,100 ,449 ,80 ,400 ,0   },
00293 { 0x003  ,M_TEXT   ,720 ,400 ,80 ,25 ,9 ,16 ,8 ,0xB8000 ,0x1000 ,100 ,449 ,80 ,400 ,0   },
00294 { 0x004  ,M_CGA4   ,320 ,200 ,40 ,25 ,8 ,8  ,1 ,0xB8000 ,0x4000 ,50  ,449 ,40 ,400 ,_EGA_HALF_CLOCK     | _DOUBLESCAN | _REPEAT1},
00295 { 0x005  ,M_CGA4   ,320 ,200 ,40 ,25 ,8 ,8  ,1 ,0xB8000 ,0x4000 ,50  ,449 ,40 ,400 ,_EGA_HALF_CLOCK     | _DOUBLESCAN | _REPEAT1},
00296 { 0x006  ,M_CGA2   ,640 ,200 ,80 ,25 ,8 ,8  ,1 ,0xB8000 ,0x4000 ,100 ,449 ,80 ,400 ,_DOUBLESCAN | _REPEAT1},
00297 { 0x007  ,M_TEXT   ,720 ,400 ,80 ,25 ,9 ,16 ,8 ,0xB0000 ,0x1000 ,100 ,449 ,80 ,400 ,0   },
00298 
00299 { 0x00D  ,M_EGA    ,320 ,200 ,40 ,25 ,8 ,8  ,8 ,0xA0000 ,0x2000 ,50  ,449 ,40 ,400 ,_EGA_HALF_CLOCK     | _DOUBLESCAN   },
00300 { 0x00E  ,M_EGA    ,640 ,200 ,80 ,25 ,8 ,8  ,4 ,0xA0000 ,0x4000 ,100 ,449 ,80 ,400 ,_DOUBLESCAN },
00301 { 0x00F  ,M_EGA    ,640 ,350 ,80 ,25 ,8 ,14 ,2 ,0xA0000 ,0x8000 ,100 ,449 ,80 ,350 ,0   },
00302 { 0x010  ,M_EGA    ,640 ,350 ,80 ,25 ,8 ,14 ,2 ,0xA0000 ,0x8000 ,100 ,449 ,80 ,350 ,0   },
00303 { 0x011  ,M_EGA    ,640 ,480 ,80 ,30 ,8 ,16 ,1 ,0xA0000 ,0xA000 ,100 ,525 ,80 ,480 ,0   },
00304 { 0x012  ,M_EGA    ,640 ,480 ,80 ,30 ,8 ,16 ,1 ,0xA0000 ,0xA000 ,100 ,525 ,80 ,480 ,0   },
00305 { 0x013  ,M_VGA    ,320 ,200 ,40 ,25 ,8 ,8  ,1 ,0xA0000 ,0x2000 ,100 ,449 ,80 ,400 ,_REPEAT1   },
00306 
00307 { 0x018  ,M_TEXT   ,1056 ,688, 132,44, 8, 8, 1 ,0xB0000 ,0x4000, 192, 800, 132, 704, 0 },
00308 { 0x019  ,M_TEXT   ,1056 ,400, 132,25, 8, 16,1 ,0xB0000 ,0x2000, 192, 449, 132, 400, 0 },
00309 { 0x01A  ,M_TEXT   ,1056 ,400, 132,28, 8, 16,1 ,0xB0000 ,0x2000, 192, 449, 132, 448, 0 },
00310 { 0x022  ,M_TEXT   ,1056 ,688, 132,44, 8, 8, 1 ,0xB8000 ,0x4000, 192, 800, 132, 704, 0 },
00311 { 0x023  ,M_TEXT   ,1056 ,400, 132,25, 8, 16,1 ,0xB8000 ,0x2000, 192, 449, 132, 400, 0 },
00312 { 0x024  ,M_TEXT   ,1056 ,400, 132,28, 8, 16,1 ,0xB8000 ,0x2000, 192, 449, 132, 448, 0 },
00313 { 0x025  ,M_LIN4   ,640 ,480 ,80 ,30 ,8 ,16 ,1 ,0xA0000 ,0xA000 ,100 ,525 ,80 ,480 , 0 },
00314 { 0x029  ,M_LIN4   ,800 ,600 ,100,37 ,8 ,16 ,1 ,0xA0000 ,0xA000, 128 ,663 ,100,600 , 0 },
00315 { 0x02D  ,M_LIN8   ,640 ,350 ,80 ,21 ,8 ,16 ,1 ,0xA0000 ,0x10000,100 ,449 ,80 ,350 , 0 },
00316 { 0x02E  ,M_LIN8   ,640 ,480 ,80 ,30 ,8 ,16 ,1 ,0xA0000 ,0x10000,100 ,525 ,80 ,480 , 0 },
00317 { 0x02F  ,M_LIN8   ,640 ,400 ,80 ,25 ,8 ,16 ,1 ,0xA0000 ,0x10000,100 ,449 ,80 ,400 , 0 },/* ET4000 only */
00318 { 0x030  ,M_LIN8   ,800 ,600 ,100,37 ,8 ,16 ,1 ,0xA0000 ,0x10000,128 ,663 ,100,600 , 0 },
00319 { 0x036  ,M_LIN4   ,960 , 720,120,45 ,8 ,16 ,1 ,0xA0000 ,0xA000, 120 ,800 ,120,720 , 0 },/* STB only */
00320 { 0x037  ,M_LIN4   ,1024, 768,128,48 ,8 ,16 ,1 ,0xA0000 ,0xA000, 128 ,800 ,128,768 , 0 },
00321 { 0x038  ,M_LIN8   ,1024 ,768,128,48 ,8 ,16 ,1 ,0xA0000 ,0x10000,168 ,800 ,128,768 , 0 },/* ET4000 only */
00322 { 0x03D  ,M_LIN4   ,1280,1024,160,64 ,8 ,16 ,1 ,0xA0000 ,0xA000, 160 ,1152,160,1024, 0 },/* newer ET4000 */
00323 { 0x03E  ,M_LIN4   ,1280, 960,160,60 ,8 ,16 ,1 ,0xA0000 ,0xA000, 160 ,1024,160,960 , 0 },/* Definicon only */ 
00324 { 0x06A  ,M_LIN4   ,800 ,600 ,100,37 ,8 ,16 ,1 ,0xA0000 ,0xA000, 128 ,663 ,100,600 , 0 },/* newer ET4000 */
00325 
00326 // Sierra SC1148x Hi-Color DAC modes
00327 { 0x213  ,M_LIN15  ,320 ,200 ,40 ,25 ,8 ,8  ,1 ,0xA0000 ,0x10000,100 ,449 ,80 ,400 , _VGA_PIXEL_DOUBLE | _REPEAT1 },
00328 { 0x22D  ,M_LIN15  ,640 ,350 ,80 ,25 ,8 ,14 ,1 ,0xA0000 ,0x10000,200 ,449 ,160,350 , 0 },
00329 { 0x22E  ,M_LIN15  ,640 ,480 ,80 ,30 ,8 ,16 ,1 ,0xA0000 ,0x10000,200 ,525 ,160,480 , 0 },
00330 { 0x22F  ,M_LIN15  ,640 ,400 ,80 ,25 ,8 ,16 ,1 ,0xA0000 ,0x10000,200 ,449 ,160,400 , 0 },
00331 { 0x230  ,M_LIN15  ,800 ,600 ,100,37 ,8 ,16 ,1 ,0xA0000 ,0x10000,264 ,628 ,200,600 , 0 },
00332 
00333 {0xFFFF  ,M_ERROR  ,0   ,0   ,0  ,0  ,0 ,0  ,0 ,0x00000 ,0x0000 ,0   ,0   ,0  ,0   ,0   },
00334 };
00335 
00336 VideoModeBlock ModeList_VGA_Paradise[]={
00337 /* mode  ,type     ,sw  ,sh  ,tw ,th ,cw,ch ,pt,pstart  ,plength,htot,vtot,hde,vde special flags */
00338 { 0x000  ,M_TEXT   ,360 ,400 ,40 ,25 ,9 ,16 ,8 ,0xB8000 ,0x0800 ,50  ,449 ,40 ,400 ,_EGA_HALF_CLOCK     },
00339 { 0x001  ,M_TEXT   ,360 ,400 ,40 ,25 ,9 ,16 ,8 ,0xB8000 ,0x0800 ,50  ,449 ,40 ,400 ,_EGA_HALF_CLOCK     },
00340 { 0x002  ,M_TEXT   ,720 ,400 ,80 ,25 ,9 ,16 ,8 ,0xB8000 ,0x1000 ,100 ,449 ,80 ,400 ,0   },
00341 { 0x003  ,M_TEXT   ,720 ,400 ,80 ,25 ,9 ,16 ,8 ,0xB8000 ,0x1000 ,100 ,449 ,80 ,400 ,0   },
00342 { 0x004  ,M_CGA4   ,320 ,200 ,40 ,25 ,8 ,8  ,1 ,0xB8000 ,0x4000 ,50  ,449 ,40 ,400 ,_EGA_HALF_CLOCK     | _DOUBLESCAN | _REPEAT1},
00343 { 0x005  ,M_CGA4   ,320 ,200 ,40 ,25 ,8 ,8  ,1 ,0xB8000 ,0x4000 ,50  ,449 ,40 ,400 ,_EGA_HALF_CLOCK     | _DOUBLESCAN | _REPEAT1},
00344 { 0x006  ,M_CGA2   ,640 ,200 ,80 ,25 ,8 ,8  ,1 ,0xB8000 ,0x4000 ,100 ,449 ,80 ,400 ,_DOUBLESCAN | _REPEAT1},
00345 { 0x007  ,M_TEXT   ,720 ,400 ,80 ,25 ,9 ,16 ,8 ,0xB0000 ,0x1000 ,100 ,449 ,80 ,400 ,0   },
00346 
00347 { 0x00D  ,M_EGA    ,320 ,200 ,40 ,25 ,8 ,8  ,8 ,0xA0000 ,0x2000 ,50  ,449 ,40 ,400 ,_EGA_HALF_CLOCK     | _DOUBLESCAN   },
00348 { 0x00E  ,M_EGA    ,640 ,200 ,80 ,25 ,8 ,8  ,4 ,0xA0000 ,0x4000 ,100 ,449 ,80 ,400 ,_DOUBLESCAN },
00349 { 0x00F  ,M_EGA    ,640 ,350 ,80 ,25 ,8 ,14 ,2 ,0xA0000 ,0x8000 ,100 ,449 ,80 ,350 ,0   },
00350 { 0x010  ,M_EGA    ,640 ,350 ,80 ,25 ,8 ,14 ,2 ,0xA0000 ,0x8000 ,100 ,449 ,80 ,350 ,0   },
00351 { 0x011  ,M_EGA    ,640 ,480 ,80 ,30 ,8 ,16 ,1 ,0xA0000 ,0xA000 ,100 ,525 ,80 ,480 ,0   },
00352 { 0x012  ,M_EGA    ,640 ,480 ,80 ,30 ,8 ,16 ,1 ,0xA0000 ,0xA000 ,100 ,525 ,80 ,480 ,0   },
00353 { 0x013  ,M_VGA    ,320 ,200 ,40 ,25 ,8 ,8  ,1 ,0xA0000 ,0x2000 ,100 ,449 ,80 ,400 ,_REPEAT1 },
00354 
00355 { 0x054  ,M_TEXT   ,1056 ,688, 132,43, 8, 9, 1, 0xB0000, 0x4000, 192, 720, 132,688, 0 },
00356 { 0x055  ,M_TEXT   ,1056 ,400, 132,25, 8, 16,1, 0xB0000, 0x2000, 192, 449, 132,400, 0 },
00357 { 0x056  ,M_TEXT   ,1056 ,688, 132,43, 8, 9, 1, 0xB0000, 0x4000, 192, 720, 132,688, 0 },
00358 { 0x057  ,M_TEXT   ,1056 ,400, 132,25, 8, 16,1, 0xB0000, 0x2000, 192, 449, 132,400, 0 },
00359 { 0x058  ,M_LIN4   ,800 , 600, 100,37, 8, 16,1, 0xA0000, 0xA000, 128 ,663 ,100,600, 0 },
00360 { 0x05C  ,M_LIN8   ,800 , 600 ,100,37 ,8 ,16,1 ,0xA0000 ,0x10000,128 ,663 ,100,600, 0 },
00361 { 0x05D  ,M_LIN4   ,1024, 768, 128,48 ,8, 16,1, 0xA0000, 0x10000,128 ,800 ,128,768 ,0 }, // documented only on C00 upwards
00362 { 0x05E  ,M_LIN8   ,640 , 400, 80 ,25, 8, 16,1, 0xA0000, 0x10000,100 ,449 ,80 ,400, 0 },
00363 { 0x05F  ,M_LIN8   ,640 , 480, 80 ,30, 8, 16,1, 0xA0000, 0x10000,100 ,525 ,80 ,480, 0 },
00364 
00365 {0xFFFF  ,M_ERROR  ,0   ,0   ,0  ,0  ,0 ,0  ,0 ,0x00000 ,0x0000 ,0   ,0   ,0  ,0   ,0   },
00366 };
00367 
00368 /* NTS: I will *NOT* set the double scanline flag for 200 line modes.
00369  *      The modes listed here are intended to reflect the actual raster sent to the EGA monitor,
00370  *      not what you think looks better. EGA as far as I know, is either sent a 200-line mode,
00371  *      or a 350-line mode. There is no VGA-line 200 to 400 line doubling. */
00372 VideoModeBlock ModeList_EGA[]={
00373 /* mode  ,type     ,sw  ,sh  ,tw ,th ,cw,ch ,pt,pstart  ,plength,htot,vtot,hde,vde special flags */
00374 { 0x000  ,M_TEXT   ,320 ,350 ,40 ,25 ,8 ,14 ,8 ,0xB8000 ,0x0800 ,50  ,366 ,40 ,350 ,_EGA_HALF_CLOCK     },
00375 { 0x001  ,M_TEXT   ,320 ,350 ,40 ,25 ,8 ,14 ,8 ,0xB8000 ,0x0800 ,50  ,366 ,40 ,350 ,_EGA_HALF_CLOCK     },
00376 { 0x002  ,M_TEXT   ,640 ,350 ,80 ,25 ,8 ,14 ,8 ,0xB8000 ,0x1000 ,96  ,366 ,80 ,350 ,0   },
00377 { 0x003  ,M_TEXT   ,640 ,350 ,80 ,25 ,8 ,14 ,8 ,0xB8000 ,0x1000 ,96  ,366 ,80 ,350 ,0   },
00378 { 0x004  ,M_CGA4   ,320 ,200 ,40 ,25 ,8 ,8  ,1 ,0xB8000 ,0x4000 ,60  ,262 ,40 ,200 ,_EGA_HALF_CLOCK     | _REPEAT1},
00379 { 0x005  ,M_CGA4   ,320 ,200 ,40 ,25 ,8 ,8  ,1 ,0xB8000 ,0x4000 ,60  ,262 ,40 ,200 ,_EGA_HALF_CLOCK     | _REPEAT1},
00380 { 0x006  ,M_CGA2   ,640 ,200 ,80 ,25 ,8 ,8  ,1 ,0xB8000 ,0x4000 ,117 ,262 ,80 ,200 ,_REPEAT1},
00381 { 0x007  ,M_TEXT   ,720 ,350 ,80 ,25 ,9 ,14 ,8 ,0xB0000 ,0x1000 ,101 ,370 ,80 ,350 ,0   },
00382 
00383 { 0x00D  ,M_EGA    ,320 ,200 ,40 ,25 ,8 ,8  ,8 ,0xA0000 ,0x2000 ,60  ,262 ,40 ,200 ,_EGA_HALF_CLOCK     },
00384 { 0x00E  ,M_EGA    ,640 ,200 ,80 ,25 ,8 ,8  ,4 ,0xA0000 ,0x4000 ,117 ,262 ,80 ,200 ,0 },
00385 { 0x00F  ,M_EGA    ,640 ,350 ,80 ,25 ,8 ,14 ,2 ,0xA0000 ,0x8000 ,101 ,370 ,80 ,350 ,0   },
00386 { 0x010  ,M_EGA    ,640 ,350 ,80 ,25 ,8 ,14 ,2 ,0xA0000 ,0x8000 ,96  ,366 ,80 ,350 ,0   },
00387 
00388 {0xFFFF  ,M_ERROR  ,0   ,0   ,0  ,0  ,0 ,0  ,0 ,0x00000 ,0x0000 ,0   ,0   ,0  ,0   ,0   },
00389 };
00390 
00391 VideoModeBlock ModeList_OTHER[]={
00392 /* mode  ,type     ,sw  ,sh  ,tw ,th ,cw,ch ,pt,pstart  ,plength,htot,vtot,hde,vde ,special flags */
00393 { 0x000  ,M_TEXT   ,320 ,400 ,40 ,25 ,8 ,8  ,8 ,0xB8000 ,0x0800 ,56  ,31  ,40 ,25  ,0   },
00394 { 0x001  ,M_TEXT   ,320 ,400 ,40 ,25 ,8 ,8  ,8 ,0xB8000 ,0x0800 ,56  ,31  ,40 ,25  ,0   },
00395 { 0x002  ,M_TEXT   ,640 ,400 ,80 ,25 ,8 ,8  ,4 ,0xB8000 ,0x1000 ,113 ,31  ,80 ,25  ,0   },
00396 { 0x003  ,M_TEXT   ,640 ,400 ,80 ,25 ,8 ,8  ,4 ,0xB8000 ,0x1000 ,113 ,31  ,80 ,25  ,0   },
00397 { 0x004  ,M_CGA4   ,320 ,200 ,40 ,25 ,8 ,8  ,4 ,0xB8000 ,0x0800 ,56  ,127 ,40 ,100 ,0   },
00398 { 0x005  ,M_CGA4   ,320 ,200 ,40 ,25 ,8 ,8  ,4 ,0xB8000 ,0x0800 ,56  ,127 ,40 ,100 ,0   },
00399 { 0x006  ,M_CGA2   ,640 ,200 ,80 ,25 ,8 ,8  ,4 ,0xB8000 ,0x0800 ,56  ,127 ,40 ,100 ,0   },
00400 { 0x008  ,M_TANDY16,160 ,200 ,20 ,25 ,8 ,8  ,8 ,0xB8000 ,0x2000 ,56  ,127 ,40 ,100 ,0   },
00401 { 0x009  ,M_TANDY16,320 ,200 ,40 ,25 ,8 ,8  ,8 ,0xB8000 ,0x2000 ,113 ,63  ,80 ,50  ,0   },
00402 { 0x00A  ,M_CGA4   ,640 ,200 ,80 ,25 ,8 ,8  ,8 ,0xB8000 ,0x2000 ,113 ,63  ,80 ,50  ,0   },
00403 //{ 0x00E  ,M_TANDY16,640 ,200 ,80 ,25 ,8 ,8  ,8 ,0xA0000 ,0x10000 ,113 ,256 ,80 ,200 ,0   },
00404 {0xFFFF  ,M_ERROR  ,0   ,0   ,0  ,0  ,0 ,0  ,0 ,0x00000 ,0x0000 ,0   ,0   ,0  ,0   ,0   },
00405 };
00406 
00407 VideoModeBlock Hercules_Mode=
00408 { 0x007  ,M_TEXT   ,640 ,400 ,80 ,25 ,8 ,14 ,1 ,0xB0000 ,0x1000 ,97 ,25  ,80 ,25  ,0    };
00409 
00410 VideoModeBlock PC98_Mode=
00411 { 0x000  ,M_PC98   ,640 ,400 ,80 ,25 ,8 ,14 ,1 ,0xA0000 ,0x1000 ,97 ,25  ,80 ,25  ,0    };
00412 
00413 static Bit8u text_palette[64][3]=
00414 {
00415   {0x00,0x00,0x00},{0x00,0x00,0x2a},{0x00,0x2a,0x00},{0x00,0x2a,0x2a},{0x2a,0x00,0x00},{0x2a,0x00,0x2a},{0x2a,0x2a,0x00},{0x2a,0x2a,0x2a},
00416   {0x00,0x00,0x15},{0x00,0x00,0x3f},{0x00,0x2a,0x15},{0x00,0x2a,0x3f},{0x2a,0x00,0x15},{0x2a,0x00,0x3f},{0x2a,0x2a,0x15},{0x2a,0x2a,0x3f},
00417   {0x00,0x15,0x00},{0x00,0x15,0x2a},{0x00,0x3f,0x00},{0x00,0x3f,0x2a},{0x2a,0x15,0x00},{0x2a,0x15,0x2a},{0x2a,0x3f,0x00},{0x2a,0x3f,0x2a},
00418   {0x00,0x15,0x15},{0x00,0x15,0x3f},{0x00,0x3f,0x15},{0x00,0x3f,0x3f},{0x2a,0x15,0x15},{0x2a,0x15,0x3f},{0x2a,0x3f,0x15},{0x2a,0x3f,0x3f},
00419   {0x15,0x00,0x00},{0x15,0x00,0x2a},{0x15,0x2a,0x00},{0x15,0x2a,0x2a},{0x3f,0x00,0x00},{0x3f,0x00,0x2a},{0x3f,0x2a,0x00},{0x3f,0x2a,0x2a},
00420   {0x15,0x00,0x15},{0x15,0x00,0x3f},{0x15,0x2a,0x15},{0x15,0x2a,0x3f},{0x3f,0x00,0x15},{0x3f,0x00,0x3f},{0x3f,0x2a,0x15},{0x3f,0x2a,0x3f},
00421   {0x15,0x15,0x00},{0x15,0x15,0x2a},{0x15,0x3f,0x00},{0x15,0x3f,0x2a},{0x3f,0x15,0x00},{0x3f,0x15,0x2a},{0x3f,0x3f,0x00},{0x3f,0x3f,0x2a},
00422   {0x15,0x15,0x15},{0x15,0x15,0x3f},{0x15,0x3f,0x15},{0x15,0x3f,0x3f},{0x3f,0x15,0x15},{0x3f,0x15,0x3f},{0x3f,0x3f,0x15},{0x3f,0x3f,0x3f}
00423 };
00424 
00425 static Bit8u mtext_palette[64][3]=
00426 {
00427   {0x00,0x00,0x00},{0x00,0x00,0x00},{0x00,0x00,0x00},{0x00,0x00,0x00},{0x00,0x00,0x00},{0x00,0x00,0x00},{0x00,0x00,0x00},{0x00,0x00,0x00},
00428   {0x2a,0x2a,0x2a},{0x2a,0x2a,0x2a},{0x2a,0x2a,0x2a},{0x2a,0x2a,0x2a},{0x2a,0x2a,0x2a},{0x2a,0x2a,0x2a},{0x2a,0x2a,0x2a},{0x2a,0x2a,0x2a},
00429   {0x00,0x00,0x00},{0x00,0x00,0x00},{0x00,0x00,0x00},{0x00,0x00,0x00},{0x00,0x00,0x00},{0x00,0x00,0x00},{0x00,0x00,0x00},{0x00,0x00,0x00},
00430   {0x3f,0x3f,0x3f},{0x3f,0x3f,0x3f},{0x3f,0x3f,0x3f},{0x3f,0x3f,0x3f},{0x3f,0x3f,0x3f},{0x3f,0x3f,0x3f},{0x3f,0x3f,0x3f},{0x3f,0x3f,0x3f},
00431   {0x00,0x00,0x00},{0x00,0x00,0x00},{0x00,0x00,0x00},{0x00,0x00,0x00},{0x00,0x00,0x00},{0x00,0x00,0x00},{0x00,0x00,0x00},{0x00,0x00,0x00},
00432   {0x2a,0x2a,0x2a},{0x2a,0x2a,0x2a},{0x2a,0x2a,0x2a},{0x2a,0x2a,0x2a},{0x2a,0x2a,0x2a},{0x2a,0x2a,0x2a},{0x2a,0x2a,0x2a},{0x2a,0x2a,0x2a},
00433   {0x00,0x00,0x00},{0x00,0x00,0x00},{0x00,0x00,0x00},{0x00,0x00,0x00},{0x00,0x00,0x00},{0x00,0x00,0x00},{0x00,0x00,0x00},{0x00,0x00,0x00},
00434   {0x3f,0x3f,0x3f},{0x3f,0x3f,0x3f},{0x3f,0x3f,0x3f},{0x3f,0x3f,0x3f},{0x3f,0x3f,0x3f},{0x3f,0x3f,0x3f},{0x3f,0x3f,0x3f},{0x3f,0x3f,0x3f} 
00435 };
00436 
00437 static Bit8u mtext_s3_palette[64][3]=
00438 {
00439   {0x00,0x00,0x00},{0x00,0x00,0x00},{0x00,0x00,0x00},{0x00,0x00,0x00},{0x00,0x00,0x00},{0x00,0x00,0x00},{0x00,0x00,0x00},{0x00,0x00,0x00},
00440   {0x2a,0x2a,0x2a},{0x2a,0x2a,0x2a},{0x2a,0x2a,0x2a},{0x2a,0x2a,0x2a},{0x2a,0x2a,0x2a},{0x2a,0x2a,0x2a},{0x2a,0x2a,0x2a},{0x2a,0x2a,0x2a},
00441   {0x2a,0x2a,0x2a},{0x2a,0x2a,0x2a},{0x2a,0x2a,0x2a},{0x2a,0x2a,0x2a},{0x2a,0x2a,0x2a},{0x2a,0x2a,0x2a},{0x2a,0x2a,0x2a},{0x2a,0x2a,0x2a},
00442   {0x3f,0x3f,0x3f},{0x3f,0x3f,0x3f},{0x3f,0x3f,0x3f},{0x3f,0x3f,0x3f},{0x3f,0x3f,0x3f},{0x3f,0x3f,0x3f},{0x3f,0x3f,0x3f},{0x3f,0x3f,0x3f},
00443   {0x00,0x00,0x00},{0x00,0x00,0x00},{0x00,0x00,0x00},{0x00,0x00,0x00},{0x00,0x00,0x00},{0x00,0x00,0x00},{0x00,0x00,0x00},{0x00,0x00,0x00},
00444   {0x2a,0x2a,0x2a},{0x2a,0x2a,0x2a},{0x2a,0x2a,0x2a},{0x2a,0x2a,0x2a},{0x2a,0x2a,0x2a},{0x2a,0x2a,0x2a},{0x2a,0x2a,0x2a},{0x2a,0x2a,0x2a},
00445   {0x2a,0x2a,0x2a},{0x2a,0x2a,0x2a},{0x2a,0x2a,0x2a},{0x2a,0x2a,0x2a},{0x2a,0x2a,0x2a},{0x2a,0x2a,0x2a},{0x2a,0x2a,0x2a},{0x2a,0x2a,0x2a},
00446   {0x3f,0x3f,0x3f},{0x3f,0x3f,0x3f},{0x3f,0x3f,0x3f},{0x3f,0x3f,0x3f},{0x3f,0x3f,0x3f},{0x3f,0x3f,0x3f},{0x3f,0x3f,0x3f},{0x3f,0x3f,0x3f} 
00447 };
00448 
00449 static Bit8u ega_palette[64][3]=
00450 {
00451   {0x00,0x00,0x00}, {0x00,0x00,0x2a}, {0x00,0x2a,0x00}, {0x00,0x2a,0x2a}, {0x2a,0x00,0x00}, {0x2a,0x00,0x2a}, {0x2a,0x15,0x00}, {0x2a,0x2a,0x2a},
00452   {0x00,0x00,0x00}, {0x00,0x00,0x2a}, {0x00,0x2a,0x00}, {0x00,0x2a,0x2a}, {0x2a,0x00,0x00}, {0x2a,0x00,0x2a}, {0x2a,0x15,0x00}, {0x2a,0x2a,0x2a},
00453   {0x15,0x15,0x15}, {0x15,0x15,0x3f}, {0x15,0x3f,0x15}, {0x15,0x3f,0x3f}, {0x3f,0x15,0x15}, {0x3f,0x15,0x3f}, {0x3f,0x3f,0x15}, {0x3f,0x3f,0x3f},
00454   {0x15,0x15,0x15}, {0x15,0x15,0x3f}, {0x15,0x3f,0x15}, {0x15,0x3f,0x3f}, {0x3f,0x15,0x15}, {0x3f,0x15,0x3f}, {0x3f,0x3f,0x15}, {0x3f,0x3f,0x3f},
00455   {0x00,0x00,0x00}, {0x00,0x00,0x2a}, {0x00,0x2a,0x00}, {0x00,0x2a,0x2a}, {0x2a,0x00,0x00}, {0x2a,0x00,0x2a}, {0x2a,0x15,0x00}, {0x2a,0x2a,0x2a},
00456   {0x00,0x00,0x00}, {0x00,0x00,0x2a}, {0x00,0x2a,0x00}, {0x00,0x2a,0x2a}, {0x2a,0x00,0x00}, {0x2a,0x00,0x2a}, {0x2a,0x15,0x00}, {0x2a,0x2a,0x2a},
00457   {0x15,0x15,0x15}, {0x15,0x15,0x3f}, {0x15,0x3f,0x15}, {0x15,0x3f,0x3f}, {0x3f,0x15,0x15}, {0x3f,0x15,0x3f}, {0x3f,0x3f,0x15}, {0x3f,0x3f,0x3f},
00458   {0x15,0x15,0x15}, {0x15,0x15,0x3f}, {0x15,0x3f,0x15}, {0x15,0x3f,0x3f}, {0x3f,0x15,0x15}, {0x3f,0x15,0x3f}, {0x3f,0x3f,0x15}, {0x3f,0x3f,0x3f}
00459 };
00460 
00461 static Bit8u cga_palette[16][3]=
00462 {
00463         {0x00,0x00,0x00}, {0x00,0x00,0x2a}, {0x00,0x2a,0x00}, {0x00,0x2a,0x2a}, {0x2a,0x00,0x00}, {0x2a,0x00,0x2a}, {0x2a,0x15,0x00}, {0x2a,0x2a,0x2a},
00464         {0x15,0x15,0x15}, {0x15,0x15,0x3f}, {0x15,0x3f,0x15}, {0x15,0x3f,0x3f}, {0x3f,0x15,0x15}, {0x3f,0x15,0x3f}, {0x3f,0x3f,0x15}, {0x3f,0x3f,0x3f},
00465 };
00466 
00467 static Bit8u cga_palette_2[64][3]=
00468 {
00469         {0x00,0x00,0x00}, {0x00,0x00,0x2a}, {0x00,0x2a,0x00}, {0x00,0x2a,0x2a}, {0x2a,0x00,0x00}, {0x2a,0x00,0x2a}, {0x2a,0x15,0x00}, {0x2a,0x2a,0x2a},
00470         {0x00,0x00,0x00}, {0x00,0x00,0x2a}, {0x00,0x2a,0x00}, {0x00,0x2a,0x2a}, {0x2a,0x00,0x00}, {0x2a,0x00,0x2a}, {0x2a,0x15,0x00}, {0x2a,0x2a,0x2a},
00471         {0x15,0x15,0x15}, {0x15,0x15,0x3f}, {0x15,0x3f,0x15}, {0x15,0x3f,0x3f}, {0x3f,0x15,0x15}, {0x3f,0x15,0x3f}, {0x3f,0x3f,0x15}, {0x3f,0x3f,0x3f},
00472         {0x15,0x15,0x15}, {0x15,0x15,0x3f}, {0x15,0x3f,0x15}, {0x15,0x3f,0x3f}, {0x3f,0x15,0x15}, {0x3f,0x15,0x3f}, {0x3f,0x3f,0x15}, {0x3f,0x3f,0x3f},
00473         {0x00,0x00,0x00}, {0x00,0x00,0x2a}, {0x00,0x2a,0x00}, {0x00,0x2a,0x2a}, {0x2a,0x00,0x00}, {0x2a,0x00,0x2a}, {0x2a,0x15,0x00}, {0x2a,0x2a,0x2a},
00474         {0x00,0x00,0x00}, {0x00,0x00,0x2a}, {0x00,0x2a,0x00}, {0x00,0x2a,0x2a}, {0x2a,0x00,0x00}, {0x2a,0x00,0x2a}, {0x2a,0x15,0x00}, {0x2a,0x2a,0x2a},
00475         {0x15,0x15,0x15}, {0x15,0x15,0x3f}, {0x15,0x3f,0x15}, {0x15,0x3f,0x3f}, {0x3f,0x15,0x15}, {0x3f,0x15,0x3f}, {0x3f,0x3f,0x15}, {0x3f,0x3f,0x3f},
00476         {0x15,0x15,0x15}, {0x15,0x15,0x3f}, {0x15,0x3f,0x15}, {0x15,0x3f,0x3f}, {0x3f,0x15,0x15}, {0x3f,0x15,0x3f}, {0x3f,0x3f,0x15}, {0x3f,0x3f,0x3f},
00477 };
00478 
00479 static Bit8u vga_palette[248][3]=
00480 {
00481   {0x00,0x00,0x00},{0x00,0x00,0x2a},{0x00,0x2a,0x00},{0x00,0x2a,0x2a},{0x2a,0x00,0x00},{0x2a,0x00,0x2a},{0x2a,0x15,0x00},{0x2a,0x2a,0x2a},
00482   {0x15,0x15,0x15},{0x15,0x15,0x3f},{0x15,0x3f,0x15},{0x15,0x3f,0x3f},{0x3f,0x15,0x15},{0x3f,0x15,0x3f},{0x3f,0x3f,0x15},{0x3f,0x3f,0x3f},
00483   {0x00,0x00,0x00},{0x05,0x05,0x05},{0x08,0x08,0x08},{0x0b,0x0b,0x0b},{0x0e,0x0e,0x0e},{0x11,0x11,0x11},{0x14,0x14,0x14},{0x18,0x18,0x18},
00484   {0x1c,0x1c,0x1c},{0x20,0x20,0x20},{0x24,0x24,0x24},{0x28,0x28,0x28},{0x2d,0x2d,0x2d},{0x32,0x32,0x32},{0x38,0x38,0x38},{0x3f,0x3f,0x3f},
00485   {0x00,0x00,0x3f},{0x10,0x00,0x3f},{0x1f,0x00,0x3f},{0x2f,0x00,0x3f},{0x3f,0x00,0x3f},{0x3f,0x00,0x2f},{0x3f,0x00,0x1f},{0x3f,0x00,0x10},
00486   {0x3f,0x00,0x00},{0x3f,0x10,0x00},{0x3f,0x1f,0x00},{0x3f,0x2f,0x00},{0x3f,0x3f,0x00},{0x2f,0x3f,0x00},{0x1f,0x3f,0x00},{0x10,0x3f,0x00},
00487   {0x00,0x3f,0x00},{0x00,0x3f,0x10},{0x00,0x3f,0x1f},{0x00,0x3f,0x2f},{0x00,0x3f,0x3f},{0x00,0x2f,0x3f},{0x00,0x1f,0x3f},{0x00,0x10,0x3f},
00488   {0x1f,0x1f,0x3f},{0x27,0x1f,0x3f},{0x2f,0x1f,0x3f},{0x37,0x1f,0x3f},{0x3f,0x1f,0x3f},{0x3f,0x1f,0x37},{0x3f,0x1f,0x2f},{0x3f,0x1f,0x27},
00489 
00490   {0x3f,0x1f,0x1f},{0x3f,0x27,0x1f},{0x3f,0x2f,0x1f},{0x3f,0x37,0x1f},{0x3f,0x3f,0x1f},{0x37,0x3f,0x1f},{0x2f,0x3f,0x1f},{0x27,0x3f,0x1f},
00491   {0x1f,0x3f,0x1f},{0x1f,0x3f,0x27},{0x1f,0x3f,0x2f},{0x1f,0x3f,0x37},{0x1f,0x3f,0x3f},{0x1f,0x37,0x3f},{0x1f,0x2f,0x3f},{0x1f,0x27,0x3f},
00492   {0x2d,0x2d,0x3f},{0x31,0x2d,0x3f},{0x36,0x2d,0x3f},{0x3a,0x2d,0x3f},{0x3f,0x2d,0x3f},{0x3f,0x2d,0x3a},{0x3f,0x2d,0x36},{0x3f,0x2d,0x31},
00493   {0x3f,0x2d,0x2d},{0x3f,0x31,0x2d},{0x3f,0x36,0x2d},{0x3f,0x3a,0x2d},{0x3f,0x3f,0x2d},{0x3a,0x3f,0x2d},{0x36,0x3f,0x2d},{0x31,0x3f,0x2d},
00494   {0x2d,0x3f,0x2d},{0x2d,0x3f,0x31},{0x2d,0x3f,0x36},{0x2d,0x3f,0x3a},{0x2d,0x3f,0x3f},{0x2d,0x3a,0x3f},{0x2d,0x36,0x3f},{0x2d,0x31,0x3f},
00495   {0x00,0x00,0x1c},{0x07,0x00,0x1c},{0x0e,0x00,0x1c},{0x15,0x00,0x1c},{0x1c,0x00,0x1c},{0x1c,0x00,0x15},{0x1c,0x00,0x0e},{0x1c,0x00,0x07},
00496   {0x1c,0x00,0x00},{0x1c,0x07,0x00},{0x1c,0x0e,0x00},{0x1c,0x15,0x00},{0x1c,0x1c,0x00},{0x15,0x1c,0x00},{0x0e,0x1c,0x00},{0x07,0x1c,0x00},
00497   {0x00,0x1c,0x00},{0x00,0x1c,0x07},{0x00,0x1c,0x0e},{0x00,0x1c,0x15},{0x00,0x1c,0x1c},{0x00,0x15,0x1c},{0x00,0x0e,0x1c},{0x00,0x07,0x1c},
00498 
00499   {0x0e,0x0e,0x1c},{0x11,0x0e,0x1c},{0x15,0x0e,0x1c},{0x18,0x0e,0x1c},{0x1c,0x0e,0x1c},{0x1c,0x0e,0x18},{0x1c,0x0e,0x15},{0x1c,0x0e,0x11},
00500   {0x1c,0x0e,0x0e},{0x1c,0x11,0x0e},{0x1c,0x15,0x0e},{0x1c,0x18,0x0e},{0x1c,0x1c,0x0e},{0x18,0x1c,0x0e},{0x15,0x1c,0x0e},{0x11,0x1c,0x0e},
00501   {0x0e,0x1c,0x0e},{0x0e,0x1c,0x11},{0x0e,0x1c,0x15},{0x0e,0x1c,0x18},{0x0e,0x1c,0x1c},{0x0e,0x18,0x1c},{0x0e,0x15,0x1c},{0x0e,0x11,0x1c},
00502   {0x14,0x14,0x1c},{0x16,0x14,0x1c},{0x18,0x14,0x1c},{0x1a,0x14,0x1c},{0x1c,0x14,0x1c},{0x1c,0x14,0x1a},{0x1c,0x14,0x18},{0x1c,0x14,0x16},
00503   {0x1c,0x14,0x14},{0x1c,0x16,0x14},{0x1c,0x18,0x14},{0x1c,0x1a,0x14},{0x1c,0x1c,0x14},{0x1a,0x1c,0x14},{0x18,0x1c,0x14},{0x16,0x1c,0x14},
00504   {0x14,0x1c,0x14},{0x14,0x1c,0x16},{0x14,0x1c,0x18},{0x14,0x1c,0x1a},{0x14,0x1c,0x1c},{0x14,0x1a,0x1c},{0x14,0x18,0x1c},{0x14,0x16,0x1c},
00505   {0x00,0x00,0x10},{0x04,0x00,0x10},{0x08,0x00,0x10},{0x0c,0x00,0x10},{0x10,0x00,0x10},{0x10,0x00,0x0c},{0x10,0x00,0x08},{0x10,0x00,0x04},
00506   {0x10,0x00,0x00},{0x10,0x04,0x00},{0x10,0x08,0x00},{0x10,0x0c,0x00},{0x10,0x10,0x00},{0x0c,0x10,0x00},{0x08,0x10,0x00},{0x04,0x10,0x00},
00507 
00508   {0x00,0x10,0x00},{0x00,0x10,0x04},{0x00,0x10,0x08},{0x00,0x10,0x0c},{0x00,0x10,0x10},{0x00,0x0c,0x10},{0x00,0x08,0x10},{0x00,0x04,0x10},
00509   {0x08,0x08,0x10},{0x0a,0x08,0x10},{0x0c,0x08,0x10},{0x0e,0x08,0x10},{0x10,0x08,0x10},{0x10,0x08,0x0e},{0x10,0x08,0x0c},{0x10,0x08,0x0a},
00510   {0x10,0x08,0x08},{0x10,0x0a,0x08},{0x10,0x0c,0x08},{0x10,0x0e,0x08},{0x10,0x10,0x08},{0x0e,0x10,0x08},{0x0c,0x10,0x08},{0x0a,0x10,0x08},
00511   {0x08,0x10,0x08},{0x08,0x10,0x0a},{0x08,0x10,0x0c},{0x08,0x10,0x0e},{0x08,0x10,0x10},{0x08,0x0e,0x10},{0x08,0x0c,0x10},{0x08,0x0a,0x10},
00512   {0x0b,0x0b,0x10},{0x0c,0x0b,0x10},{0x0d,0x0b,0x10},{0x0f,0x0b,0x10},{0x10,0x0b,0x10},{0x10,0x0b,0x0f},{0x10,0x0b,0x0d},{0x10,0x0b,0x0c},
00513   {0x10,0x0b,0x0b},{0x10,0x0c,0x0b},{0x10,0x0d,0x0b},{0x10,0x0f,0x0b},{0x10,0x10,0x0b},{0x0f,0x10,0x0b},{0x0d,0x10,0x0b},{0x0c,0x10,0x0b},
00514   {0x0b,0x10,0x0b},{0x0b,0x10,0x0c},{0x0b,0x10,0x0d},{0x0b,0x10,0x0f},{0x0b,0x10,0x10},{0x0b,0x0f,0x10},{0x0b,0x0d,0x10},{0x0b,0x0c,0x10}
00515 };
00516 VideoModeBlock * CurMode = NULL;
00517 
00518 static bool SetCurMode(VideoModeBlock modeblock[],Bit16u mode) {
00519         Bitu i=0;
00520         while (modeblock[i].mode!=0xffff) {
00521                 if (modeblock[i].mode!=mode)
00522                         i++;
00523                 /* Hack for VBE 1.2 modes and 24/32bpp ambiguity UNLESS the user changed the mode */
00524                 else if (modeblock[i].mode >= 0x100 && modeblock[i].mode <= 0x11F &&
00525             !(modeblock[i].special & _USER_MODIFIED) &&
00526                         ((modeblock[i].type == M_LIN32 && !vesa12_modes_32bpp) ||
00527                         (modeblock[i].type == M_LIN24 && vesa12_modes_32bpp))) {
00528                         /* ignore */
00529                         i++;
00530                 }
00531         /* ignore deleted modes */
00532         else if (modeblock[i].type == M_ERROR) {
00533             /* ignore */
00534             i++;
00535         }
00536             /* ignore disabled modes */
00537         else if (modeblock[i].special & _USER_DISABLED) {
00538             /* ignore */
00539             i++;
00540         }
00541                 else {
00542                         if ((!int10.vesa_oldvbe) || (ModeList_VGA[i].mode<0x120)) {
00543                                 CurMode=&modeblock[i];
00544                                 return true;
00545                         }
00546                         return false;
00547                 }
00548         }
00549         return false;
00550 }
00551 
00552 bool INT10_SetCurMode(void) {
00553         bool mode_changed=false;
00554         Bit16u bios_mode=(Bit16u)real_readb(BIOSMEM_SEG,BIOSMEM_CURRENT_MODE);
00555         if (CurMode == NULL || CurMode->mode != bios_mode) {
00556                 switch (machine) {
00557                 case MCH_CGA:
00558                         if (bios_mode<7) mode_changed=SetCurMode(ModeList_OTHER,bios_mode);
00559                         break;
00560                 case TANDY_ARCH_CASE:
00561                         if (bios_mode!=7 && bios_mode<=0xa) mode_changed=SetCurMode(ModeList_OTHER,bios_mode);
00562                         break;
00563                 case MCH_HERC:
00564                         break;
00565                 case MCH_EGA:
00566                         mode_changed=SetCurMode(ModeList_EGA,bios_mode);
00567                         break;
00568                 case VGA_ARCH_CASE:
00569                         switch (svgaCard) {
00570                         case SVGA_TsengET4K:
00571                         case SVGA_TsengET3K:
00572                                 mode_changed=SetCurMode(ModeList_VGA_Tseng,bios_mode);
00573                                 break;
00574                         case SVGA_ParadisePVGA1A:
00575                                 mode_changed=SetCurMode(ModeList_VGA_Paradise,bios_mode);
00576                                 break;
00577                         case SVGA_S3Trio:
00578                                 if (bios_mode>=0x68 && CurMode->mode==(bios_mode+0x98)) break;
00579                         default:
00580                                 mode_changed=SetCurMode(ModeList_VGA,bios_mode);
00581                                 break;
00582                         }
00583                         if (mode_changed && bios_mode<=3) {
00584                                 switch (real_readb(BIOSMEM_SEG,BIOSMEM_MODESET_CTL)&0x90) {
00585                                 case 0x00:
00586                                         CurMode=&ModeList_VGA_Text_350lines[bios_mode];
00587                                         break;
00588                                 case 0x80:
00589                                         CurMode=&ModeList_VGA_Text_200lines[bios_mode];
00590                                         break;
00591                                 }
00592                         }
00593                         break;
00594                 default:
00595                         break;
00596                 }
00597         }
00598         return mode_changed;
00599 }
00600 
00601 static void FinishSetMode(bool clearmem) {
00602         /* Clear video memory if needs be */
00603         if (clearmem) {
00604                 switch (CurMode->type) {
00605                 case M_CGA4:
00606                 case M_CGA2:
00607                 case M_TANDY16:
00608                         for (Bit16u ct=0;ct<16*1024;ct++) {
00609                                 real_writew( 0xb800,ct*2,0x0000);
00610                         }
00611                         break;
00612                 case M_TEXT: {
00613                         Bit16u max = (CurMode->ptotal*CurMode->plength)>>1;
00614                         if (CurMode->mode == 7) {
00615                                 for (Bit16u ct=0;ct<max;ct++) real_writew(0xB000,ct*2,0x0720);
00616                         }
00617                         else {
00618                                 for (Bit16u ct=0;ct<max;ct++) real_writew(0xB800,ct*2,0x0720);
00619                         }
00620                         break;
00621                 }
00622                 case M_EGA:     
00623                 case M_VGA:
00624                 case M_LIN8:
00625                 case M_LIN4:
00626                 case M_LIN15:
00627                 case M_LIN16:
00628                 case M_LIN24:
00629                 case M_LIN32:
00630                         /* Hack we just access the memory directly */
00631                         memset(vga.mem.linear,0,vga.mem.memsize);
00632                         break;
00633                 default:
00634                         break;
00635                 }
00636         }
00637         /* Setup the BIOS */
00638         if (CurMode->mode<128) real_writeb(BIOSMEM_SEG,BIOSMEM_CURRENT_MODE,(Bit8u)CurMode->mode);
00639         else real_writeb(BIOSMEM_SEG,BIOSMEM_CURRENT_MODE,(Bit8u)(CurMode->mode-0x98)); //Looks like the s3 bios
00640         real_writew(BIOSMEM_SEG,BIOSMEM_NB_COLS,(Bit16u)CurMode->twidth);
00641         real_writew(BIOSMEM_SEG,BIOSMEM_PAGE_SIZE,(Bit16u)CurMode->plength);
00642         real_writew(BIOSMEM_SEG,BIOSMEM_CRTC_ADDRESS,((CurMode->mode==7 )|| (CurMode->mode==0x0f)) ? 0x3b4 : 0x3d4);
00643         real_writeb(BIOSMEM_SEG,BIOSMEM_NB_ROWS,(Bit8u)(CurMode->theight-1));
00644         real_writew(BIOSMEM_SEG,BIOSMEM_CHAR_HEIGHT,(Bit16u)CurMode->cheight);
00645         real_writeb(BIOSMEM_SEG,BIOSMEM_VIDEO_CTL,(0x60|(clearmem?0:0x80)));
00646         real_writeb(BIOSMEM_SEG,BIOSMEM_SWITCHES,0x09);
00647 
00648         // this is an index into the dcc table:
00649         if (IS_VGA_ARCH) real_writeb(BIOSMEM_SEG,BIOSMEM_DCC_INDEX,0x0b);
00650         real_writed(BIOSMEM_SEG,BIOSMEM_VS_POINTER,int10.rom.video_save_pointers);
00651 
00652         // Set cursor shape
00653         if (CurMode->type==M_TEXT) {
00654                 INT10_SetCursorShape(CURSOR_SCAN_LINE_NORMAL, CURSOR_SCAN_LINE_END);
00655         }
00656         // Set cursor pos for page 0..7
00657         for (Bit8u ct=0;ct<8;ct++) INT10_SetCursorPos(0,0,ct);
00658         // Set active page 0
00659         INT10_SetActivePage(0);
00660         /* Set some interrupt vectors */
00661         if (CurMode->mode<=3 || CurMode->mode==7) {
00662                 RealSetVec(0x43,int10.rom.font_8_first);
00663         } else {
00664                 switch (CurMode->cheight) {
00665                 case 8:RealSetVec(0x43,int10.rom.font_8_first);break;
00666                 case 14:RealSetVec(0x43,int10.rom.font_14);break;
00667                 case 16:RealSetVec(0x43,int10.rom.font_16);break;
00668                 }
00669         }
00670         /* FIXME */
00671         VGA_DAC_UpdateColorPalette();
00672         /* Tell mouse resolution change */
00673         Mouse_NewVideoMode();
00674 }
00675 
00676 extern bool en_int33;
00677 
00678 bool INT10_SetVideoMode_OTHER(Bit16u mode,bool clearmem) {
00679         switch (machine) {
00680         case MCH_CGA:
00681         case MCH_AMSTRAD:
00682                 if (mode>6) return false;
00683         case TANDY_ARCH_CASE:
00684                 if (mode>0xa) return false;
00685                 if (mode==7) mode=0; // PCJR defaults to 0 on illegal mode 7
00686                 if (!SetCurMode(ModeList_OTHER,mode)) {
00687                         LOG(LOG_INT10,LOG_ERROR)("Trying to set illegal mode %X",mode);
00688                         return false;
00689                 }
00690                 break;
00691         case MCH_HERC:
00692                 // Only init the adapter if the equipment word is set to monochrome (Testdrive)
00693                 if ((real_readw(BIOSMEM_SEG,BIOSMEM_INITIAL_MODE)&0x30)!=0x30) return false;
00694                 CurMode=&Hercules_Mode;
00695                 mode=7; // in case the video parameter table is modified
00696                 break;
00697         default:
00698                 break;
00699         }
00700         LOG(LOG_INT10,LOG_NORMAL)("Set Video Mode %X",mode);
00701 
00702         /* Setup the CRTC */
00703         Bitu crtc_base=machine==MCH_HERC ? 0x3b4 : 0x3d4;
00704         //Horizontal total
00705         IO_WriteW(crtc_base,0x00 | (CurMode->htotal) << 8);
00706         //Horizontal displayed
00707         IO_WriteW(crtc_base,0x01 | (CurMode->hdispend) << 8);
00708         //Horizontal sync position
00709         IO_WriteW(crtc_base,0x02 | (CurMode->hdispend+1) << 8);
00710         //Horizontal sync width, seems to be fixed to 0xa, for cga at least, hercules has 0xf
00711         // PCjr doubles sync width in high resolution modes, good for aspect correction
00712         // newer "compatible" CGA BIOS does the same
00713         // The IBM CGA card seems to limit retrace pulse widths
00714         Bitu syncwidth;
00715         if(machine==MCH_HERC) syncwidth = 0xf;
00716         else if(CurMode->hdispend==80) syncwidth = 0xc;
00717         else syncwidth = 0x6;
00718         
00719         IO_WriteW(crtc_base,0x03 | (syncwidth) << 8);
00721         IO_WriteW(crtc_base,0x04 | (CurMode->vtotal) << 8);
00722         //Vertical total adjust, 6 for cga,hercules,tandy
00723         IO_WriteW(crtc_base,0x05 | (6) << 8);
00724         //Vertical displayed
00725         IO_WriteW(crtc_base,0x06 | (CurMode->vdispend) << 8);
00726         //Vertical sync position
00727         IO_WriteW(crtc_base,0x07 | (CurMode->vdispend + ((CurMode->vtotal - CurMode->vdispend)/2)-1) << 8);
00728         //Maximum scanline
00729         Bit8u scanline,crtpage;
00730         scanline=8;
00731         switch(CurMode->type) {
00732         case M_TEXT: // text mode character height
00733                 if (machine==MCH_HERC) scanline=14;
00734                 else scanline=8;
00735                 break;
00736         case M_CGA2: // graphics mode: even/odd banks interleaved
00737                 scanline=2;
00738                 break;
00739         case M_CGA4:
00740                 if (CurMode->mode!=0xa) scanline=2;
00741                 else scanline=4;
00742                 break;
00743         case M_TANDY16:
00744                 if (CurMode->mode!=0x9) scanline=2;
00745                 else scanline=4;
00746                 break;
00747         default:
00748                 break;
00749         }
00750         IO_WriteW(crtc_base,0x09 | (scanline-1u) << 8u);
00751         //Setup the CGA palette using VGA DAC palette
00752         for (Bit8u ct=0;ct<16;ct++) VGA_DAC_SetEntry(ct,cga_palette[ct][0],cga_palette[ct][1],cga_palette[ct][2]);
00753         //Setup the tandy palette
00754         for (Bit8u ct=0;ct<16;ct++) VGA_DAC_CombineColor(ct,ct);
00755         //Setup the special registers for each machine type
00756         Bit8u mode_control_list[0xa+1]={
00757                 0x2c,0x28,0x2d,0x29,    //0-3
00758                 0x2a,0x2e,0x1e,0x29,    //4-7
00759                 0x2a,0x2b,0x3b                  //8-a
00760         };
00761         Bit8u mode_control_list_pcjr[0xa+1]={
00762                 0x0c,0x08,0x0d,0x09,    //0-3
00763                 0x0a,0x0e,0x0e,0x09,    //4-7           
00764                 0x1a,0x1b,0x0b                  //8-a
00765         };
00766         Bit8u mode_control,color_select;
00767         switch (machine) {
00768         case MCH_HERC:
00769                 IO_WriteB(0x3b8,0x28);  // TEXT mode and blinking characters
00770 
00771                 Herc_Palette();
00772                 VGA_DAC_CombineColor(0,0);
00773 
00774                 real_writeb(BIOSMEM_SEG,BIOSMEM_CURRENT_MSR,0x29); // attribute controls blinking
00775                 break;
00776         case MCH_AMSTRAD:
00777                 IO_WriteB( 0x3d9, 0x0f );
00778         case MCH_CGA:
00779                 mode_control=mode_control_list[CurMode->mode];
00780                 if (CurMode->mode == 0x6) color_select=0x3f;
00781                 else color_select=0x30;
00782                 IO_WriteB(0x3d8,mode_control);
00783                 IO_WriteB(0x3d9,color_select);
00784                 real_writeb(BIOSMEM_SEG,BIOSMEM_CURRENT_MSR,mode_control);
00785                 real_writeb(BIOSMEM_SEG,BIOSMEM_CURRENT_PAL,color_select);
00786                 if (mono_cga) Mono_CGA_Palette();
00787                 break;
00788         case MCH_TANDY:
00789                 /* Init some registers */
00790                 IO_WriteB(0x3da,0x1);IO_WriteB(0x3de,0xf);              //Palette mask always 0xf
00791                 IO_WriteB(0x3da,0x2);IO_WriteB(0x3de,0x0);              //black border
00792                 IO_WriteB(0x3da,0x3);                                                   //Tandy color overrides?
00793                 switch (CurMode->mode) {
00794                 case 0x8:       
00795                         IO_WriteB(0x3de,0x14);break;
00796                 case 0x9:
00797                         IO_WriteB(0x3de,0x14);break;
00798                 case 0xa:
00799                         IO_WriteB(0x3de,0x0c);break;
00800                 default:
00801                         IO_WriteB(0x3de,0x0);break;
00802                 }
00803                 // write palette
00804                 for(Bitu i = 0; i < 16; i++) {
00805                         IO_WriteB(0x3da,i+0x10);
00806                         IO_WriteB(0x3de,i);
00807                 }
00808                 //Clear extended mapping
00809                 IO_WriteB(0x3da,0x5);
00810                 IO_WriteB(0x3de,0x0);
00811                 //Clear monitor mode
00812                 IO_WriteB(0x3da,0x8);
00813                 IO_WriteB(0x3de,0x0);
00814                 crtpage=(CurMode->mode>=0x9) ? 0xf6 : 0x3f;
00815                 IO_WriteB(0x3df,crtpage);
00816                 real_writeb(BIOSMEM_SEG,BIOSMEM_CRTCPU_PAGE,crtpage);
00817                 mode_control=mode_control_list[CurMode->mode];
00818                 if (CurMode->mode == 0x6 || CurMode->mode==0xa) color_select=0x3f;
00819                 else color_select=0x30;
00820                 IO_WriteB(0x3d8,mode_control);
00821                 IO_WriteB(0x3d9,color_select);
00822                 real_writeb(BIOSMEM_SEG,BIOSMEM_CURRENT_MSR,mode_control);
00823                 real_writeb(BIOSMEM_SEG,BIOSMEM_CURRENT_PAL,color_select);
00824                 break;
00825         case MCH_PCJR:
00826                 /* Init some registers */
00827                 IO_ReadB(0x3da);
00828                 IO_WriteB(0x3da,0x1);IO_WriteB(0x3da,0xf);              //Palette mask always 0xf
00829                 IO_WriteB(0x3da,0x2);IO_WriteB(0x3da,0x0);              //black border
00830                 IO_WriteB(0x3da,0x3);
00831                 if (CurMode->mode<=0x04) IO_WriteB(0x3da,0x02);
00832                 else if (CurMode->mode==0x06) IO_WriteB(0x3da,0x08);
00833                 else IO_WriteB(0x3da,0x00);
00834 
00835                 /* set CRT/Processor page register */
00836                 if (CurMode->mode<0x04) crtpage=0x3f;
00837                 else if (CurMode->mode>=0x09) crtpage=0xf6;
00838                 else crtpage=0x7f;
00839                 IO_WriteB(0x3df,crtpage);
00840                 real_writeb(BIOSMEM_SEG,BIOSMEM_CRTCPU_PAGE,crtpage);
00841 
00842                 mode_control=mode_control_list_pcjr[CurMode->mode];
00843                 IO_WriteB(0x3da,0x0);IO_WriteB(0x3da,mode_control);
00844                 real_writeb(BIOSMEM_SEG,BIOSMEM_CURRENT_MSR,mode_control);
00845 
00846                 if (CurMode->mode == 0x6 || CurMode->mode==0xa) color_select=0x3f;
00847                 else color_select=0x30;
00848                 real_writeb(BIOSMEM_SEG,BIOSMEM_CURRENT_PAL,color_select);
00849                 INT10_SetColorSelect(1);
00850                 INT10_SetBackgroundBorder(0);
00851                 break;
00852         default:
00853                 break;
00854         }
00855 
00856         // Check if the program wants us to use a custom mode table
00857         RealPt vparams = RealGetVec(0x1d);
00858         if (vparams != 0 && (vparams != BIOS_VIDEO_TABLE_LOCATION) && (mode < 8)) {
00859                 // load crtc parameters from video params table
00860                 Bit16u crtc_block_index = 0;
00861                 if (mode < 2) crtc_block_index = 0;
00862                 else if (mode < 4) crtc_block_index = 1;
00863                 else if (mode < 7) crtc_block_index = 2;
00864                 else if (mode == 7) crtc_block_index = 3; // MDA mono mode; invalid for others
00865                 else if (mode < 9) crtc_block_index = 2;
00866                 else crtc_block_index = 3; // Tandy/PCjr modes
00867 
00868                 // init CRTC registers
00869                 for (Bit16u i = 0; i < 16; i++)
00870                         IO_WriteW(crtc_base, (uint16_t)(i | (real_readb(RealSeg(vparams), 
00871                                 RealOff(vparams) + i + crtc_block_index*16) << 8)));
00872         }
00873         FinishSetMode(clearmem);
00874 
00875         if (en_int33) INT10_SetCurMode();
00876 
00877         return true;
00878 }
00879 
00880 bool unmask_irq0_on_int10_setmode = true;
00881 
00882 bool INT10_SetVideoMode(Bit16u mode) {
00883         //LOG_MSG("set mode %x",mode);
00884         bool clearmem=true;Bitu i;
00885         if (mode>=0x100) {
00886                 if ((mode & 0x4000) && int10.vesa_nolfb) return false;
00887                 if (mode & 0x8000) clearmem=false;
00888                 mode&=0xfff;
00889         }
00890         if ((mode<0x100) && (mode & 0x80)) {
00891                 clearmem=false;
00892                 mode-=0x80;
00893         }
00894 
00895     if (unmask_irq0_on_int10_setmode) {
00896         /* setting the video mode unmasks certain IRQs as a matter of course */
00897         PIC_SetIRQMask(0,false); /* Enable system timer */
00898     }
00899 
00900         int10.vesa_setmode=0xffff;
00901         LOG(LOG_INT10,LOG_NORMAL)("Set Video Mode %X",mode);
00902         if (!IS_EGAVGA_ARCH) return INT10_SetVideoMode_OTHER(mode,clearmem);
00903 
00904         /* First read mode setup settings from bios area */
00905 //      Bit8u video_ctl=real_readb(BIOSMEM_SEG,BIOSMEM_VIDEO_CTL);
00906 //      Bit8u vga_switches=real_readb(BIOSMEM_SEG,BIOSMEM_SWITCHES);
00907         Bit8u modeset_ctl=real_readb(BIOSMEM_SEG,BIOSMEM_MODESET_CTL);
00908 
00909         if (IS_VGA_ARCH) {
00910                 if (svga.accepts_mode) {
00911                         if (!svga.accepts_mode(mode)) return false;
00912                 }
00913 
00914                 switch(svgaCard) {
00915                 case SVGA_TsengET4K:
00916                 case SVGA_TsengET3K:
00917                         if (!SetCurMode(ModeList_VGA_Tseng,mode)){
00918                                 LOG(LOG_INT10,LOG_ERROR)("VGA:Trying to set illegal mode %X",mode);
00919                                 return false;
00920                         }
00921                         break;
00922                 case SVGA_ParadisePVGA1A:
00923                         if (!SetCurMode(ModeList_VGA_Paradise,mode)){
00924                                 LOG(LOG_INT10,LOG_ERROR)("VGA:Trying to set illegal mode %X",mode);
00925                                 return false;
00926                         }
00927                         break;
00928                 default:
00929                         if (!SetCurMode(ModeList_VGA,mode)){
00930                                 LOG(LOG_INT10,LOG_ERROR)("VGA:Trying to set illegal mode %X",mode);
00931                                 return false;
00932                         }
00933                 }
00934                 // check for scanline backwards compatibility (VESA text modes??)
00935                 if (CurMode->type==M_TEXT) {
00936                         if ((modeset_ctl&0x90)==0x80) { // 200 lines emulation
00937                                 if (CurMode->mode <= 3) {
00938                                         CurMode = &ModeList_VGA_Text_200lines[CurMode->mode];
00939                                 }
00940                         } else if ((modeset_ctl&0x90)==0x00) { // 350 lines emulation
00941                                 if (CurMode->mode <= 3) {
00942                                         CurMode = &ModeList_VGA_Text_350lines[CurMode->mode];
00943                                 }
00944                         }
00945                 }
00946         } else {
00947                 if (!SetCurMode(ModeList_EGA,mode)){
00948                         LOG(LOG_INT10,LOG_ERROR)("EGA:Trying to set illegal mode %X",mode);
00949                         return false;
00950                 }
00951         }
00952 
00953         /* Setup the VGA to the correct mode */
00954         // turn off video
00955         IO_Write(0x3c4,0); IO_Write(0x3c5,1); // reset
00956         IO_Write(0x3c4,1); IO_Write(0x3c5,0x20); // screen off
00957 
00958         Bit16u crtc_base;
00959         bool mono_mode=(mode == 7) || (mode==0xf);  
00960         if (mono_mode) crtc_base=0x3b4;
00961         else crtc_base=0x3d4;
00962 
00963         /* Setup MISC Output Register */
00964         Bit8u misc_output=0x2 | (mono_mode ? 0x0 : 0x1);
00965 
00966         if (machine==MCH_EGA) {
00967                 // 16MHz clock for 350-line EGA modes except mode F
00968                 if ((CurMode->vdispend==350) && (mode!=0xf)) misc_output|=0x4;
00969         } else {
00970                 // 28MHz clock for 9-pixel wide chars
00971                 if ((CurMode->type==M_TEXT) && (CurMode->cwidth==9)) misc_output|=0x4;
00972         }
00973 
00974         switch (CurMode->vdispend) {
00975         case 400: 
00976                 misc_output|=0x60;
00977                 break;
00978         case 480:
00979                 misc_output|=0xe0;
00980                 break;
00981         case 350:
00982                 misc_output|=0xa0;
00983                 break;
00984         case 200:
00985         default:
00986                 misc_output|=0x20;
00987         }
00988         IO_Write(0x3c2,misc_output);            //Setup for 3b4 or 3d4
00989         
00990         if (IS_VGA_ARCH && (svgaCard == SVGA_S3Trio)) {
00991         // unlock the S3 registers
00992                 IO_Write(crtc_base,0x38);IO_Write(crtc_base+1u,0x48);   //Register lock 1
00993                 IO_Write(crtc_base,0x39);IO_Write(crtc_base+1u,0xa5);   //Register lock 2
00994                 IO_Write(0x3c4,0x8);IO_Write(0x3c5,0x06);
00995                 // Disable MMIO here so we can read / write memory
00996                 IO_Write(crtc_base,0x53);IO_Write(crtc_base+1u,0x0);
00997         }
00998         
00999         /* Program Sequencer */
01000         Bit8u seq_data[SEQ_REGS];
01001         memset(seq_data,0,SEQ_REGS);
01002         
01003         seq_data[0] = 0x3;      // not reset
01004         seq_data[1] = 0x21;     // screen still disabled, will be enabled at end of setmode
01005         seq_data[4] = 0x04;     // odd/even disable
01006         
01007         if (CurMode->special & _EGA_HALF_CLOCK) seq_data[1]|=0x08; //Check for half clock
01008         if ((machine==MCH_EGA) && (CurMode->special & _EGA_HALF_CLOCK)) seq_data[1]|=0x02;
01009 
01010         if (IS_VGA_ARCH || (IS_EGA_ARCH && vga.mem.memsize >= 0x20000))
01011         seq_data[4]|=0x02;      //More than 64kb
01012     else if (IS_EGA_ARCH && CurMode->vdispend==350) {
01013         seq_data[4] &= ~0x04; // turn on odd/even
01014         seq_data[1] |= 0x04; // half clock
01015     }
01016 
01017         switch (CurMode->type) {
01018         case M_TEXT:
01019                 if (CurMode->cwidth==9) seq_data[1] &= ~1;
01020                 seq_data[2]|=0x3;                               //Enable plane 0 and 1
01021                 seq_data[4]|=0x01;                              //Alpanumeric
01022                 seq_data[4]&=~0x04;                             //odd/even enable
01023                 break;
01024         case M_CGA2:
01025                 if (IS_EGAVGA_ARCH) {
01026                         seq_data[2]|=0x1;                       //Enable plane 0. Most VGA cards treat it as a 640x200 variant of the MCGA 2-color mode, with bit 13 remapped for interlace
01027                 }
01028                 break;
01029         case M_CGA4:
01030                 if (IS_EGAVGA_ARCH) {
01031                         seq_data[2]|=0x3;                       //Enable plane 0 and 1
01032                         seq_data[4]&=~0x04;                     //odd/even enable
01033                 }
01034                 break;
01035         case M_LIN4:
01036         case M_EGA:
01037                 seq_data[2]|=0xf;                               //Enable all planes for writing
01038                 break;
01039         case M_LIN8:                                            //Seems to have the same reg layout from testing
01040         case M_LIN15:
01041         case M_LIN16:
01042         case M_LIN24:
01043         case M_LIN32:
01044         case M_VGA:
01045                 seq_data[2]|=0xf;                               //Enable all planes for writing
01046                 seq_data[4]|=0x8;                               //Graphics - Chained
01047                 break;
01048         default:
01049                 break;
01050         }
01051         for (Bit8u ct=0;ct<SEQ_REGS;ct++) {
01052                 IO_Write(0x3c4,ct);
01053                 IO_Write(0x3c5,seq_data[ct]);
01054         }
01055 
01056         /* NTS: S3 INT 10 modesetting code below sets this bit anyway when writing CRTC register 0x31.
01057          *      It needs to be done as I/O port write so that Windows 95 can virtualize it properly when
01058          *      we're called to set INT10 mode 3 (from within virtual 8086 mode) when opening a DOS box.
01059          *
01060          *      If we just set it directly, then the generic S3 driver in Windows 95 cannot trap the I/O
01061          *      and prevent our own INT 10h handler from setting the VGA memory mapping into "compatible
01062          *      chain 4" mode, and then any non accelerated drawing from the Windows driver becomes a
01063          *      garbled mess spread out across the screen (due to the weird way that VGA planar memory
01064          *      is "chained" on SVGA chipsets).
01065          *
01066          *      The S3 linear framebuffer isn't affected by VGA chained mode, which is why only the
01067          *      generic S3 driver was affected by this bug, since the generic S3 driver is the one that
01068          *      uses only VGA access (0xA0000-0xAFFFF) and SVGA bank switching while the more specific
01069          *      "S3 Trio32 PCI" driver uses the linear framebuffer.
01070          *
01071          *      But to avoid breaking other SVGA emulation in DOSBox-X, we still set this manually for
01072          *      other VGA/SVGA emulation cases, just not S3 Trio emulation. */
01073         if (svgaCard != SVGA_S3Trio)
01074                 vga.config.compatible_chain4 = true; // this may be changed by SVGA chipset emulation
01075 
01076         if( machine==MCH_AMSTRAD )
01077         {
01078                 vga.amstrad.mask_plane = 0x07070707;
01079                 vga.amstrad.write_plane = 0x0F;
01080                 vga.amstrad.read_plane = 0x00;
01081                 vga.amstrad.border_color = 0x00;
01082         }
01083 
01084         /* Program CRTC */
01085         /* First disable write protection */
01086         IO_Write(crtc_base,0x11);
01087         IO_Write(crtc_base+1u,IO_Read(crtc_base+1u)&0x7f);
01088         /* Clear all the regs */
01089         for (Bit8u ct=0x0;ct<=0x18;ct++) {
01090                 IO_Write(crtc_base,ct);IO_Write(crtc_base+1u,0);
01091         }
01092         Bit8u overflow=0;Bit8u max_scanline=0;
01093         Bit8u ver_overflow=0;Bit8u hor_overflow=0;
01094         /* Horizontal Total */
01095         IO_Write(crtc_base,0x00);IO_Write(crtc_base+1u,(Bit8u)(CurMode->htotal-5));
01096         hor_overflow|=((CurMode->htotal-5) & 0x100) >> 8;
01097         /* Horizontal Display End */
01098         IO_Write(crtc_base,0x01);IO_Write(crtc_base+1u,(Bit8u)(CurMode->hdispend-1));
01099         hor_overflow|=((CurMode->hdispend-1) & 0x100) >> 7;
01100         /* Start horizontal Blanking */
01101         IO_Write(crtc_base,0x02);IO_Write(crtc_base+1u,(Bit8u)CurMode->hdispend);
01102         hor_overflow|=((CurMode->hdispend) & 0x100) >> 6;
01103         /* End horizontal Blanking */
01104         Bitu blank_end=(CurMode->htotal-2) & 0x7f;
01105         IO_Write(crtc_base,0x03);IO_Write(crtc_base+1u,0x80|(blank_end & 0x1f));
01106 
01107         /* Start Horizontal Retrace */
01108         Bitu ret_start;
01109         if ((CurMode->special & _EGA_HALF_CLOCK) && (CurMode->type!=M_CGA2)) ret_start = (CurMode->hdispend+3);
01110         else if (CurMode->type==M_TEXT) ret_start = (CurMode->hdispend+5);
01111         else ret_start = (CurMode->hdispend+4);
01112         IO_Write(crtc_base,0x04);IO_Write(crtc_base+1u,(Bit8u)ret_start);
01113         hor_overflow|=(ret_start & 0x100) >> 4;
01114 
01115         /* End Horizontal Retrace */
01116         Bitu ret_end;
01117         if (CurMode->special & _EGA_HALF_CLOCK) {
01118                 if (CurMode->type==M_CGA2) ret_end=0;   // mode 6
01119                 else if (CurMode->special & _DOUBLESCAN) ret_end = (CurMode->htotal-18) & 0x1f;
01120                 else ret_end = ((CurMode->htotal-18) & 0x1f) | 0x20; // mode 0&1 have 1 char sync delay
01121         } else if (CurMode->type==M_TEXT) ret_end = (CurMode->htotal-3) & 0x1f;
01122         else ret_end = (CurMode->htotal-4) & 0x1f;
01123         
01124         IO_Write(crtc_base,0x05);IO_Write(crtc_base+1u,(Bit8u)(ret_end | (blank_end & 0x20) << 2));
01125 
01126         /* Vertical Total */
01127         IO_Write(crtc_base,0x06);IO_Write(crtc_base+1u,(Bit8u)(CurMode->vtotal-2));
01128         overflow|=((CurMode->vtotal-2) & 0x100) >> 8;
01129         overflow|=((CurMode->vtotal-2) & 0x200) >> 4;
01130         ver_overflow|=((CurMode->vtotal-2) & 0x400) >> 10;
01131 
01132         Bitu vretrace;
01133         if (IS_VGA_ARCH) {
01134                 switch (CurMode->vdispend) {
01135                 case 400: vretrace=CurMode->vdispend+12;
01136                                 break;
01137                 case 480: vretrace=CurMode->vdispend+10;
01138                                 break;
01139                 case 350: vretrace=CurMode->vdispend+37;
01140                                 break;
01141                 default: vretrace=CurMode->vdispend+12;
01142                 }
01143         } else {
01144                 switch (CurMode->vdispend) {
01145                 case 350: vretrace=CurMode->vdispend;
01146                                 break;
01147                 default: vretrace=CurMode->vdispend+24;
01148                 }
01149         }
01150 
01151         /* Vertical Retrace Start */
01152         IO_Write(crtc_base,0x10);IO_Write(crtc_base+1u,(Bit8u)vretrace);
01153         overflow|=(vretrace & 0x100) >> 6;
01154         overflow|=(vretrace & 0x200) >> 2;
01155         ver_overflow|=(vretrace & 0x400) >> 6;
01156 
01157         /* Vertical Retrace End */
01158         IO_Write(crtc_base,0x11);IO_Write(crtc_base+1u,(vretrace+2) & 0xF);
01159 
01160         /* Vertical Display End */
01161         IO_Write(crtc_base,0x12);IO_Write(crtc_base+1u,(Bit8u)(CurMode->vdispend-1));
01162         overflow|=((CurMode->vdispend-1) & 0x100) >> 7;
01163         overflow|=((CurMode->vdispend-1) & 0x200) >> 3;
01164         ver_overflow|=((CurMode->vdispend-1) & 0x400) >> 9;
01165         
01166         Bitu vblank_trim;
01167         if (IS_VGA_ARCH) {
01168                 switch (CurMode->vdispend) {
01169                 case 400: vblank_trim=6;
01170                                 break;
01171                 case 480: vblank_trim=7;
01172                                 break;
01173                 case 350: vblank_trim=5;
01174                                 break;
01175                 default: vblank_trim=8;
01176                 }
01177         } else {
01178                 switch (CurMode->vdispend) {
01179                 case 350: vblank_trim=0;
01180                                 break;
01181                 default: vblank_trim=23;
01182                 }
01183         }
01184 
01185         /* Vertical Blank Start */
01186         IO_Write(crtc_base,0x15);IO_Write(crtc_base+1u,(Bit8u)(CurMode->vdispend+vblank_trim));
01187         overflow|=((CurMode->vdispend+vblank_trim) & 0x100) >> 5;
01188         max_scanline|=((CurMode->vdispend+vblank_trim) & 0x200) >> 4;
01189         ver_overflow|=((CurMode->vdispend+vblank_trim) & 0x400) >> 8;
01190 
01191         /* Vertical Blank End */
01192         IO_Write(crtc_base,0x16);IO_Write(crtc_base+1u,(Bit8u)(CurMode->vtotal-vblank_trim-2));
01193 
01194         /* Line Compare */
01195         Bitu line_compare=(CurMode->vtotal < 1024) ? 1023 : 2047;
01196         IO_Write(crtc_base,0x18);IO_Write(crtc_base+1u,line_compare&0xff);
01197         overflow|=(line_compare & 0x100) >> 4;
01198         max_scanline|=(line_compare & 0x200) >> 3;
01199         ver_overflow|=(line_compare & 0x400) >> 4;
01200         Bit8u underline=0;
01201         /* Maximum scanline / Underline Location */
01202         if (CurMode->special & _DOUBLESCAN) max_scanline|=0x80;
01203         if (CurMode->special & _REPEAT1) max_scanline|=0x01;
01204 
01205         switch (CurMode->type) {
01206         case M_TEXT:
01207                 if(IS_VGA_ARCH) {
01208                         switch(modeset_ctl & 0x90) {
01209                         case 0x0: // 350-lines mode: 8x14 font
01210                                 max_scanline |= (14-1);
01211                                 break;
01212                         default: // reserved
01213                         case 0x10: // 400 lines 8x16 font
01214                 max_scanline|=CurMode->cheight-1;
01215                                 break;
01216                         case 0x80: // 200 lines: 8x8 font and doublescan
01217                                 max_scanline |= (8-1);
01218                                 max_scanline |= 0x80;
01219                                 break;
01220                         }
01221                 } else max_scanline |= CurMode->cheight-1;
01222                 underline=mono_mode ? 0x0f : 0x1f; // mode 7 uses a diff underline position
01223                 break;
01224         case M_VGA:
01225                 underline=0x40;
01226                 break;
01227         case M_LIN8:
01228         case M_LIN15:
01229         case M_LIN16:
01230         case M_LIN24:
01231         case M_LIN32:
01232                 underline=0x60;                 //Seems to enable the every 4th clock on my s3
01233                 break;
01234         default:
01235                 break;
01236         }
01237 
01238     /* do NOT apply this to VESA BIOS modes */
01239         if (CurMode->mode < 0x100 && CurMode->vdispend==350) underline=0x0f;
01240 
01241         IO_Write(crtc_base,0x09);IO_Write(crtc_base+1u,max_scanline);
01242         IO_Write(crtc_base,0x14);IO_Write(crtc_base+1u,underline);
01243 
01244         /* OverFlow */
01245         IO_Write(crtc_base,0x07);IO_Write(crtc_base+1u,overflow);
01246 
01247         if (svgaCard == SVGA_S3Trio) {
01248                 /* Extended Horizontal Overflow */
01249                 IO_Write(crtc_base,0x5d);IO_Write(crtc_base+1u,hor_overflow);
01250                 /* Extended Vertical Overflow */
01251                 IO_Write(crtc_base,0x5e);IO_Write(crtc_base+1u,ver_overflow);
01252         }
01253 
01254         /* Offset Register */
01255         Bitu offset;
01256         switch (CurMode->type) {
01257         case M_LIN8:
01258                 offset = CurMode->swidth/8;
01259                 break;
01260         case M_LIN15:
01261         case M_LIN16:
01262                 offset = 2 * CurMode->swidth/8;
01263                 break;
01264         case M_LIN24:
01265                 offset = 3 * CurMode->swidth/8;
01266                 break;
01267         case M_LIN32:
01268                 offset = 4 * CurMode->swidth/8;
01269                 break;
01270     case M_EGA:
01271         if (IS_EGA_ARCH && vga.mem.memsize < 0x20000 && CurMode->vdispend==350)
01272             offset = CurMode->hdispend/4;
01273         else
01274             offset = CurMode->hdispend/2;
01275                 break;
01276         default:
01277         offset = CurMode->hdispend/2;
01278         break;
01279     }
01280         IO_Write(crtc_base,0x13);
01281         IO_Write(crtc_base + 1u,offset & 0xff);
01282 
01283         if (svgaCard == SVGA_S3Trio) {
01284                 /* Extended System Control 2 Register  */
01285                 /* This register actually has more bits but only use the extended offset ones */
01286                 IO_Write(crtc_base,0x51);
01287                 IO_Write(crtc_base + 1u,(Bit8u)((offset & 0x300) >> 4));
01288                 /* Clear remaining bits of the display start */
01289                 IO_Write(crtc_base,0x69);
01290                 IO_Write(crtc_base + 1u,0);
01291                 /* Extended Vertical Overflow */
01292                 IO_Write(crtc_base,0x5e);IO_Write(crtc_base+1u,ver_overflow);
01293         }
01294 
01295         /* Mode Control */
01296         Bit8u mode_control=0;
01297 
01298         switch (CurMode->type) {
01299         case M_CGA2:
01300                 mode_control=0xc2; // 0x06 sets address wrap.
01301                 break;
01302         case M_CGA4:
01303                 mode_control=0xa2;
01304                 break;
01305         case M_LIN4:
01306         case M_EGA:
01307         if (CurMode->mode==0x11) // 0x11 also sets address wrap.  thought maybe all 2 color modes did but 0x0f doesn't.
01308             mode_control=0xc3; // so.. 0x11 or 0x0f a one off?
01309         else
01310             mode_control=0xe3;
01311 
01312         if (IS_EGA_ARCH && vga.mem.memsize < 0x20000 && CurMode->vdispend==350)
01313             mode_control &= ~0x40; // word mode
01314                 break;
01315         case M_TEXT:
01316         case M_VGA:
01317         case M_LIN8:
01318         case M_LIN15:
01319         case M_LIN16:
01320         case M_LIN24:
01321         case M_LIN32:
01322                 mode_control=0xa3;
01323                 if (CurMode->special & _VGA_PIXEL_DOUBLE)
01324                         mode_control |= 0x08;
01325                 break;
01326         default:
01327                 break;
01328         }
01329 
01330     if (IS_EGA_ARCH && vga.mem.memsize < 0x20000)
01331         mode_control &= ~0x20; // address wrap bit 13
01332 
01333         IO_Write(crtc_base,0x17);IO_Write(crtc_base+1u,mode_control);
01334         /* Renable write protection */
01335         IO_Write(crtc_base,0x11);
01336         IO_Write(crtc_base+1u,IO_Read(crtc_base+1u)|0x80);
01337 
01338         if (svgaCard == SVGA_S3Trio) {
01339                 /* Setup the correct clock */
01340                 if (CurMode->mode>=0x100) {
01341                         misc_output|=0xef;              //Select clock 3 
01342                         Bitu clock=CurMode->vtotal*8*CurMode->htotal*70;
01343                         if(CurMode->type==M_LIN15 || CurMode->type==M_LIN16) clock/=2;
01344                         VGA_SetClock(3,clock/1000);
01345                 }
01346                 Bit8u misc_control_2;
01347                 /* Setup Pixel format */
01348                 switch (CurMode->type) {
01349                 case M_LIN8:
01350                 default:
01351                         misc_control_2=0x00;
01352                         break;
01353                 case M_LIN15:
01354                         misc_control_2=0x30;
01355                         break;
01356                 case M_LIN16:
01357                         misc_control_2=0x50;
01358                         break;
01359                 case M_LIN24:
01360                         misc_control_2=0x70; /* FIXME: Is this right? I have no other reference than comments in vga_s3.cpp and s3freak's patch */
01361                         break;
01362                 case M_LIN32:
01363                         misc_control_2=0xd0;
01364                         break;
01365                 }
01366                 IO_WriteB(crtc_base,0x67);IO_WriteB(crtc_base+1u,misc_control_2);
01367         }
01368 
01369         /* Write Misc Output */
01370         IO_Write(0x3c2,misc_output);
01371         /* Program Graphics controller */
01372         Bit8u gfx_data[GFX_REGS];
01373         memset(gfx_data,0,GFX_REGS);
01374         gfx_data[0x7]=0xf;                              /* Color don't care */
01375         gfx_data[0x8]=0xff;                             /* BitMask */
01376         switch (CurMode->type) {
01377         case M_TEXT:
01378                 gfx_data[0x5]|=0x10;            //Odd-Even Mode
01379                 gfx_data[0x6]|=mono_mode ? 0x0a : 0x0e;         //Either b800 or b000, chain odd/even enable
01380                 break;
01381         case M_LIN8:
01382         case M_LIN15:
01383         case M_LIN16:
01384         case M_LIN24:
01385         case M_LIN32:
01386                 gfx_data[0x5]|=0x40;            //256 color mode
01387         if (int10_vesa_map_as_128kb)
01388                 gfx_data[0x6]|=0x01;    //graphics mode at 0xa000-bffff
01389         else
01390                 gfx_data[0x6]|=0x05;    //graphics mode at 0xa000-affff
01391                 break;
01392         case M_VGA:
01393                 gfx_data[0x5]|=0x40;            //256 color mode
01394                 gfx_data[0x6]|=0x05;            //graphics mode at 0xa000-affff
01395                 break;
01396         case M_LIN4:
01397         case M_EGA:
01398         if (IS_EGA_ARCH && vga.mem.memsize < 0x20000 && CurMode->vdispend==350) {
01399             gfx_data[0x5]|=0x10;                //Odd-Even Mode
01400             gfx_data[0x6]|=0x02;                //Odd-Even Mode
01401                 gfx_data[0x7]=0x5;                      /* Color don't care */
01402         }
01403                 gfx_data[0x6]|=0x05;            //graphics mode at 0xa000-affff
01404                 break;
01405         case M_CGA4:
01406                 gfx_data[0x5]|=0x20;            //CGA mode
01407                 gfx_data[0x6]|=0x0f;            //graphics mode at at 0xb800=0xbfff
01408                 if (IS_EGAVGA_ARCH) gfx_data[0x5]|=0x10;
01409                 break;
01410         case M_CGA2:
01411                 gfx_data[0x6]|=0x0d;            //graphics mode at at 0xb800=0xbfff, chain odd/even disabled
01412                 break;
01413         default:
01414                 break;
01415         }
01416         for (Bit8u ct=0;ct<GFX_REGS;ct++) {
01417                 IO_Write(0x3ce,ct);
01418                 IO_Write(0x3cf,gfx_data[ct]);
01419         }
01420         Bit8u att_data[ATT_REGS];
01421         memset(att_data,0,ATT_REGS);
01422         att_data[0x12]=0xf;                             //Always have all color planes enabled
01423         /* Program Attribute Controller */
01424         switch (CurMode->type) {
01425         case M_EGA:
01426         case M_LIN4:
01427                 att_data[0x10]=0x01;            //Color Graphics
01428                 switch (CurMode->mode) {
01429                 case 0x0f:
01430                         att_data[0x12]=0x05;    // planes 0 and 2 enabled
01431                         att_data[0x10]|=0x0a;   // monochrome and blinking
01432         
01433                         att_data[0x01]=0x08; // low-intensity
01434                         att_data[0x04]=0x18; // blink-on case
01435                         att_data[0x05]=0x18; // high-intensity
01436                         att_data[0x09]=0x08; // low-intensity in blink-off case
01437                         att_data[0x0d]=0x18; // high-intensity in blink-off
01438                         break;
01439                 case 0x11:
01440                         for (i=1;i<16;i++) att_data[i]=0x3f;
01441                         break;
01442                 case 0x10:
01443                 case 0x12: 
01444                         goto att_text16;
01445                 default:
01446                         if ( CurMode->type == M_LIN4 )
01447                                 goto att_text16;
01448                         for (Bit8u ct=0;ct<8;ct++) {
01449                                 att_data[ct]=ct;
01450                                 att_data[ct+8]=ct+0x10;
01451                         }
01452                         break;
01453                 }
01454                 break;
01455         case M_TANDY16:
01456                 att_data[0x10]=0x01;            //Color Graphics
01457                 for (Bit8u ct=0;ct<16;ct++) att_data[ct]=ct;
01458                 break;
01459         case M_TEXT:
01460                 if (CurMode->cwidth==9) {
01461                         att_data[0x13]=0x08;    //Pel panning on 8, although we don't have 9 dot text mode
01462                         att_data[0x10]=0x0C;    //Color Text with blinking, 9 Bit characters
01463                 } else {
01464                         att_data[0x13]=0x00;
01465                         att_data[0x10]=0x08;    //Color Text with blinking, 8 Bit characters
01466                 }
01467                 real_writeb(BIOSMEM_SEG,BIOSMEM_CURRENT_PAL,0x30);
01468 att_text16:
01469                 if (CurMode->mode==7) {
01470                         att_data[0]=0x00;
01471                         att_data[8]=0x10;
01472                         for (i=1; i<8; i++) {
01473                                 att_data[i]=0x08;
01474                                 att_data[i+8]=0x18;
01475                         }
01476                 } else {
01477                         for (Bit8u ct=0;ct<8;ct++) {
01478                                 att_data[ct]=ct;
01479                                 att_data[ct+8]=ct+0x38;
01480                         }
01481                         if (IS_VGA_ARCH) att_data[0x06]=0x14;           //Odd Color 6 yellow/brown.
01482                 }
01483                 break;
01484         case M_CGA2:
01485                 att_data[0x10]=0x01;            //Color Graphics
01486                 att_data[0]=0x0;
01487                 for (i=1;i<0x10;i++) att_data[i]=0x17;
01488                 att_data[0x12]=0x1;                     //Only enable 1 plane
01489                 real_writeb(BIOSMEM_SEG,BIOSMEM_CURRENT_PAL,0x3f);
01490                 break;
01491         case M_CGA4:
01492                 att_data[0x10]=0x01;            //Color Graphics
01493                 att_data[0]=0x0;
01494                 att_data[1]=0x13;
01495                 att_data[2]=0x15;
01496                 att_data[3]=0x17;
01497                 att_data[4]=0x02;
01498                 att_data[5]=0x04;
01499                 att_data[6]=0x06;
01500                 att_data[7]=0x07;
01501                 for (Bit8u ct=0x8;ct<0x10;ct++) 
01502                         att_data[ct] = ct + 0x8;
01503                 real_writeb(BIOSMEM_SEG,BIOSMEM_CURRENT_PAL,0x30);
01504                 break;
01505         case M_VGA:
01506         case M_LIN8:
01507         case M_LIN15:
01508         case M_LIN16:
01509         case M_LIN24:
01510         case M_LIN32:
01511                 for (Bit8u ct=0;ct<16;ct++) att_data[ct]=ct;
01512                 att_data[0x10]=0x41;            //Color Graphics 8-bit
01513                 break;
01514         default:
01515                 break;
01516         }
01517         IO_Read(mono_mode ? 0x3ba : 0x3da);
01518         if ((modeset_ctl & 8)==0) {
01519                 for (Bit8u ct=0;ct<ATT_REGS;ct++) {
01520                         IO_Write(0x3c0,ct);
01521                         IO_Write(0x3c0,att_data[ct]);
01522                 }
01523                 vga.config.pel_panning = 0;
01524                 IO_Write(0x3c0,0x20); IO_Write(0x3c0,0x00); //Disable palette access
01525                 IO_Write(0x3c6,0xff); //Reset Pelmask
01526                 /* Setup the DAC */
01527                 IO_Write(0x3c8,0);
01528                 switch (CurMode->type) {
01529                 case M_EGA:
01530                         if (CurMode->mode>0xf) {
01531                                 goto dac_text16;
01532                         } else if (CurMode->mode==0xf) {
01533                                 for (i=0;i<64;i++) {
01534                                         IO_Write(0x3c9,mtext_s3_palette[i][0]);
01535                                         IO_Write(0x3c9,mtext_s3_palette[i][1]);
01536                                         IO_Write(0x3c9,mtext_s3_palette[i][2]);
01537                                 }
01538                         } else {
01539                                 for (i=0;i<64;i++) {
01540                                         IO_Write(0x3c9,ega_palette[i][0]);
01541                                         IO_Write(0x3c9,ega_palette[i][1]);
01542                                         IO_Write(0x3c9,ega_palette[i][2]);
01543                                 }
01544                         }
01545                         break;
01546                 case M_CGA2:
01547                 case M_CGA4:
01548                 case M_TANDY16:
01549                         for (i=0;i<64;i++) {
01550                                 IO_Write(0x3c9,cga_palette_2[i][0]);
01551                                 IO_Write(0x3c9,cga_palette_2[i][1]);
01552                                 IO_Write(0x3c9,cga_palette_2[i][2]);
01553                         }
01554                         break;
01555                 case M_TEXT:
01556                         if (CurMode->mode==7) {
01557                                 if ((IS_VGA_ARCH) && (svgaCard == SVGA_S3Trio)) {
01558                                         for (i=0;i<64;i++) {
01559                                                 IO_Write(0x3c9,mtext_s3_palette[i][0]);
01560                                                 IO_Write(0x3c9,mtext_s3_palette[i][1]);
01561                                                 IO_Write(0x3c9,mtext_s3_palette[i][2]);
01562                                         }
01563                                 } else {
01564                                         for (i=0;i<64;i++) {
01565                                                 IO_Write(0x3c9,mtext_palette[i][0]);
01566                                                 IO_Write(0x3c9,mtext_palette[i][1]);
01567                                                 IO_Write(0x3c9,mtext_palette[i][2]);
01568                                         }
01569                                 }
01570                                 break;
01571                         } //FALLTHROUGH!!!!
01572                 case M_LIN4: //Added for CAD Software
01573 dac_text16:
01574                         for (i=0;i<64;i++) {
01575                                 IO_Write(0x3c9,text_palette[i][0]);
01576                                 IO_Write(0x3c9,text_palette[i][1]);
01577                                 IO_Write(0x3c9,text_palette[i][2]);
01578                         }
01579                         break;
01580                 case M_VGA:
01581                 case M_LIN8:
01582                 case M_LIN15:
01583                 case M_LIN16:
01584                 case M_LIN24:
01585                 case M_LIN32:
01586                         // IBM and clones use 248 default colors in the palette for 256-color mode.
01587                         // The last 8 colors of the palette are only initialized to 0 at BIOS init.
01588                         // Palette index is left at 0xf8 as on most clones, IBM leaves it at 0x10.
01589                         for (i=0;i<248;i++) {
01590                                 IO_Write(0x3c9,vga_palette[i][0]);
01591                                 IO_Write(0x3c9,vga_palette[i][1]);
01592                                 IO_Write(0x3c9,vga_palette[i][2]);
01593                         }
01594                         break;
01595                 default:
01596                         break;
01597                 }
01598                 if (IS_VGA_ARCH) {
01599                         /* check if gray scale summing is enabled */
01600                         if (modeset_ctl & 2) INT10_PerformGrayScaleSumming(0,256);
01601                 }
01602         /* make sure the DAC index is reset on modeset */
01603                 IO_Write(0x3c7,0); /* according to src/hardware/vga_dac.cpp this sets read_index=0 and write_index=1 */
01604                 IO_Write(0x3c8,0); /* so set write_index=0 */
01605         } else {
01606                 for (Bit8u ct=0x10;ct<ATT_REGS;ct++) {
01607                         if (ct==0x11) continue; // skip overscan register
01608                         IO_Write(0x3c0,ct);
01609                         IO_Write(0x3c0,att_data[ct]);
01610                 }
01611                 vga.config.pel_panning = 0;
01612         }
01613         /* Setup some special stuff for different modes */
01614         Bit8u feature=real_readb(BIOSMEM_SEG,BIOSMEM_INITIAL_MODE);
01615         switch (CurMode->type) {
01616         case M_CGA2:
01617                 feature=(feature&~0x30)|0x20;
01618                 real_writeb(BIOSMEM_SEG,BIOSMEM_CURRENT_MSR,0x1e);
01619                 break;
01620         case M_CGA4:
01621                 feature=(feature&~0x30)|0x20;
01622                 if (CurMode->mode==4) real_writeb(BIOSMEM_SEG,BIOSMEM_CURRENT_MSR,0x2a);
01623                 else if (CurMode->mode==5) real_writeb(BIOSMEM_SEG,BIOSMEM_CURRENT_MSR,0x2e);
01624                 else real_writeb(BIOSMEM_SEG,BIOSMEM_CURRENT_MSR,0x2);
01625                 break;
01626         case M_TANDY16:
01627                 feature=(feature&~0x30)|0x20;
01628                 break;
01629         case M_TEXT:
01630                 feature=(feature&~0x30)|0x20;
01631                 switch (CurMode->mode) {
01632                 case 0:real_writeb(BIOSMEM_SEG,BIOSMEM_CURRENT_MSR,0x2c);break;
01633                 case 1:real_writeb(BIOSMEM_SEG,BIOSMEM_CURRENT_MSR,0x28);break;
01634                 case 2:real_writeb(BIOSMEM_SEG,BIOSMEM_CURRENT_MSR,0x2d);break;
01635                 case 3:
01636                 case 7:real_writeb(BIOSMEM_SEG,BIOSMEM_CURRENT_MSR,0x29);break;
01637                 }
01638                 break;
01639         case M_LIN4:
01640         case M_EGA:     
01641         case M_VGA:
01642                 feature=(feature&~0x30);
01643                 break;
01644         default:
01645                 break;
01646         }
01647         // disabled, has to be set in bios.cpp exclusively
01648 //      real_writeb(BIOSMEM_SEG,BIOSMEM_INITIAL_MODE,feature);
01649 
01650         if (svgaCard == SVGA_S3Trio) {
01651                 /* Setup the CPU Window */
01652                 IO_Write(crtc_base,0x6a);
01653                 IO_Write(crtc_base+1u,0);
01654                 /* Setup the linear frame buffer */
01655                 IO_Write(crtc_base,0x59);
01656                 IO_Write(crtc_base+1u,(Bit8u)((S3_LFB_BASE >> 24)&0xff));
01657                 IO_Write(crtc_base,0x5a);
01658                 IO_Write(crtc_base+1u,(Bit8u)((S3_LFB_BASE >> 16)&0xff));
01659                 IO_Write(crtc_base,0x6b); // BIOS scratchpad
01660                 IO_Write(crtc_base+1u,(Bit8u)((S3_LFB_BASE >> 24)&0xff));
01661                 
01662                 /* Setup some remaining S3 registers */
01663                 IO_Write(crtc_base,0x41); // BIOS scratchpad
01664                 IO_Write(crtc_base+1u,0x88);
01665                 IO_Write(crtc_base,0x52); // extended BIOS scratchpad
01666                 IO_Write(crtc_base+1u,0x80);
01667 
01668                 IO_Write(0x3c4,0x15);
01669                 IO_Write(0x3c5,0x03);
01670 
01671                 IO_Write(crtc_base,0x45);
01672                 IO_Write(crtc_base+1u,0x00);
01673 
01674                 // Accellerator setup 
01675                 Bitu reg_50=S3_XGA_8BPP;
01676                 switch (CurMode->type) {
01677                         case M_LIN15:
01678                         case M_LIN16: reg_50|=S3_XGA_16BPP; break;
01679                         case M_LIN32: reg_50|=S3_XGA_32BPP; break;
01680                         default: break;
01681                 }
01682                 switch(CurMode->swidth) {
01683                         case 640:  reg_50|=S3_XGA_640; break;
01684                         case 800:  reg_50|=S3_XGA_800; break;
01685                         case 1024: reg_50|=S3_XGA_1024; break;
01686                         case 1152: reg_50|=S3_XGA_1152; break;
01687                         case 1280: reg_50|=S3_XGA_1280; break;
01688                         case 1600: reg_50|=S3_XGA_1600; break;
01689                         default: break;
01690                 }
01691                 IO_WriteB(crtc_base,0x50); IO_WriteB(crtc_base+1u,reg_50);
01692 
01693                 Bit8u reg_31, reg_3a;
01694                 switch (CurMode->type) {
01695                         case M_LIN15:
01696                         case M_LIN16:
01697                         case M_LIN24:
01698                         case M_LIN32:
01699                                 reg_3a=0x15;
01700                                 break;
01701                         case M_LIN8:
01702                                 // S3VBE20 does it this way. The other double pixel bit does not
01703                                 // seem to have an effect on the Trio64.
01704                                 if(CurMode->special&_S3_PIXEL_DOUBLE) reg_3a=0x5;
01705                                 else reg_3a=0x15;
01706                                 break;
01707                         default:
01708                                 reg_3a=5;
01709                                 break;
01710                 };
01711                 
01712                 switch (CurMode->type) {
01713                 case M_LIN4: // <- Theres a discrepance with real hardware on this
01714                 case M_LIN8:
01715                 case M_LIN15:
01716                 case M_LIN16:
01717                 case M_LIN24:
01718                 case M_LIN32:
01719                         reg_31 = 9;
01720                         break;
01721                 default:
01722                         reg_31 = 5;
01723                         break;
01724                 }
01725                 IO_Write(crtc_base,0x3a);IO_Write(crtc_base+1u,reg_3a);
01726                 IO_Write(crtc_base,0x31);IO_Write(crtc_base+1u,reg_31); //Enable banked memory and 256k+ access
01727 
01728                 IO_Write(crtc_base,0x58);
01729                 if (vga.mem.memsize >= (4*1024*1024))
01730                         IO_Write(crtc_base+1u,0x3);             // 4+ MB window
01731                 else if (vga.mem.memsize >= (2*1024*1024))
01732                         IO_Write(crtc_base+1u,0x2);             // 2 MB window
01733                 else
01734                         IO_Write(crtc_base+1u,0x1);             // 1 MB window
01735 
01736                 IO_Write(crtc_base,0x38);IO_Write(crtc_base+1u,0x48);   //Register lock 1
01737                 IO_Write(crtc_base,0x39);IO_Write(crtc_base+1u,0xa5);   //Register lock 2
01738         } else if (svga.set_video_mode) {
01739                 VGA_ModeExtraData modeData;
01740                 modeData.ver_overflow = ver_overflow;
01741                 modeData.hor_overflow = hor_overflow;
01742                 modeData.offset = offset;
01743                 modeData.modeNo = CurMode->mode;
01744                 modeData.htotal = CurMode->htotal;
01745                 modeData.vtotal = CurMode->vtotal;
01746                 svga.set_video_mode(crtc_base, &modeData);
01747         }
01748 
01749         FinishSetMode(clearmem);
01750 
01751         /* Set vga attrib register into defined state */
01752         IO_Read(mono_mode ? 0x3ba : 0x3da);
01753         IO_Write(0x3c0,0x20);
01754         IO_Read(mono_mode ? 0x3ba : 0x3da);
01755 
01756         /* Load text mode font */
01757         if (CurMode->type==M_TEXT) {
01758                 INT10_ReloadFont();
01759         }
01760         // Enable screen memory access
01761         IO_Write(0x3c4,1); IO_Write(0x3c5,seq_data[1] & ~0x20);
01762         //LOG_MSG("setmode end");
01763 
01764         if (en_int33) INT10_SetCurMode();
01765 
01766         return true;
01767 }
01768 
01769 Bitu VideoModeMemSize(Bitu mode) {
01770         if (!IS_VGA_ARCH)
01771                 return 0;
01772 
01773         VideoModeBlock* modelist = NULL;
01774 
01775         switch (svgaCard) {
01776         case SVGA_TsengET4K:
01777         case SVGA_TsengET3K:
01778                 modelist = ModeList_VGA_Tseng;
01779                 break;
01780         case SVGA_ParadisePVGA1A:
01781                 modelist = ModeList_VGA_Paradise;
01782                 break;
01783         default:
01784                 modelist = ModeList_VGA;
01785                 break;
01786         }
01787 
01788         VideoModeBlock* vmodeBlock = NULL;
01789         Bitu i=0;
01790         while (modelist[i].mode!=0xffff) {
01791                 if (modelist[i].mode==mode) {
01792                         /* Hack for VBE 1.2 modes and 24/32bpp ambiguity */
01793                         if (modelist[i].mode >= 0x100 && modelist[i].mode <= 0x11F &&
01794                 !(modelist[i].special & _USER_MODIFIED) &&
01795                                 ((modelist[i].type == M_LIN32 && !vesa12_modes_32bpp) ||
01796                                  (modelist[i].type == M_LIN24 && vesa12_modes_32bpp))) {
01797                                 /* ignore */
01798                         }
01799                         else {
01800                                 vmodeBlock = &modelist[i];
01801                                 break;
01802                         }
01803                 }
01804                 i++;
01805         }
01806 
01807         if (!vmodeBlock)
01808                 return ~0ul;
01809 
01810         switch(vmodeBlock->type) {
01811         case M_LIN4:
01812                 if (mode >= 0x100 && !allow_vesa_4bpp) return ~0ul;
01813                 return vmodeBlock->swidth*vmodeBlock->sheight/2;
01814         case M_LIN8:
01815                 if (mode >= 0x100 && !allow_vesa_8bpp) return ~0ul;
01816                 return vmodeBlock->swidth*vmodeBlock->sheight;
01817         case M_LIN15:
01818                 if (mode >= 0x100 && !allow_vesa_15bpp) return ~0ul;
01819                 return vmodeBlock->swidth*vmodeBlock->sheight*2;
01820         case M_LIN16:
01821                 if (mode >= 0x100 && !allow_vesa_16bpp) return ~0ul;
01822                 return vmodeBlock->swidth*vmodeBlock->sheight*2;
01823         case M_LIN24:
01824                 if (mode >= 0x100 && !allow_vesa_24bpp) return ~0ul;
01825                 return vmodeBlock->swidth*vmodeBlock->sheight*3;
01826         case M_LIN32:
01827                 if (mode >= 0x100 && !allow_vesa_32bpp) return ~0ul;
01828                 return vmodeBlock->swidth*vmodeBlock->sheight*4;
01829         case M_TEXT:
01830                 if (mode >= 0x100 && !allow_vesa_tty) return ~0ul;
01831                 return vmodeBlock->twidth*vmodeBlock->theight*2;
01832         default:
01833                 break;
01834         }
01835         // Return 0 for all other types, those always fit in memory
01836         return 0;
01837 }
01838 
01839 Bitu INT10_WriteVESAModeList(Bitu max_modes);
01840 
01841 /* ====================== VESAMOED.COM ====================== */
01842 class VESAMOED : public Program {
01843 public:
01844         void Run(void) {
01845         size_t array_i = 0;
01846         std::string arg,tmp;
01847                 bool got_opt=false;
01848         int mode = -1;
01849         int fmt = -1;
01850         int w = -1,h = -1;
01851         int ch = -1;
01852         int newmode = -1;
01853         signed char enable = -1;
01854         bool doDelete = false;
01855         bool modefind = false;
01856                 
01857         cmd->BeginOpt();
01858         while (cmd->GetOpt(/*&*/arg)) {
01859                         got_opt=true;
01860             if (arg == "?" || arg == "help") {
01861                 doHelp();
01862                 break;
01863             }
01864             else if (arg == "mode") {
01865                 cmd->NextOptArgv(/*&*/tmp);
01866 
01867                 if (tmp == "find") {
01868                     modefind = true;
01869                 }
01870                 else if (isdigit(tmp[0])) {
01871                     mode = strtoul(tmp.c_str(),NULL,0);
01872                 }
01873                 else {
01874                     WriteOut("Unknown mode '%s'\n",tmp.c_str());
01875                     return;
01876                 }
01877             }
01878             else if (arg == "fmt") {
01879                 cmd->NextOptArgv(/*&*/tmp);
01880 
01881                      if (tmp == "LIN4")
01882                     fmt = M_LIN4;
01883                 else if (tmp == "LIN8")
01884                     fmt = M_LIN8;
01885                 else if (tmp == "LIN15")
01886                     fmt = M_LIN15;
01887                 else if (tmp == "LIN16")
01888                     fmt = M_LIN16;
01889                 else if (tmp == "LIN24")
01890                     fmt = M_LIN24;
01891                 else if (tmp == "LIN32")
01892                     fmt = M_LIN32;
01893                 else if (tmp == "TEXT")
01894                     fmt = M_TEXT;
01895                 else {
01896                     WriteOut("Unknown format '%s'\n",tmp.c_str());
01897                     return;
01898                 }
01899             }
01900             else if (arg == "w") {
01901                 cmd->NextOptArgv(/*&*/tmp);
01902                 w = strtoul(tmp.c_str(),NULL,0);
01903             }
01904             else if (arg == "h") {
01905                 cmd->NextOptArgv(/*&*/tmp);
01906                 h = strtoul(tmp.c_str(),NULL,0);
01907             }
01908             else if (arg == "ch") {
01909                 cmd->NextOptArgv(/*&*/tmp);
01910                 ch = strtoul(tmp.c_str(),NULL,0);
01911             }
01912             else if (arg == "newmode") {
01913                 cmd->NextOptArgv(/*&*/tmp);
01914 
01915                 if (isdigit(tmp[0])) {
01916                     newmode = strtoul(tmp.c_str(),NULL,0);
01917                 }
01918                 else {
01919                     WriteOut("Unknown newmode '%s'\n",tmp.c_str());
01920                     return;
01921                 }
01922             }
01923             else if (arg == "delete") {
01924                 doDelete = true;
01925             }
01926             // NTS: If you're wondering why we support disabled modes (modes listed but cannot be set),
01927             //      there are plenty of scenarios on actual hardware where this occurs. Laptops, for
01928             //      example, have SVGA chipsets that can go up to 1600x1200, but the BIOS will disable
01929             //      anything above the native resolution of the laptop's LCD display unless an
01930             //      external monitor is attached at boot-up.
01931             else if (arg == "disable") {
01932                 enable = 0;
01933             }
01934             else if (arg == "enable") {
01935                 enable = 1;
01936             }
01937             else {
01938                 WriteOut("Unknown switch %s",arg.c_str());
01939                 return;
01940             }
01941         }
01942         cmd->EndOpt();
01943                 if(!got_opt) {
01944             doHelp();
01945             return;
01946         }
01947 
01948         if (modefind) {
01949             if (w < 0 && h < 0 && fmt < 0)
01950                 return;
01951 
01952             while (ModeList_VGA[array_i].mode != 0xFFFF) {
01953                 bool match = true;
01954 
01955                      if (w > 0 && (Bitu)w != ModeList_VGA[array_i].swidth)
01956                     match = false;
01957                 else if (h > 0 && (Bitu)h != ModeList_VGA[array_i].sheight)
01958                     match = false;
01959                 else if (fmt >= 0 && (Bitu)fmt != ModeList_VGA[array_i].type)
01960                     match = false;
01961                 else if (ModeList_VGA[array_i].type == M_ERROR)
01962                     match = false;
01963                 else if (ModeList_VGA[array_i].mode <= 0x13)
01964                     match = false;
01965 
01966                 if (!match)
01967                     array_i++;
01968                 else
01969                     break;
01970             }
01971         }
01972         else {
01973             while (ModeList_VGA[array_i].mode != 0xFFFF) {
01974                 if (ModeList_VGA[array_i].mode == (Bitu)mode)
01975                     break;
01976 
01977                 array_i++;
01978             }
01979         }
01980 
01981         if (ModeList_VGA[array_i].mode == 0xFFFF) {
01982             WriteOut("Mode not found\n");
01983             return;
01984         }
01985         else if (ModeList_VGA[array_i].mode <= 0x13) {
01986             WriteOut("Editing base VGA modes is not allowed\n");
01987             return;
01988         }
01989         else if (modefind) {
01990             WriteOut("Found mode 0x%x\n",(unsigned int)ModeList_VGA[array_i].mode);
01991         }
01992 
01993         if (enable == 0)
01994             ModeList_VGA[array_i].special |= _USER_DISABLED;
01995         else if (enable == 1)
01996             ModeList_VGA[array_i].special &= ~_USER_DISABLED;
01997 
01998         if (doDelete) {
01999             if (ModeList_VGA[array_i].type != M_ERROR)
02000                 WriteOut("Mode 0x%x deleted\n",ModeList_VGA[array_i].mode);
02001             else
02002                 WriteOut("Mode 0x%x already deleted\n",ModeList_VGA[array_i].mode);
02003 
02004             ModeList_VGA[array_i].type = M_ERROR;
02005             INT10_WriteVESAModeList(int10.rom.vesa_alloc_modes);
02006             return;
02007         }
02008 
02009         if (fmt < 0 && ModeList_VGA[array_i].type == M_ERROR) {
02010             WriteOut("Mode 0x%x is still deleted. Set a format with -fmt to un-delete\n",ModeList_VGA[array_i].mode);
02011             return;
02012         }
02013 
02014         if (!modefind && (w > 0 || h > 0 || fmt >= 0 || ch > 0)) {
02015             WriteOut("Changing mode 0x%x parameters\n",(unsigned int)ModeList_VGA[array_i].mode);
02016 
02017             ModeList_VGA[array_i].special |= _USER_MODIFIED;
02018 
02019             if (fmt >= 0) {
02020                 ModeList_VGA[array_i].type = (VGAModes)fmt;
02021                 /* will require reprogramming width in some cases! */
02022                 if (w < 0) w = ModeList_VGA[array_i].swidth;
02023             }
02024             if (w > 0) {
02025                 /* enforce alignment to avoid problems with modesetting code */
02026                 {
02027                     unsigned int aln = 8;
02028 
02029                     if (ModeList_VGA[array_i].type == M_LIN4)
02030                         aln = 16;
02031 
02032                     w += aln / 2;
02033                     w -= w % aln;
02034                     if (w == 0) w = aln;
02035                 }
02036 
02037                 ModeList_VGA[array_i].swidth = (Bitu)w;
02038                 if (ModeList_VGA[array_i].type == M_LIN15 || ModeList_VGA[array_i].type == M_LIN16) {
02039                     ModeList_VGA[array_i].hdispend = (Bitu)w / 4;
02040                     ModeList_VGA[array_i].htotal = ModeList_VGA[array_i].hdispend + 40;
02041                 }
02042                 else {
02043                     ModeList_VGA[array_i].hdispend = (Bitu)w / 8;
02044                     ModeList_VGA[array_i].htotal = ModeList_VGA[array_i].hdispend + 20;
02045                 }
02046             }
02047             if (h > 0) {
02048                 ModeList_VGA[array_i].sheight = (Bitu)h;
02049 
02050                 if (h >= 340)
02051                     ModeList_VGA[array_i].special &= ~_REPEAT1;
02052                 else
02053                     ModeList_VGA[array_i].special |= _REPEAT1;
02054 
02055                 if (ModeList_VGA[array_i].special & _REPEAT1)
02056                     ModeList_VGA[array_i].vdispend = (Bitu)h * 2;
02057                 else
02058                     ModeList_VGA[array_i].vdispend = (Bitu)h;
02059 
02060                 ModeList_VGA[array_i].vtotal = ModeList_VGA[array_i].vdispend + 49;
02061             }
02062             if (ch == 8 || ch == 14 || ch == 16)
02063                 ModeList_VGA[array_i].cheight = (Bitu)ch;
02064 
02065             ModeList_VGA[array_i].twidth = ModeList_VGA[array_i].swidth / ModeList_VGA[array_i].cwidth;
02066             ModeList_VGA[array_i].theight = ModeList_VGA[array_i].sheight / ModeList_VGA[array_i].cheight;
02067             INT10_WriteVESAModeList(int10.rom.vesa_alloc_modes);
02068         }
02069 
02070         if (newmode >= 0x40) {
02071             WriteOut("Mode 0x%x moved to mode 0x%x\n",(unsigned int)ModeList_VGA[array_i].mode,(unsigned int)newmode);
02072             ModeList_VGA[array_i].mode = (Bitu)newmode;
02073             INT10_WriteVESAModeList(int10.rom.vesa_alloc_modes);
02074         }
02075 
02076         /* if the new mode cannot fit in available memory, then mark as disabled */
02077         {
02078             unsigned int pitch = 0;
02079 
02080             switch (ModeList_VGA[array_i].type) {
02081                 case M_LIN4:
02082                     pitch = (ModeList_VGA[array_i].swidth / 8) * 4; /* not totally accurate but close enough */
02083                     break;
02084                 case M_LIN8:
02085                     pitch = ModeList_VGA[array_i].swidth;
02086                     break;
02087                 case M_LIN15:
02088                 case M_LIN16:
02089                     pitch = ModeList_VGA[array_i].swidth * 2;
02090                     break;
02091                 case M_LIN24:
02092                     pitch = ModeList_VGA[array_i].swidth * 3;
02093                     break;
02094                 case M_LIN32:
02095                     pitch = ModeList_VGA[array_i].swidth * 4;
02096                     break;
02097                 default:
02098                     break;
02099             }
02100 
02101             if ((pitch * ModeList_VGA[array_i].sheight) > vga.mem.memsize) {
02102                 /* NTS: Actually we don't mark as disabled, the VESA mode query function will
02103                  *      report as disabled automatically for the same check we do. This just
02104                  *      lets the user know. */
02105                 WriteOut("WARNING: Mode %u x %u as specified exceeds video memory, will be disabled\n",
02106                         ModeList_VGA[array_i].swidth,
02107                         ModeList_VGA[array_i].sheight);
02108             }
02109         }
02110     }
02111     void doHelp(void) {
02112         WriteOut("VESAMOED VESA BIOS mode editor utility\n");
02113         WriteOut("\n");
02114         WriteOut("NOTE: Due to architectual limitations of VBE emulation,\n");
02115         WriteOut("      Adding new modes is not allowed.\n");
02116         WriteOut("\n");
02117         WriteOut("  -mode <x>               VBE video mode to edit.\n");
02118         WriteOut("                            Specify video mode in decimal or hexadecimal,\n");
02119         WriteOut("                            or specify 'find' to match by fmt, width, height.\n");
02120         WriteOut("  -fmt <x>                Change pixel format, or mode to find.\n");
02121         WriteOut("                            LIN4, LIN8, LIN15, LIN16,\n");
02122         WriteOut("                            LIN24, LIN32, TEXT\n");
02123         WriteOut("  -w <x>                  Change width (in pixels), or mode to find.\n");
02124         WriteOut("  -h <x>                  Change height (in pixels), or mode to find.\n");
02125         WriteOut("  -ch <x>                 Change char height (in pixels), or mode to find.\n");
02126         WriteOut("  -newmode <x>            Change video mode number\n");
02127         WriteOut("  -delete                 Delete video mode\n");
02128         WriteOut("  -disable                Disable video mode (list but do not allow setting)\n");
02129         WriteOut("  -enable                 Enable video mode\n");
02130     }
02131 };
02132 
02133 void VESAMOED_ProgramStart(Program * * make) {
02134         *make=new VESAMOED;
02135 }
02136