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src/ints/int10_modes.cpp
00001 /*
00002  *  Copyright (C) 2002-2019  The DOSBox Team
00003  *
00004  *  This program is free software; you can redistribute it and/or modify
00005  *  it under the terms of the GNU General Public License as published by
00006  *  the Free Software Foundation; either version 2 of the License, or
00007  *  (at your option) any later version.
00008  *
00009  *  This program is distributed in the hope that it will be useful,
00010  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
00011  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
00012  *  GNU General Public License for more details.
00013  *
00014  *  You should have received a copy of the GNU General Public License
00015  *  along with this program; if not, write to the Free Software
00016  *  Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1335, USA.
00017  */
00018 
00019 
00020 #include <stdlib.h>
00021 #include <string.h>
00022 
00023 #include "dosbox.h"
00024 #include "mem.h"
00025 #include "inout.h"
00026 #include "int10.h"
00027 #include "vga.h"
00028 #include "bios.h"
00029 #include "programs.h"
00030 
00031 #define SEQ_REGS 0x05
00032 #define GFX_REGS 0x09
00033 #define ATT_REGS 0x15
00034 
00035 extern bool enable_vga_8bit_dac;
00036 extern bool int10_vesa_map_as_128kb;
00037 extern bool allow_vesa_lowres_modes;
00038 extern bool allow_vesa_4bpp_packed;
00039 extern bool vesa12_modes_32bpp;
00040 extern bool allow_vesa_32bpp;
00041 extern bool allow_vesa_24bpp;
00042 extern bool allow_vesa_16bpp;
00043 extern bool allow_vesa_15bpp;
00044 extern bool allow_vesa_8bpp;
00045 extern bool allow_vesa_4bpp;
00046 extern bool allow_vesa_tty;
00047 extern bool vga_8bit_dac;
00048 
00049 VideoModeBlock ModeList_VGA[]={
00050 /* mode  ,type     ,sw  ,sh  ,tw ,th ,cw,ch ,pt,pstart  ,plength,htot,vtot,hde,vde special flags */
00051 { 0x000  ,M_TEXT   ,360 ,400 ,40 ,25 ,9 ,16 ,8 ,0xB8000 ,0x0800 ,50  ,449 ,40 ,400 ,_EGA_HALF_CLOCK     },
00052 { 0x001  ,M_TEXT   ,360 ,400 ,40 ,25 ,9 ,16 ,8 ,0xB8000 ,0x0800 ,50  ,449 ,40 ,400 ,_EGA_HALF_CLOCK     },
00053 { 0x002  ,M_TEXT   ,720 ,400 ,80 ,25 ,9 ,16 ,8 ,0xB8000 ,0x1000 ,100 ,449 ,80 ,400 ,0   },
00054 { 0x003  ,M_TEXT   ,720 ,400 ,80 ,25 ,9 ,16 ,8 ,0xB8000 ,0x1000 ,100 ,449 ,80 ,400 ,0   },
00055 { 0x004  ,M_CGA4   ,320 ,200 ,40 ,25 ,8 ,8  ,1 ,0xB8000 ,0x4000 ,50  ,449 ,40 ,400 ,_EGA_HALF_CLOCK     | _DOUBLESCAN | _REPEAT1},
00056 { 0x005  ,M_CGA4   ,320 ,200 ,40 ,25 ,8 ,8  ,1 ,0xB8000 ,0x4000 ,50  ,449 ,40 ,400 ,_EGA_HALF_CLOCK     | _DOUBLESCAN | _REPEAT1},
00057 { 0x006  ,M_CGA2   ,640 ,200 ,80 ,25 ,8 ,8  ,1 ,0xB8000 ,0x4000 ,100 ,449 ,80 ,400 ,_DOUBLESCAN | _REPEAT1},
00058 { 0x007  ,M_TEXT   ,720 ,400 ,80 ,25 ,9 ,16 ,8 ,0xB0000 ,0x1000 ,100 ,449 ,80 ,400 ,0   },
00059 
00060 { 0x00D  ,M_EGA    ,320 ,200 ,40 ,25 ,8 ,8  ,8 ,0xA0000 ,0x2000 ,50  ,449 ,40 ,400 ,_EGA_HALF_CLOCK     | _DOUBLESCAN   },
00061 { 0x00E  ,M_EGA    ,640 ,200 ,80 ,25 ,8 ,8  ,4 ,0xA0000 ,0x4000 ,100 ,449 ,80 ,400 ,_DOUBLESCAN },
00062 { 0x00F  ,M_EGA    ,640 ,350 ,80 ,25 ,8 ,14 ,2 ,0xA0000 ,0x8000 ,100 ,449 ,80 ,350 ,0   },/*was EGA_2*/
00063 { 0x010  ,M_EGA    ,640 ,350 ,80 ,25 ,8 ,14 ,2 ,0xA0000 ,0x8000 ,100 ,449 ,80 ,350 ,0   },
00064 { 0x011  ,M_EGA    ,640 ,480 ,80 ,30 ,8 ,16 ,1 ,0xA0000 ,0xA000 ,100 ,525 ,80 ,480 ,0   },/*was EGA_2 */
00065 { 0x012  ,M_EGA    ,640 ,480 ,80 ,30 ,8 ,16 ,1 ,0xA0000 ,0xA000 ,100 ,525 ,80 ,480 ,0   },
00066 { 0x013  ,M_VGA    ,320 ,200 ,40 ,25 ,8 ,8  ,1 ,0xA0000 ,0x2000 ,100 ,449 ,80 ,400 ,_REPEAT1   },
00067 
00068 { 0x054  ,M_TEXT   ,1056,344, 132,43, 8,  8, 1 ,0xB8000 ,0x4000, 160, 449, 132,344, 0   },
00069 { 0x055  ,M_TEXT   ,1056,400, 132,25, 8, 16, 1 ,0xB8000 ,0x2000, 160, 449, 132,400, 0   },
00070 
00071 /* Alias of mode 101 */
00072 { 0x069  ,M_LIN8   ,640 ,480 ,80 ,30 ,8 ,16 ,1 ,0xA0000 ,0x10000,100 ,525 ,80 ,480 ,0   },
00073 /* Alias of mode 102 */
00074 { 0x06A  ,M_LIN4   ,800 ,600 ,100,37 ,8 ,16 ,1 ,0xA0000 ,0x10000,128 ,663 ,100,600 ,0   },
00075 
00076 /* Follow vesa 1.2 for first 0x20 */
00077 { 0x100  ,M_LIN8   ,640 ,400 ,80 ,25 ,8 ,16 ,1 ,0xA0000 ,0x10000,100 ,449 ,80 ,400 ,0   },
00078 { 0x101  ,M_LIN8   ,640 ,480 ,80 ,30 ,8 ,16 ,1 ,0xA0000 ,0x10000,100 ,525 ,80 ,480 , _VGA_PIXEL_DOUBLE },
00079 { 0x102  ,M_LIN4   ,800 ,600 ,100,37 ,8 ,16 ,1 ,0xA0000 ,0x10000,132 ,628 ,100,600 ,0   },
00080 { 0x103  ,M_LIN8   ,800 ,600 ,100,37 ,8 ,16 ,1 ,0xA0000 ,0x10000,132 ,628 ,100,600 ,0   },
00081 { 0x104  ,M_LIN4   ,1024,768 ,128,48 ,8 ,16 ,1 ,0xA0000 ,0x10000,168 ,806 ,128,768 ,0   },
00082 { 0x105  ,M_LIN8   ,1024,768 ,128,48 ,8 ,16 ,1 ,0xA0000 ,0x10000,168 ,806 ,128,768 ,0   },
00083 { 0x106  ,M_LIN4   ,1280,1024,160,64 ,8 ,16 ,1 ,0xA0000 ,0x10000,212 ,1066,160,1024,0   },
00084 { 0x107  ,M_LIN8   ,1280,1024,160,64 ,8 ,16 ,1 ,0xA0000 ,0x10000,212 ,1066,160,1024,0   },
00085 
00086 /* VESA text modes */ 
00087 { 0x108  ,M_TEXT   ,640 ,480,  80,60, 8,  8 ,2 ,0xB8000 ,0x4000, 100 ,525 ,80 ,480 ,0   },
00088 { 0x109  ,M_TEXT   ,1056,400, 132,25, 8, 16, 1 ,0xB8000 ,0x2000, 160, 449, 132,400, 0   },
00089 { 0x10A  ,M_TEXT   ,1056,688, 132,43, 8, 16, 1 ,0xB8000 ,0x4000, 160, 806, 132,688, 0   },
00090 { 0x10B  ,M_TEXT   ,1056,400, 132,50, 8,  8, 1 ,0xB8000 ,0x4000, 160, 449, 132,400, 0   },
00091 { 0x10C  ,M_TEXT   ,1056,480, 132,60, 8,  8, 2 ,0xB8000 ,0x4000, 160, 531, 132,480, 0   },
00092 
00093 /* VESA higher color modes.
00094  * Note v1.2 of the VESA BIOS extensions explicitly states modes 0x10F, 0x112, 0x115, 0x118 are 8:8:8 (24-bit) not 8:8:8:8 (32-bit).
00095  * This also fixes COMA "Parhaat" 1997 demo, by offering a true 24bpp mode so that it doesn't try to draw 24bpp on a 32bpp VESA linear framebuffer.
00096  * NTS: The 24bpp modes listed here will not be available to the DOS game/demo if the user says that the VBE 1.2 modes are 32bpp,
00097  *      instead the redefinitions in the next block will apply to allow M_LIN32. To use the 24bpp modes here, you must set 'vesa vbe 1.2 modes are 32bpp=false' */
00098 { 0x10D  ,M_LIN15  ,320 ,200 ,40 ,25 ,8 ,8  ,1 ,0xA0000 ,0x10000,100 ,449 ,80 ,400 , _REPEAT1 },
00099 { 0x10E  ,M_LIN16  ,320 ,200 ,40 ,25 ,8 ,8  ,1 ,0xA0000 ,0x10000,100 ,449 ,80 ,400 , _REPEAT1 },
00100 { 0x10F  ,M_LIN24  ,320 ,200 ,40 ,25 ,8 ,8  ,1 ,0xA0000 ,0x10000,50  ,449 ,40 ,400 , _REPEAT1 },
00101 { 0x110  ,M_LIN15  ,640 ,480 ,80 ,30 ,8 ,16 ,1 ,0xA0000 ,0x10000,200 ,525 ,160,480 ,0   },
00102 { 0x111  ,M_LIN16  ,640 ,480 ,80 ,30 ,8 ,16 ,1 ,0xA0000 ,0x10000,200 ,525 ,160,480 ,0   },
00103 { 0x112  ,M_LIN24  ,640 ,480 ,80 ,30 ,8 ,16 ,1 ,0xA0000 ,0x10000,100 ,525 ,80 ,480 ,0   },
00104 { 0x113  ,M_LIN15  ,800 ,600 ,100,37 ,8 ,16 ,1 ,0xA0000 ,0x10000,264 ,628 ,200,600 ,0   },
00105 { 0x114  ,M_LIN16  ,800 ,600 ,100,37 ,8 ,16 ,1 ,0xA0000 ,0x10000,264 ,628 ,200,600 ,0   },
00106 { 0x115  ,M_LIN24  ,800 ,600 ,100,37 ,8 ,16 ,1 ,0xA0000 ,0x10000,132 ,628 ,100,600 ,0   },
00107 { 0x116  ,M_LIN15  ,1024,768 ,128,48 ,8 ,16 ,1 ,0xA0000 ,0x10000,336 ,806 ,256,768 ,0   },
00108 { 0x117  ,M_LIN16  ,1024,768 ,128,48 ,8 ,16 ,1 ,0xA0000 ,0x10000,336 ,806 ,256,768 ,0   },
00109 { 0x118  ,M_LIN24  ,1024,768 ,128,48 ,8 ,16 ,1 ,0xA0000 ,0x10000,168 ,806 ,128,768 ,0   },
00110 
00111 /* But of course... there are other demos that assume mode 0x10F is 32bpp!
00112  * So we have another definition of those modes that overlaps some of the same mode numbers above.
00113  * This allows "Phenomena" demo to use 32bpp 320x200 mode if you set 'vesa vbe 1.2 modes are 32bpp=true'.
00114  * The code will allow either this block's mode 0x10F (LIN32), or the previous block's mode 0x10F (LIN24), but not both. */
00115 { 0x10F  ,M_LIN32  ,320 ,200 ,40 ,25 ,8 ,8  ,1 ,0xA0000 ,0x10000,50  ,449 ,40 ,400 , _REPEAT1 },
00116 { 0x112  ,M_LIN32  ,640 ,480 ,80 ,30 ,8 ,16 ,1 ,0xA0000 ,0x10000,100 ,525 ,80 ,480 ,0   },
00117 { 0x115  ,M_LIN32  ,800 ,600 ,100,37 ,8 ,16 ,1 ,0xA0000 ,0x10000,132 ,628 ,100,600 ,0   },
00118 { 0x118  ,M_LIN32  ,1024,768 ,128,48 ,8 ,16 ,1 ,0xA0000 ,0x10000,168 ,806 ,128,768 ,0   },
00119 
00120 /* RGBX 8:8:8:8 modes. These were once the M_LIN32 modes DOSBox mapped to 0x10F-0x11B prior to implementing M_LIN24. */
00121 { 0x210  ,M_LIN32  ,320 ,200 ,40 ,25 ,8 ,8  ,1 ,0xA0000 ,0x10000,50  ,449 ,40 ,400 , _REPEAT1 },
00122 { 0x211  ,M_LIN32  ,640 ,480 ,80 ,30 ,8 ,16 ,1 ,0xA0000 ,0x10000,100 ,525 ,80 ,480 ,0   },
00123 { 0x212  ,M_LIN32  ,800 ,600 ,100,37 ,8 ,16 ,1 ,0xA0000 ,0x10000,132 ,628 ,100,600 ,0   },
00124 { 0x214  ,M_LIN32  ,1024,768 ,128,48 ,8 ,16 ,1 ,0xA0000 ,0x10000,168 ,806 ,128,768 ,0   },
00125 
00126 { 0x215  ,M_LIN24  ,320 ,200 ,40 ,25 ,8 ,8  ,1 ,0xA0000 ,0x10000,50  ,449 ,40 ,400 , _REPEAT1 },
00127 { 0x216  ,M_LIN24  ,640 ,480 ,80 ,30 ,8 ,16 ,1 ,0xA0000 ,0x10000,100 ,525 ,80 ,480 ,0   },
00128 { 0x217  ,M_LIN24  ,800 ,600 ,100,37 ,8 ,16 ,1 ,0xA0000 ,0x10000,132 ,628 ,100,600 ,0   },
00129 { 0x218  ,M_LIN24  ,1024,768 ,128,48 ,8 ,16 ,1 ,0xA0000 ,0x10000,168 ,806 ,128,768 ,0   },
00130 
00131 /* those should be interlaced but ok */
00132 { 0x119  ,M_LIN15  ,1280,1024,160,64 ,8 ,16 ,1 ,0xA0000 ,0x10000,424 ,1066,320,1024,0   },
00133 { 0x11A  ,M_LIN16  ,1280,1024,160,64 ,8 ,16 ,1 ,0xA0000 ,0x10000,424 ,1066,320,1024,0   },
00134 
00135 { 0x11C  ,M_LIN8   ,640 ,350 ,80 ,25 ,8 ,14 ,2 ,0xA0000 ,0x10000,100 ,449 ,80 ,350 ,0   },
00136 // special mode for Birth demo by Incognita
00137 { 0x11D  ,M_LIN15  ,640 ,350 ,80 ,25 ,8 ,14 ,1 ,0xA0000 ,0x10000,200 ,449 ,160,350 ,0   },
00138 { 0x11F  ,M_LIN16  ,640 ,350 ,80 ,25 ,8 ,14 ,1 ,0xA0000 ,0x10000,200 ,449 ,160,350 ,0   },
00139 { 0x120  ,M_LIN8   ,1600,1200,200,75 ,8 ,16 ,1 ,0xA0000 ,0x10000,264 ,1240,200,1200,0   },
00140 { 0x142  ,M_LIN32  ,640 ,350 ,80 ,25 ,8 ,14 ,2 ,0xA0000 ,0x10000 ,100 ,449 ,80 ,350 ,0  },
00141 
00142 // FIXME: Find an old S3 Trio and dump the VESA modelist, then arrange this modelist to match
00143 { 0x150  ,M_LIN8   ,320 ,480 ,40 ,60 ,8 ,8  ,1 ,0xA0000 ,0x10000,100 ,525 ,80 ,480 , _S3_PIXEL_DOUBLE  },
00144 { 0x151  ,M_LIN8   ,320 ,240 ,40 ,30 ,8 ,8  ,1 ,0xA0000 ,0x10000,100 ,525 ,80 ,480 , _S3_PIXEL_DOUBLE | _REPEAT1 },
00145 { 0x152  ,M_LIN8   ,320 ,400 ,40 ,50 ,8 ,8  ,1 ,0xA0000 ,0x10000,100 ,449 ,80 ,400 , _S3_PIXEL_DOUBLE  },
00146 // For S3 Trio emulation this mode must exist as mode 0x153 else RealTech "Countdown" will crash
00147 // if you select VGA 320x200 with S3 acceleration.
00148 { 0x153  ,M_LIN8   ,320 ,200 ,40 ,25 ,8 ,8  ,1 ,0xA0000 ,0x10000,100 ,449 ,80 ,400 , _S3_PIXEL_DOUBLE | _REPEAT1 },
00149 
00150 { 0x15C ,M_LIN8,    512 ,384 ,64 ,48 ,8, 8  ,1 ,0xA0000 ,0x10000,168 ,806 ,128,768 , _S3_PIXEL_DOUBLE | _DOUBLESCAN },
00151 { 0x159 ,M_LIN8,    400 ,300 ,50 ,37 ,8 ,8  ,1 ,0xA0000 ,0x10000,132 ,628 ,100,600 , _S3_PIXEL_DOUBLE | _DOUBLESCAN },
00152 { 0x15D ,M_LIN16,   512 ,384 ,64 ,48 ,8, 16 ,1 ,0xA0000 ,0x10000,168 ,806 ,128,768 , _S3_PIXEL_DOUBLE | _DOUBLESCAN },
00153 { 0x15A ,M_LIN16,   400 ,300 ,50 ,37 ,8 ,16 ,1 ,0xA0000 ,0x10000,132 ,628 ,100,600 , _S3_PIXEL_DOUBLE | _DOUBLESCAN },
00154 
00155 { 0x160  ,M_LIN15  ,320 ,240 ,40 ,30 ,8 ,8  ,1 ,0xA0000 ,0x10000,100 ,525 , 80 ,480 , _REPEAT1 },
00156 { 0x161  ,M_LIN15  ,320 ,400 ,40 ,50 ,8 ,8  ,1 ,0xA0000 ,0x10000,100 ,449 , 80 ,400 ,0 },
00157 { 0x162  ,M_LIN15  ,320 ,480 ,40 ,60 ,8 ,8  ,1 ,0xA0000 ,0x10000,100 ,525 , 80 ,480 ,0 },
00158 { 0x165  ,M_LIN15  ,640 ,400 ,80 ,25 ,8 ,16 ,1 ,0xA0000 ,0x10000,200 ,449 ,160 ,400 ,0   },
00159 
00160 // hack: 320x200x16bpp for "Process" demo (1997) with apparently hard-coded VBE mode
00161 { 0x136  ,M_LIN16  ,320 ,240 ,40 ,30 ,8 ,8  ,1 ,0xA0000 ,0x10000,100 ,525 , 80 ,480 , _REPEAT1 },
00162 
00163 // hack: 320x480x256-color alias for Habitual demo. doing this removes the need to run S3VBE20.EXE before running the demo.
00164 //       the reason it has to be this particular video mode is because HABITUAL.EXE does not query modes, it simply assumes
00165 //       that mode 0x166 is this particular mode and errors out if it can't set it.
00166 { 0x166  ,M_LIN8   ,320 ,480 ,40 ,60 ,8 ,8  ,1 ,0xA0000 ,0x10000,100 ,525 ,80 ,480 , _S3_PIXEL_DOUBLE  },
00167 
00168 { 0x170  ,M_LIN16  ,320 ,240 ,40 ,30 ,8 ,8  ,1 ,0xA0000 ,0x10000,100 ,525 , 80 ,480 , _REPEAT1 },
00169 { 0x171  ,M_LIN16  ,320 ,400 ,40 ,50 ,8 ,8  ,1 ,0xA0000 ,0x10000,100 ,449 , 80 ,400 ,0 },
00170 { 0x172  ,M_LIN16  ,320 ,480 ,40 ,60 ,8 ,8  ,1 ,0xA0000 ,0x10000,100 ,525 , 80 ,480 ,0 },
00171 { 0x175  ,M_LIN16  ,640 ,400 ,80 ,25 ,8 ,16 ,1 ,0xA0000 ,0x10000,200 ,449 ,160 ,400 ,0   },
00172 
00173 { 0x190  ,M_LIN32  ,320 ,240 ,40 ,30 ,8 ,8  ,1 ,0xA0000 ,0x10000, 50 ,525 ,40 ,480 , _REPEAT1 },
00174 { 0x191  ,M_LIN32  ,320 ,400 ,40 ,50 ,8 ,8  ,1 ,0xA0000 ,0x10000, 50 ,449 ,40 ,400 ,0 },
00175 { 0x192  ,M_LIN32  ,320 ,480 ,40 ,60 ,8 ,8  ,1 ,0xA0000 ,0x10000, 50 ,525 ,40 ,480 ,0 },
00176 
00177 // S3 specific modes (OEM modes). See also [http://www.ctyme.com/intr/rb-0275.htm]
00178 { 0x201  ,M_LIN8    ,640 ,480, 80,30 ,8 ,16 ,1 ,0xA0000 ,0x10000,100 ,525 ,80 ,480 , _VGA_PIXEL_DOUBLE },
00179 { 0x202  ,M_LIN4    ,800 ,600,100,37 ,8 ,16 ,1 ,0xA0000 ,0x10000,132 ,628 ,100,600 ,0   },
00180 { 0x203  ,M_LIN8    ,800 ,600,100,37 ,8 ,16 ,1 ,0xA0000 ,0x10000,132 ,628 ,100,600 ,0   }, // Line Wars II, S3 accelerated 800x600
00181 { 0x204  ,M_LIN4    ,1024,768,128,48 ,8 ,16 ,1 ,0xA0000 ,0x10000,168 ,806 ,128,768 ,0   },
00182 { 0x205  ,M_LIN8    ,1024,768,128,48 ,8 ,16 ,1 ,0xA0000 ,0x10000,168 ,806 ,128,768 ,0   },
00183 { 0x206  ,M_LIN4    ,1280,960,160,64 ,8 ,16 ,1 ,0xA0000 ,0x10000,212 ,1024,160,960 ,0   }, // TODO VERIFY THIS
00184 { 0x207  ,M_LIN8        ,1152,864,160,64 ,8 ,16 ,1 ,0xA0000 ,0x10000,182 ,948 ,144,864 ,0       },
00185 { 0x208  ,M_LIN4    ,1280,1024,160,64 ,8 ,16 ,1 ,0xA0000 ,0x10000,212 ,1066,160,1024,0  },
00186 { 0x209  ,M_LIN15       ,1152,864,160,64 ,8 ,16 ,1 ,0xA0000 ,0x10000,364 ,948 ,288,864 ,0       },
00187 { 0x20A  ,M_LIN16       ,1152,864,160,64 ,8 ,16 ,1 ,0xA0000 ,0x10000,364 ,948 ,288,864 ,0       },
00188 { 0x20B  ,M_LIN32       ,1152,864,160,64 ,8 ,16 ,1 ,0xA0000 ,0x10000,182 ,948 ,144,864 ,0       },
00189 { 0x213  ,M_LIN32   ,640 ,400,80 ,25 ,8 ,16 ,1 ,0xA0000 ,0x10000,100 ,449 ,80 ,400 ,0   },
00190 
00191 // Some custom modes
00192 
00193 // 720x480 3:2 modes
00194 { 0x21B  ,M_LIN4   ,720 ,480 ,90 ,30 ,8 ,16 ,1 ,0xA0000 ,0x10000,132 ,525 ,90  ,480 ,0  },
00195 { 0x21C  ,M_LIN8   ,720 ,480 ,90 ,30 ,8 ,16 ,1 ,0xA0000 ,0x10000,132 ,525 ,90  ,480 ,0  },
00196 { 0x21D  ,M_LIN15  ,720 ,480 ,90 ,30 ,8 ,16 ,1 ,0xA0000 ,0x10000,264 ,525 ,180 ,480 ,0  },
00197 { 0x21E  ,M_LIN16  ,720 ,480 ,90 ,30 ,8 ,16 ,1 ,0xA0000 ,0x10000,264 ,525 ,180 ,480 ,0  },
00198 { 0x21F  ,M_LIN32  ,720 ,480 ,90 ,30 ,8 ,16 ,1 ,0xA0000 ,0x10000,132 ,525 ,90  ,480 ,0  },
00199 
00200 // 848x480 16:9 modes
00201 { 0x220  ,M_LIN4   ,848 ,480 ,106,30 ,8 ,16 ,1 ,0xA0000 ,0x10000,132 ,525 ,106 ,480 ,0  },
00202 { 0x221  ,M_LIN8   ,848 ,480 ,106,30 ,8 ,16 ,1 ,0xA0000 ,0x10000,132 ,525 ,106 ,480 ,0  },
00203 { 0x222  ,M_LIN15  ,848 ,480 ,106,30 ,8 ,16 ,1 ,0xA0000 ,0x10000,264 ,525 ,212 ,480 ,0  },
00204 { 0x223  ,M_LIN16  ,848 ,480 ,106,30 ,8 ,16 ,1 ,0xA0000 ,0x10000,264 ,525 ,212 ,480 ,0  },
00205 { 0x224  ,M_LIN32  ,848 ,480 ,106,30 ,8 ,16 ,1 ,0xA0000 ,0x10000,132 ,525 ,106 ,480 ,0  },
00206 
00207 // 1280x800 8:5 modes
00208 { 0x225  ,M_LIN4   ,1280,800 ,160,50 ,8 ,16 ,1 ,0xA0000 ,0x10000,200 ,880 ,160 ,800 ,0  },
00209 { 0x226  ,M_LIN8   ,1280,800 ,160,50 ,8 ,16 ,1 ,0xA0000 ,0x10000,200 ,880 ,160 ,800 ,0  },
00210 { 0x227  ,M_LIN15  ,1280,800 ,160,50 ,8 ,16 ,1 ,0xA0000 ,0x10000,400 ,880 ,320 ,800 ,0  },
00211 { 0x228  ,M_LIN16  ,1280,800 ,160,50 ,8 ,16 ,1 ,0xA0000 ,0x10000,400 ,880 ,320 ,800 ,0  },
00212 { 0x229  ,M_LIN32  ,1280,800 ,160,50 ,8 ,16 ,1 ,0xA0000 ,0x10000,200 ,880 ,160 ,800 ,0  },
00213 { 0x300  ,M_LIN24  ,1280,800 ,160,50 ,8 ,16 ,1 ,0xA0000 ,0x10000,200 ,880 ,160 ,800 ,0  },
00214 
00215 // 1280x960 4:3 modes
00216 { 0x22a  ,M_LIN4   ,1280,960 ,160,60 ,8 ,16 ,1 ,0xA0000 ,0x10000,200 ,1020,160 ,960 ,0  },
00217 { 0x22b  ,M_LIN8   ,1280,960 ,160,60 ,8 ,16 ,1 ,0xA0000 ,0x10000,200 ,1020,160 ,960 ,0  },
00218 { 0x22c  ,M_LIN15  ,1280,960 ,160,60 ,8 ,16 ,1 ,0xA0000 ,0x10000,400 ,1020,320 ,960 ,0  },
00219 { 0x22d  ,M_LIN16  ,1280,960 ,160,60 ,8 ,16 ,1 ,0xA0000 ,0x10000,400 ,1020,320 ,960 ,0  },
00220 { 0x22e  ,M_LIN32  ,1280,960 ,160,60 ,8 ,16 ,1 ,0xA0000 ,0x10000,200 ,1020,160 ,960 ,0  },
00221 { 0x301  ,M_LIN24  ,1280,960 ,160,60 ,8 ,16 ,1 ,0xA0000 ,0x10000,200 ,1020,160 ,960 ,0  },
00222 
00223 // 1280x1024 5:4 rest
00224 { 0x22f  ,M_LIN32  ,1280,1024,160,64 ,8 ,16 ,1 ,0xA0000 ,0x10000,212 ,1066,160,1024,0   },
00225 { 0x302  ,M_LIN24  ,1280,1024,160,64 ,8 ,16 ,1 ,0xA0000 ,0x10000,212 ,1066,160,1024,0   },
00226 
00227 // 1400x1050 4:3 - 4bpp requires a hdisplayend value that is even, so round up
00228 { 0x250  ,M_LIN4   ,1400,1050,175,66 ,8 ,16 ,1 ,0xA0000 ,0x10000,220 ,1100,176 ,1050,0  },
00229 { 0x230  ,M_LIN8   ,1400,1050,175,66 ,8 ,16 ,1 ,0xA0000 ,0x10000,220 ,1100,175 ,1050,0  },
00230 { 0x231  ,M_LIN15  ,1400,1050,175,66 ,8 ,16 ,1 ,0xA0000 ,0x10000,440 ,1100,350 ,1050,0  },
00231 { 0x232  ,M_LIN16  ,1400,1050,175,66 ,8 ,16 ,1 ,0xA0000 ,0x10000,440 ,1100,350 ,1050,0  },
00232 { 0x233  ,M_LIN32  ,1400,1050,175,66 ,8 ,16 ,1 ,0xA0000 ,0x10000,220 ,1100,175 ,1050,0  },
00233 { 0x303  ,M_LIN24  ,1400,1050,175,66 ,8 ,16 ,1 ,0xA0000 ,0x10000,220 ,1100,175 ,1050,0  },
00234 
00235 // 1440x900 8:5 modes
00236 { 0x234  ,M_LIN4   ,1440, 900,180,56 ,8 ,16 ,1 ,0xA0000 ,0x10000,220 , 980,180 , 900,0  },
00237 { 0x235  ,M_LIN8   ,1440, 900,180,56 ,8 ,16 ,1 ,0xA0000 ,0x10000,220 , 980,180 , 900,0  },
00238 { 0x236  ,M_LIN15  ,1440, 900,180,56 ,8 ,16 ,1 ,0xA0000 ,0x10000,440 , 980,360 , 900,0  },
00239 { 0x237  ,M_LIN16  ,1440, 900,180,56 ,8 ,16 ,1 ,0xA0000 ,0x10000,440 , 980,360 , 900,0  },
00240 { 0x238  ,M_LIN32  ,1440, 900,180,56 ,8 ,16 ,1 ,0xA0000 ,0x10000,220 , 980,180 , 900,0  },
00241 
00242 // 1600x1200 4:3 rest - 32bpp needs more than 4 megs
00243 { 0x239  ,M_LIN4   ,1600,1200,200,75 ,8 ,16 ,1 ,0xA0000 ,0x10000,264 ,1240,200, 1200,0  },
00244 { 0x23a  ,M_LIN15  ,1600,1200,200,75 ,8 ,16 ,1 ,0xA0000 ,0x10000,500 ,1240,400 ,1200,0  },
00245 { 0x23b  ,M_LIN16  ,1600,1200,200,75 ,8 ,16 ,1 ,0xA0000 ,0x10000,500 ,1240,400 ,1200,0  },
00246 { 0x23c  ,M_LIN32  ,1600,1200,200,75 ,8 ,16 ,1 ,0xA0000 ,0x10000,264 ,1240,200 ,1200,0  },
00247 
00248 // 1280x720 16:9 modes
00249 { 0x23D  ,M_LIN4   ,1280,720 ,160,45 ,8 ,16 ,1 ,0xA0000 ,0x10000,176 ,792 ,160 ,720 ,0  },
00250 { 0x23E  ,M_LIN8   ,1280,720 ,160,45 ,8 ,16 ,1 ,0xA0000 ,0x10000,176 ,792 ,160 ,720 ,0  },
00251 { 0x23F  ,M_LIN15  ,1280,720 ,160,45 ,8 ,16 ,1 ,0xA0000 ,0x10000,352 ,792 ,320 ,720 ,0  },
00252 { 0x240  ,M_LIN16  ,1280,720 ,160,45 ,8 ,16 ,1 ,0xA0000 ,0x10000,352 ,792 ,320 ,720 ,0  },
00253 { 0x241  ,M_LIN32  ,1280,720 ,160,45 ,8 ,16 ,1 ,0xA0000 ,0x10000,176 ,792 ,160 ,720 ,0  },
00254 { 0x303  ,M_LIN24  ,1280,720 ,160,45 ,8 ,16 ,1 ,0xA0000 ,0x10000,176 ,792 ,160 ,720 ,0  },
00255 
00256 // 1920x1080 16:9 modes
00257 { 0x242  ,M_LIN4   ,1920,1080,240,67 ,8 ,16 ,1 ,0xA0000 ,0x10000,264 ,1188,240 ,1080,0  },
00258 { 0x243  ,M_LIN8   ,1920,1080,240,67 ,8 ,16 ,1 ,0xA0000 ,0x10000,264 ,1188,240 ,1080,0  },
00259 { 0x244  ,M_LIN15  ,1920,1080,240,67 ,8 ,16 ,1 ,0xA0000 ,0x10000,528 ,1188,480 ,1080,0  },
00260 { 0x245  ,M_LIN16  ,1920,1080,240,67 ,8 ,16 ,1 ,0xA0000 ,0x10000,528 ,1188,480 ,1080,0  },
00261 { 0x246  ,M_LIN32  ,1920,1080,240,67 ,8 ,16 ,1 ,0xA0000 ,0x10000,264 ,1188,240 ,1080,0  },
00262 { 0x304  ,M_LIN24  ,1920,1080,240,67 ,8 ,16 ,1 ,0xA0000 ,0x10000,264 ,1188,240 ,1080,0  },
00263 
00264 // 960x720 4:3 modes
00265 { 0x247  ,M_LIN4   ,960,720 ,160,45 ,8 ,16 ,1 ,0xA0000 ,0x10000,144 ,792 ,120 ,720 ,0   },
00266 { 0x248  ,M_LIN8   ,960,720 ,160,45 ,8 ,16 ,1 ,0xA0000 ,0x10000,144 ,792 ,120 ,720 ,0   },
00267 { 0x249  ,M_LIN15  ,960,720 ,160,45 ,8 ,16 ,1 ,0xA0000 ,0x10000,288 ,792 ,240 ,720 ,0  },
00268 { 0x24A  ,M_LIN16  ,960,720 ,160,45 ,8 ,16 ,1 ,0xA0000 ,0x10000,288 ,792 ,240 ,720 ,0  },
00269 { 0x24B  ,M_LIN32  ,960,720 ,160,45 ,8 ,16 ,1 ,0xA0000 ,0x10000,144 ,792 ,120 ,720 ,0  },
00270 
00271 // 1440x1080 16:9 modes
00272 { 0x24C  ,M_LIN4   ,1440,1080,240,67 ,8 ,16 ,1 ,0xA0000 ,0x10000,200 ,1188,180 ,1080,0  },
00273 { 0x24D  ,M_LIN8   ,1440,1080,240,67 ,8 ,16 ,1 ,0xA0000 ,0x10000,200 ,1188,180 ,1080,0  },
00274 { 0x24E  ,M_LIN15  ,1440,1080,240,67 ,8 ,16 ,1 ,0xA0000 ,0x10000,400 ,1188,360 ,1080,0  },
00275 { 0x24F  ,M_LIN16  ,1440,1080,240,67 ,8 ,16 ,1 ,0xA0000 ,0x10000,400 ,1188,360 ,1080,0  },
00276 { 0x2F0  ,M_LIN32  ,1440,1080,240,67 ,8 ,16 ,1 ,0xA0000 ,0x10000,200 ,1188,180 ,1080,0  },
00277 
00278 // packed 16-color (4bpp) modes seen on a Toshiba Libretto VESA BIOS (Chips & Technologies 65550)
00279 { 0x25F  ,M_PACKED4,320 ,200 ,40 ,25 ,8 ,8  ,1 ,0xA0000 ,0x10000,50  ,449 ,40  ,400 , _REPEAT1 },
00280 { 0x260  ,M_PACKED4,640 ,400 ,80 ,25 ,8 ,16 ,1 ,0xA0000 ,0x10000,100 ,449 ,80  ,400 ,0  },
00281 { 0x261  ,M_PACKED4,640 ,480 ,80 ,30 ,8 ,16 ,1 ,0xA0000 ,0x10000,100 ,525 ,80  ,480 ,0  },
00282 { 0x262  ,M_PACKED4,720 ,480 ,90 ,30 ,8 ,16 ,1 ,0xA0000 ,0x10000,132 ,525 ,90  ,480 ,0  },
00283 { 0x263  ,M_PACKED4,800 ,600 ,100,37 ,8 ,16 ,1 ,0xA0000 ,0x10000,128 ,663 ,100 ,600 ,0  },
00284 { 0x264  ,M_PACKED4,848 ,480 ,106,30 ,8 ,16 ,1 ,0xA0000 ,0x10000,132 ,525 ,106 ,480 ,0  },
00285 { 0x265  ,M_PACKED4,1024,768 ,128,48 ,8 ,16 ,1 ,0xA0000 ,0x10000,168 ,806 ,128 ,768 ,0  },
00286 { 0x266  ,M_PACKED4,1280,720 ,160,45 ,8 ,16 ,1 ,0xA0000 ,0x10000,176 ,792 ,160 ,720 ,0  },
00287 { 0x267  ,M_PACKED4,1280,1024,160,64 ,8 ,16 ,1 ,0xA0000 ,0x10000,212 ,1066,160 ,1024,0  },
00288 { 0x268  ,M_PACKED4,1440,900 ,180,56 ,8 ,16 ,1 ,0xA0000 ,0x10000,220 ,980 ,180 ,900 ,0  },
00289 { 0x269  ,M_PACKED4,1400,1050,175,66 ,8 ,16 ,1 ,0xA0000 ,0x10000,220 ,1100,176 ,1050,0  },
00290 { 0x26A  ,M_PACKED4,1600,1200,200,75 ,8 ,16 ,1 ,0xA0000 ,0x10000,264 ,1240,200 ,1200,0  },
00291 { 0x26B  ,M_PACKED4,1920,1080,240,67 ,8 ,16 ,1 ,0xA0000 ,0x10000,264 ,1188,240 ,1080,0  },
00292 
00293 {0xFFFF  ,M_ERROR  ,0   ,0   ,0  ,0  ,0 ,0  ,0 ,0x00000 ,0x0000 ,0   ,0   ,0  ,0   ,0   },
00294 };
00295 
00296 VideoModeBlock ModeList_VGA_Text_200lines[]={
00297 /* mode  ,type     ,sw  ,sh  ,tw ,th ,cw,ch ,pt,pstart  ,plength,htot,vtot,hde,vde special flags */
00298 { 0x000  ,M_TEXT   ,320 ,200 ,40 ,25 ,8 , 8 ,8 ,0xB8000 ,0x0800 ,50  ,449 ,40 ,400 ,_EGA_HALF_CLOCK | _DOUBLESCAN},
00299 { 0x001  ,M_TEXT   ,320 ,200 ,40 ,25 ,8 , 8 ,8 ,0xB8000 ,0x0800 ,50  ,449 ,40 ,400 ,_EGA_HALF_CLOCK | _DOUBLESCAN},
00300 { 0x002  ,M_TEXT   ,640 ,200 ,80 ,25 ,8 , 8 ,8 ,0xB8000 ,0x1000 ,100 ,449 ,80 ,400 ,_DOUBLESCAN },
00301 { 0x003  ,M_TEXT   ,640 ,200 ,80 ,25 ,8 , 8 ,8 ,0xB8000 ,0x1000 ,100 ,449 ,80 ,400 ,_DOUBLESCAN }
00302 };
00303 
00304 VideoModeBlock ModeList_VGA_Text_350lines[]={
00305 /* mode  ,type     ,sw  ,sh  ,tw ,th ,cw,ch ,pt,pstart  ,plength,htot,vtot,hde,vde special flags */
00306 { 0x000  ,M_TEXT   ,320 ,350 ,40 ,25 ,8 ,14 ,8 ,0xB8000 ,0x0800 ,50  ,449 ,40 ,350 ,_EGA_HALF_CLOCK     },
00307 { 0x001  ,M_TEXT   ,320 ,350 ,40 ,25 ,8 ,14 ,8 ,0xB8000 ,0x0800 ,50  ,449 ,40 ,350 ,_EGA_HALF_CLOCK     },
00308 { 0x002  ,M_TEXT   ,640 ,350 ,80 ,25 ,8 ,14 ,8 ,0xB8000 ,0x1000 ,100 ,449 ,80 ,350 ,0   },
00309 { 0x003  ,M_TEXT   ,640 ,350 ,80 ,25 ,8 ,14 ,8 ,0xB8000 ,0x1000 ,100 ,449 ,80 ,350 ,0   },
00310 { 0x007  ,M_TEXT   ,720 ,350 ,80 ,25 ,9 ,14 ,8 ,0xB0000 ,0x1000 ,100 ,449 ,80 ,350 ,0   }
00311 };
00312 
00313 VideoModeBlock ModeList_VGA_Tseng[]={
00314 /* mode  ,type     ,sw  ,sh  ,tw ,th ,cw,ch ,pt,pstart  ,plength,htot,vtot,hde,vde special flags */
00315 { 0x000  ,M_TEXT   ,360 ,400 ,40 ,25 ,9 ,16 ,8 ,0xB8000 ,0x0800 ,50  ,449 ,40 ,400 ,_EGA_HALF_CLOCK     },
00316 { 0x001  ,M_TEXT   ,360 ,400 ,40 ,25 ,9 ,16 ,8 ,0xB8000 ,0x0800 ,50  ,449 ,40 ,400 ,_EGA_HALF_CLOCK     },
00317 { 0x002  ,M_TEXT   ,720 ,400 ,80 ,25 ,9 ,16 ,8 ,0xB8000 ,0x1000 ,100 ,449 ,80 ,400 ,0   },
00318 { 0x003  ,M_TEXT   ,720 ,400 ,80 ,25 ,9 ,16 ,8 ,0xB8000 ,0x1000 ,100 ,449 ,80 ,400 ,0   },
00319 { 0x004  ,M_CGA4   ,320 ,200 ,40 ,25 ,8 ,8  ,1 ,0xB8000 ,0x4000 ,50  ,449 ,40 ,400 ,_EGA_HALF_CLOCK     | _DOUBLESCAN | _REPEAT1},
00320 { 0x005  ,M_CGA4   ,320 ,200 ,40 ,25 ,8 ,8  ,1 ,0xB8000 ,0x4000 ,50  ,449 ,40 ,400 ,_EGA_HALF_CLOCK     | _DOUBLESCAN | _REPEAT1},
00321 { 0x006  ,M_CGA2   ,640 ,200 ,80 ,25 ,8 ,8  ,1 ,0xB8000 ,0x4000 ,100 ,449 ,80 ,400 ,_DOUBLESCAN | _REPEAT1},
00322 { 0x007  ,M_TEXT   ,720 ,400 ,80 ,25 ,9 ,16 ,8 ,0xB0000 ,0x1000 ,100 ,449 ,80 ,400 ,0   },
00323 
00324 { 0x00D  ,M_EGA    ,320 ,200 ,40 ,25 ,8 ,8  ,8 ,0xA0000 ,0x2000 ,50  ,449 ,40 ,400 ,_EGA_HALF_CLOCK     | _DOUBLESCAN   },
00325 { 0x00E  ,M_EGA    ,640 ,200 ,80 ,25 ,8 ,8  ,4 ,0xA0000 ,0x4000 ,100 ,449 ,80 ,400 ,_DOUBLESCAN },
00326 { 0x00F  ,M_EGA    ,640 ,350 ,80 ,25 ,8 ,14 ,2 ,0xA0000 ,0x8000 ,100 ,449 ,80 ,350 ,0   },
00327 { 0x010  ,M_EGA    ,640 ,350 ,80 ,25 ,8 ,14 ,2 ,0xA0000 ,0x8000 ,100 ,449 ,80 ,350 ,0   },
00328 { 0x011  ,M_EGA    ,640 ,480 ,80 ,30 ,8 ,16 ,1 ,0xA0000 ,0xA000 ,100 ,525 ,80 ,480 ,0   },
00329 { 0x012  ,M_EGA    ,640 ,480 ,80 ,30 ,8 ,16 ,1 ,0xA0000 ,0xA000 ,100 ,525 ,80 ,480 ,0   },
00330 { 0x013  ,M_VGA    ,320 ,200 ,40 ,25 ,8 ,8  ,1 ,0xA0000 ,0x2000 ,100 ,449 ,80 ,400 ,_REPEAT1   },
00331 
00332 { 0x018  ,M_TEXT   ,1056 ,688, 132,44, 8, 8, 1 ,0xB0000 ,0x4000, 192, 800, 132, 704, 0 },
00333 { 0x019  ,M_TEXT   ,1056 ,400, 132,25, 8, 16,1 ,0xB0000 ,0x2000, 192, 449, 132, 400, 0 },
00334 { 0x01A  ,M_TEXT   ,1056 ,400, 132,28, 8, 16,1 ,0xB0000 ,0x2000, 192, 449, 132, 448, 0 },
00335 { 0x022  ,M_TEXT   ,1056 ,688, 132,44, 8, 8, 1 ,0xB8000 ,0x4000, 192, 800, 132, 704, 0 },
00336 { 0x023  ,M_TEXT   ,1056 ,400, 132,25, 8, 16,1 ,0xB8000 ,0x2000, 192, 449, 132, 400, 0 },
00337 { 0x024  ,M_TEXT   ,1056 ,400, 132,28, 8, 16,1 ,0xB8000 ,0x2000, 192, 449, 132, 448, 0 },
00338 { 0x025  ,M_LIN4   ,640 ,480 ,80 ,30 ,8 ,16 ,1 ,0xA0000 ,0xA000 ,100 ,525 ,80 ,480 , 0 },
00339 { 0x029  ,M_LIN4   ,800 ,600 ,100,37 ,8 ,16 ,1 ,0xA0000 ,0xA000, 128 ,663 ,100,600 , 0 },
00340 { 0x02D  ,M_LIN8   ,640 ,350 ,80 ,21 ,8 ,16 ,1 ,0xA0000 ,0x10000,100 ,449 ,80 ,350 , 0 },
00341 { 0x02E  ,M_LIN8   ,640 ,480 ,80 ,30 ,8 ,16 ,1 ,0xA0000 ,0x10000,100 ,525 ,80 ,480 , 0 },
00342 { 0x02F  ,M_LIN8   ,640 ,400 ,80 ,25 ,8 ,16 ,1 ,0xA0000 ,0x10000,100 ,449 ,80 ,400 , 0 },/* ET4000 only */
00343 { 0x030  ,M_LIN8   ,800 ,600 ,100,37 ,8 ,16 ,1 ,0xA0000 ,0x10000,128 ,663 ,100,600 , 0 },
00344 { 0x036  ,M_LIN4   ,960 , 720,120,45 ,8 ,16 ,1 ,0xA0000 ,0xA000, 120 ,800 ,120,720 , 0 },/* STB only */
00345 { 0x037  ,M_LIN4   ,1024, 768,128,48 ,8 ,16 ,1 ,0xA0000 ,0xA000, 128 ,800 ,128,768 , 0 },
00346 { 0x038  ,M_LIN8   ,1024 ,768,128,48 ,8 ,16 ,1 ,0xA0000 ,0x10000,168 ,800 ,128,768 , 0 },/* ET4000 only */
00347 { 0x03D  ,M_LIN4   ,1280,1024,160,64 ,8 ,16 ,1 ,0xA0000 ,0xA000, 160 ,1152,160,1024, 0 },/* newer ET4000 */
00348 { 0x03E  ,M_LIN4   ,1280, 960,160,60 ,8 ,16 ,1 ,0xA0000 ,0xA000, 160 ,1024,160,960 , 0 },/* Definicon only */ 
00349 { 0x06A  ,M_LIN4   ,800 ,600 ,100,37 ,8 ,16 ,1 ,0xA0000 ,0xA000, 128 ,663 ,100,600 , 0 },/* newer ET4000 */
00350 
00351 // Sierra SC1148x Hi-Color DAC modes
00352 { 0x213  ,M_LIN15  ,320 ,200 ,40 ,25 ,8 ,8  ,1 ,0xA0000 ,0x10000,100 ,449 ,80 ,400 , _VGA_PIXEL_DOUBLE | _REPEAT1 },
00353 { 0x22D  ,M_LIN15  ,640 ,350 ,80 ,25 ,8 ,14 ,1 ,0xA0000 ,0x10000,200 ,449 ,160,350 , 0 },
00354 { 0x22E  ,M_LIN15  ,640 ,480 ,80 ,30 ,8 ,16 ,1 ,0xA0000 ,0x10000,200 ,525 ,160,480 , 0 },
00355 { 0x22F  ,M_LIN15  ,640 ,400 ,80 ,25 ,8 ,16 ,1 ,0xA0000 ,0x10000,200 ,449 ,160,400 , 0 },
00356 { 0x230  ,M_LIN15  ,800 ,600 ,100,37 ,8 ,16 ,1 ,0xA0000 ,0x10000,264 ,628 ,200,600 , 0 },
00357 
00358 {0xFFFF  ,M_ERROR  ,0   ,0   ,0  ,0  ,0 ,0  ,0 ,0x00000 ,0x0000 ,0   ,0   ,0  ,0   ,0   },
00359 };
00360 
00361 VideoModeBlock ModeList_VGA_Paradise[]={
00362 /* mode  ,type     ,sw  ,sh  ,tw ,th ,cw,ch ,pt,pstart  ,plength,htot,vtot,hde,vde special flags */
00363 { 0x000  ,M_TEXT   ,360 ,400 ,40 ,25 ,9 ,16 ,8 ,0xB8000 ,0x0800 ,50  ,449 ,40 ,400 ,_EGA_HALF_CLOCK     },
00364 { 0x001  ,M_TEXT   ,360 ,400 ,40 ,25 ,9 ,16 ,8 ,0xB8000 ,0x0800 ,50  ,449 ,40 ,400 ,_EGA_HALF_CLOCK     },
00365 { 0x002  ,M_TEXT   ,720 ,400 ,80 ,25 ,9 ,16 ,8 ,0xB8000 ,0x1000 ,100 ,449 ,80 ,400 ,0   },
00366 { 0x003  ,M_TEXT   ,720 ,400 ,80 ,25 ,9 ,16 ,8 ,0xB8000 ,0x1000 ,100 ,449 ,80 ,400 ,0   },
00367 { 0x004  ,M_CGA4   ,320 ,200 ,40 ,25 ,8 ,8  ,1 ,0xB8000 ,0x4000 ,50  ,449 ,40 ,400 ,_EGA_HALF_CLOCK     | _DOUBLESCAN | _REPEAT1},
00368 { 0x005  ,M_CGA4   ,320 ,200 ,40 ,25 ,8 ,8  ,1 ,0xB8000 ,0x4000 ,50  ,449 ,40 ,400 ,_EGA_HALF_CLOCK     | _DOUBLESCAN | _REPEAT1},
00369 { 0x006  ,M_CGA2   ,640 ,200 ,80 ,25 ,8 ,8  ,1 ,0xB8000 ,0x4000 ,100 ,449 ,80 ,400 ,_DOUBLESCAN | _REPEAT1},
00370 { 0x007  ,M_TEXT   ,720 ,400 ,80 ,25 ,9 ,16 ,8 ,0xB0000 ,0x1000 ,100 ,449 ,80 ,400 ,0   },
00371 
00372 { 0x00D  ,M_EGA    ,320 ,200 ,40 ,25 ,8 ,8  ,8 ,0xA0000 ,0x2000 ,50  ,449 ,40 ,400 ,_EGA_HALF_CLOCK     | _DOUBLESCAN   },
00373 { 0x00E  ,M_EGA    ,640 ,200 ,80 ,25 ,8 ,8  ,4 ,0xA0000 ,0x4000 ,100 ,449 ,80 ,400 ,_DOUBLESCAN },
00374 { 0x00F  ,M_EGA    ,640 ,350 ,80 ,25 ,8 ,14 ,2 ,0xA0000 ,0x8000 ,100 ,449 ,80 ,350 ,0   },
00375 { 0x010  ,M_EGA    ,640 ,350 ,80 ,25 ,8 ,14 ,2 ,0xA0000 ,0x8000 ,100 ,449 ,80 ,350 ,0   },
00376 { 0x011  ,M_EGA    ,640 ,480 ,80 ,30 ,8 ,16 ,1 ,0xA0000 ,0xA000 ,100 ,525 ,80 ,480 ,0   },
00377 { 0x012  ,M_EGA    ,640 ,480 ,80 ,30 ,8 ,16 ,1 ,0xA0000 ,0xA000 ,100 ,525 ,80 ,480 ,0   },
00378 { 0x013  ,M_VGA    ,320 ,200 ,40 ,25 ,8 ,8  ,1 ,0xA0000 ,0x2000 ,100 ,449 ,80 ,400 ,_REPEAT1 },
00379 
00380 { 0x054  ,M_TEXT   ,1056 ,688, 132,43, 8, 9, 1, 0xB0000, 0x4000, 192, 720, 132,688, 0 },
00381 { 0x055  ,M_TEXT   ,1056 ,400, 132,25, 8, 16,1, 0xB0000, 0x2000, 192, 449, 132,400, 0 },
00382 { 0x056  ,M_TEXT   ,1056 ,688, 132,43, 8, 9, 1, 0xB0000, 0x4000, 192, 720, 132,688, 0 },
00383 { 0x057  ,M_TEXT   ,1056 ,400, 132,25, 8, 16,1, 0xB0000, 0x2000, 192, 449, 132,400, 0 },
00384 { 0x058  ,M_LIN4   ,800 , 600, 100,37, 8, 16,1, 0xA0000, 0xA000, 128 ,663 ,100,600, 0 },
00385 { 0x05C  ,M_LIN8   ,800 , 600 ,100,37 ,8 ,16,1 ,0xA0000 ,0x10000,128 ,663 ,100,600, 0 },
00386 { 0x05D  ,M_LIN4   ,1024, 768, 128,48 ,8, 16,1, 0xA0000, 0x10000,128 ,800 ,128,768 ,0 }, // documented only on C00 upwards
00387 { 0x05E  ,M_LIN8   ,640 , 400, 80 ,25, 8, 16,1, 0xA0000, 0x10000,100 ,449 ,80 ,400, 0 },
00388 { 0x05F  ,M_LIN8   ,640 , 480, 80 ,30, 8, 16,1, 0xA0000, 0x10000,100 ,525 ,80 ,480, 0 },
00389 
00390 {0xFFFF  ,M_ERROR  ,0   ,0   ,0  ,0  ,0 ,0  ,0 ,0x00000 ,0x0000 ,0   ,0   ,0  ,0   ,0   },
00391 };
00392 
00393 /* NTS: I will *NOT* set the double scanline flag for 200 line modes.
00394  *      The modes listed here are intended to reflect the actual raster sent to the EGA monitor,
00395  *      not what you think looks better. EGA as far as I know, is either sent a 200-line mode,
00396  *      or a 350-line mode. There is no VGA-line 200 to 400 line doubling. */
00397 VideoModeBlock ModeList_EGA[]={
00398 /* mode  ,type     ,sw  ,sh  ,tw ,th ,cw,ch ,pt,pstart  ,plength,htot,vtot,hde,vde special flags */
00399 { 0x000  ,M_TEXT   ,320 ,350 ,40 ,25 ,8 ,14 ,8 ,0xB8000 ,0x0800 ,50  ,366 ,40 ,350 ,_EGA_HALF_CLOCK     },
00400 { 0x001  ,M_TEXT   ,320 ,350 ,40 ,25 ,8 ,14 ,8 ,0xB8000 ,0x0800 ,50  ,366 ,40 ,350 ,_EGA_HALF_CLOCK     },
00401 { 0x002  ,M_TEXT   ,640 ,350 ,80 ,25 ,8 ,14 ,8 ,0xB8000 ,0x1000 ,96  ,366 ,80 ,350 ,0   },
00402 { 0x003  ,M_TEXT   ,640 ,350 ,80 ,25 ,8 ,14 ,8 ,0xB8000 ,0x1000 ,96  ,366 ,80 ,350 ,0   },
00403 { 0x004  ,M_CGA4   ,320 ,200 ,40 ,25 ,8 ,8  ,1 ,0xB8000 ,0x4000 ,60  ,262 ,40 ,200 ,_EGA_HALF_CLOCK     | _REPEAT1},
00404 { 0x005  ,M_CGA4   ,320 ,200 ,40 ,25 ,8 ,8  ,1 ,0xB8000 ,0x4000 ,60  ,262 ,40 ,200 ,_EGA_HALF_CLOCK     | _REPEAT1},
00405 { 0x006  ,M_CGA2   ,640 ,200 ,80 ,25 ,8 ,8  ,1 ,0xB8000 ,0x4000 ,117 ,262 ,80 ,200 ,_REPEAT1},
00406 { 0x007  ,M_TEXT   ,720 ,350 ,80 ,25 ,9 ,14 ,8 ,0xB0000 ,0x1000 ,101 ,370 ,80 ,350 ,0   },
00407 
00408 { 0x00D  ,M_EGA    ,320 ,200 ,40 ,25 ,8 ,8  ,8 ,0xA0000 ,0x2000 ,60  ,262 ,40 ,200 ,_EGA_HALF_CLOCK     },
00409 { 0x00E  ,M_EGA    ,640 ,200 ,80 ,25 ,8 ,8  ,4 ,0xA0000 ,0x4000 ,117 ,262 ,80 ,200 ,0 },
00410 { 0x00F  ,M_EGA    ,640 ,350 ,80 ,25 ,8 ,14 ,2 ,0xA0000 ,0x8000 ,101 ,370 ,80 ,350 ,0   },
00411 { 0x010  ,M_EGA    ,640 ,350 ,80 ,25 ,8 ,14 ,2 ,0xA0000 ,0x8000 ,96  ,366 ,80 ,350 ,0   },
00412 
00413 {0xFFFF  ,M_ERROR  ,0   ,0   ,0  ,0  ,0 ,0  ,0 ,0x00000 ,0x0000 ,0   ,0   ,0  ,0   ,0   },
00414 };
00415 
00416 VideoModeBlock ModeList_OTHER[]={
00417 /* mode  ,type     ,sw  ,sh  ,tw ,th ,cw,ch ,pt,pstart  ,plength,htot,vtot,hde,vde ,special flags */
00418 { 0x000  ,M_TEXT   ,320 ,400 ,40 ,25 ,8 ,8  ,8 ,0xB8000 ,0x0800 ,56  ,31  ,40 ,25  ,0   },
00419 { 0x001  ,M_TEXT   ,320 ,400 ,40 ,25 ,8 ,8  ,8 ,0xB8000 ,0x0800 ,56  ,31  ,40 ,25  ,0   },
00420 { 0x002  ,M_TEXT   ,640 ,400 ,80 ,25 ,8 ,8  ,4 ,0xB8000 ,0x1000 ,113 ,31  ,80 ,25  ,0   },
00421 { 0x003  ,M_TEXT   ,640 ,400 ,80 ,25 ,8 ,8  ,4 ,0xB8000 ,0x1000 ,113 ,31  ,80 ,25  ,0   },
00422 { 0x004  ,M_CGA4   ,320 ,200 ,40 ,25 ,8 ,8  ,1 ,0xB8000 ,0x4000 ,56  ,127 ,40 ,100 ,0   },
00423 { 0x005  ,M_CGA4   ,320 ,200 ,40 ,25 ,8 ,8  ,1 ,0xB8000 ,0x4000 ,56  ,127 ,40 ,100 ,0   },
00424 { 0x006  ,M_CGA2   ,640 ,200 ,80 ,25 ,8 ,8  ,1 ,0xB8000 ,0x4000 ,56  ,127 ,40 ,100 ,0   },
00425 { 0x008  ,M_TANDY16,160 ,200 ,20 ,25 ,8 ,8  ,8 ,0xB8000 ,0x2000 ,56  ,127 ,40 ,100 ,0   },
00426 { 0x009  ,M_TANDY16,320 ,200 ,40 ,25 ,8 ,8  ,8 ,0xB8000 ,0x2000 ,113 ,63  ,80 ,50  ,0   },
00427 { 0x00A  ,M_CGA4   ,640 ,200 ,80 ,25 ,8 ,8  ,8 ,0xB8000 ,0x2000 ,113 ,63  ,80 ,50  ,0   },
00428 //{ 0x00E  ,M_TANDY16,640 ,200 ,80 ,25 ,8 ,8  ,8 ,0xA0000 ,0x10000 ,113 ,256 ,80 ,200 ,0   },
00429 {0xFFFF  ,M_ERROR  ,0   ,0   ,0  ,0  ,0 ,0  ,0 ,0x00000 ,0x0000 ,0   ,0   ,0  ,0   ,0   },
00430 };
00431 
00432 /* MCGA mode list.
00433  * These are based off of a register capture of actual MCGA hardware for each mode.
00434  * According to register captures, all modes seem to be consistently programmed as if
00435  * for 40x25 CGA modes, including 80x25 modes.
00436  *
00437  * These modes should generally make a 70Hz VGA compatible output, except 640x480 2-color MCGA
00438  * mode, which should make a 60Hz VGA compatible mode.
00439  *
00440  * Register values are CGA-like, meaning that the modes are defined in character clocks
00441  * horizontally and character cells vertically and the actual scan line numbers are determined
00442  * by the vertical param times max scanline.
00443  *
00444  * According to the register dump I made, vertical total values don't fully make sense and
00445  * may be nonsensical and handled differently for emulation purposes. They're weird.
00446  *
00447  * When I can figure out which ones are directly handled, doubled, or just ignored, I can
00448  * update this table and the emulation to match it.
00449  *
00450  * Until then, this is close enough. */
00451 VideoModeBlock ModeList_MCGA[]={
00452 /* mode  ,type     ,sw  ,sh  ,tw ,th ,cw,ch ,pt,pstart  ,plength,htot,vtot,hde,vde ,special flags */
00453 { 0x000  ,M_TEXT   ,320 ,400 ,40 ,25 ,8 ,16 ,8 ,0xB8000 ,0x0800 ,49  ,26  ,40 ,25  ,0   },
00454 { 0x001  ,M_TEXT   ,320 ,400 ,40 ,25 ,8 ,16 ,8 ,0xB8000 ,0x0800 ,49  ,26  ,40 ,25  ,0   },
00455 { 0x002  ,M_TEXT   ,640 ,400 ,80 ,25 ,8 ,16 ,8 ,0xB8000 ,0x1000 ,49  ,26  ,40 ,25  ,0   },
00456 { 0x003  ,M_TEXT   ,640 ,400 ,80 ,25 ,8 ,16 ,8 ,0xB8000 ,0x1000 ,49  ,26  ,40 ,25  ,0   },
00457 { 0x004  ,M_CGA4   ,320 ,200 ,40 ,25 ,8 ,8  ,1 ,0xB8000 ,0x4000 ,49  ,108 ,40 ,100 ,0   },
00458 { 0x005  ,M_CGA4   ,320 ,200 ,40 ,25 ,8 ,8  ,1 ,0xB8000 ,0x4000 ,49  ,108 ,40 ,100 ,0   },
00459 { 0x006  ,M_CGA2   ,640 ,200 ,80 ,25 ,8 ,8  ,1 ,0xB8000 ,0x4000 ,49  ,108 ,40 ,100 ,0   },
00460 { 0x011  ,M_CGA2   ,640 ,480 ,80 ,30 ,8 ,16 ,1 ,0xA0000 ,0xA000 ,49  ,127 ,40 ,120 ,0   }, // note 1
00461 { 0x013  ,M_VGA    ,320 ,200 ,40 ,25 ,8 ,8  ,1 ,0xA0000 ,0x2000 ,49  ,108 ,40 ,100 ,0   }, // note 1
00462 {0xFFFF  ,M_ERROR  ,0   ,0   ,0  ,0  ,0 ,0  ,0 ,0x00000 ,0x0000 ,0   ,0   ,0  ,0   ,0   },
00463 };
00464 // note 1: CGA-like 200-line vertical timing is programmed into the registers, and then the
00465 //         hardware doubles them again. The max scanline row is zero in these modes, so
00466 //         doubling twice is the only way it could work.
00467 
00468 VideoModeBlock Hercules_Mode=
00469 { 0x007  ,M_TEXT   ,640 ,350 ,80 ,25 ,8 ,14 ,1 ,0xB0000 ,0x1000 ,97 ,25  ,80 ,25  ,0    };
00470 
00471 VideoModeBlock PC98_Mode=
00472 { 0x000  ,M_PC98   ,640 ,400 ,80 ,25 ,8 ,14 ,1 ,0xA0000 ,0x1000 ,97 ,25  ,80 ,25  ,0    };
00473 
00474 static Bit8u text_palette[64][3]=
00475 {
00476   {0x00,0x00,0x00},{0x00,0x00,0x2a},{0x00,0x2a,0x00},{0x00,0x2a,0x2a},{0x2a,0x00,0x00},{0x2a,0x00,0x2a},{0x2a,0x2a,0x00},{0x2a,0x2a,0x2a},
00477   {0x00,0x00,0x15},{0x00,0x00,0x3f},{0x00,0x2a,0x15},{0x00,0x2a,0x3f},{0x2a,0x00,0x15},{0x2a,0x00,0x3f},{0x2a,0x2a,0x15},{0x2a,0x2a,0x3f},
00478   {0x00,0x15,0x00},{0x00,0x15,0x2a},{0x00,0x3f,0x00},{0x00,0x3f,0x2a},{0x2a,0x15,0x00},{0x2a,0x15,0x2a},{0x2a,0x3f,0x00},{0x2a,0x3f,0x2a},
00479   {0x00,0x15,0x15},{0x00,0x15,0x3f},{0x00,0x3f,0x15},{0x00,0x3f,0x3f},{0x2a,0x15,0x15},{0x2a,0x15,0x3f},{0x2a,0x3f,0x15},{0x2a,0x3f,0x3f},
00480   {0x15,0x00,0x00},{0x15,0x00,0x2a},{0x15,0x2a,0x00},{0x15,0x2a,0x2a},{0x3f,0x00,0x00},{0x3f,0x00,0x2a},{0x3f,0x2a,0x00},{0x3f,0x2a,0x2a},
00481   {0x15,0x00,0x15},{0x15,0x00,0x3f},{0x15,0x2a,0x15},{0x15,0x2a,0x3f},{0x3f,0x00,0x15},{0x3f,0x00,0x3f},{0x3f,0x2a,0x15},{0x3f,0x2a,0x3f},
00482   {0x15,0x15,0x00},{0x15,0x15,0x2a},{0x15,0x3f,0x00},{0x15,0x3f,0x2a},{0x3f,0x15,0x00},{0x3f,0x15,0x2a},{0x3f,0x3f,0x00},{0x3f,0x3f,0x2a},
00483   {0x15,0x15,0x15},{0x15,0x15,0x3f},{0x15,0x3f,0x15},{0x15,0x3f,0x3f},{0x3f,0x15,0x15},{0x3f,0x15,0x3f},{0x3f,0x3f,0x15},{0x3f,0x3f,0x3f}
00484 };
00485 
00486 static Bit8u mtext_palette[64][3]=
00487 {
00488   {0x00,0x00,0x00},{0x00,0x00,0x00},{0x00,0x00,0x00},{0x00,0x00,0x00},{0x00,0x00,0x00},{0x00,0x00,0x00},{0x00,0x00,0x00},{0x00,0x00,0x00},
00489   {0x2a,0x2a,0x2a},{0x2a,0x2a,0x2a},{0x2a,0x2a,0x2a},{0x2a,0x2a,0x2a},{0x2a,0x2a,0x2a},{0x2a,0x2a,0x2a},{0x2a,0x2a,0x2a},{0x2a,0x2a,0x2a},
00490   {0x00,0x00,0x00},{0x00,0x00,0x00},{0x00,0x00,0x00},{0x00,0x00,0x00},{0x00,0x00,0x00},{0x00,0x00,0x00},{0x00,0x00,0x00},{0x00,0x00,0x00},
00491   {0x3f,0x3f,0x3f},{0x3f,0x3f,0x3f},{0x3f,0x3f,0x3f},{0x3f,0x3f,0x3f},{0x3f,0x3f,0x3f},{0x3f,0x3f,0x3f},{0x3f,0x3f,0x3f},{0x3f,0x3f,0x3f},
00492   {0x00,0x00,0x00},{0x00,0x00,0x00},{0x00,0x00,0x00},{0x00,0x00,0x00},{0x00,0x00,0x00},{0x00,0x00,0x00},{0x00,0x00,0x00},{0x00,0x00,0x00},
00493   {0x2a,0x2a,0x2a},{0x2a,0x2a,0x2a},{0x2a,0x2a,0x2a},{0x2a,0x2a,0x2a},{0x2a,0x2a,0x2a},{0x2a,0x2a,0x2a},{0x2a,0x2a,0x2a},{0x2a,0x2a,0x2a},
00494   {0x00,0x00,0x00},{0x00,0x00,0x00},{0x00,0x00,0x00},{0x00,0x00,0x00},{0x00,0x00,0x00},{0x00,0x00,0x00},{0x00,0x00,0x00},{0x00,0x00,0x00},
00495   {0x3f,0x3f,0x3f},{0x3f,0x3f,0x3f},{0x3f,0x3f,0x3f},{0x3f,0x3f,0x3f},{0x3f,0x3f,0x3f},{0x3f,0x3f,0x3f},{0x3f,0x3f,0x3f},{0x3f,0x3f,0x3f} 
00496 };
00497 
00498 static Bit8u mtext_s3_palette[64][3]=
00499 {
00500   {0x00,0x00,0x00},{0x00,0x00,0x00},{0x00,0x00,0x00},{0x00,0x00,0x00},{0x00,0x00,0x00},{0x00,0x00,0x00},{0x00,0x00,0x00},{0x00,0x00,0x00},
00501   {0x2a,0x2a,0x2a},{0x2a,0x2a,0x2a},{0x2a,0x2a,0x2a},{0x2a,0x2a,0x2a},{0x2a,0x2a,0x2a},{0x2a,0x2a,0x2a},{0x2a,0x2a,0x2a},{0x2a,0x2a,0x2a},
00502   {0x2a,0x2a,0x2a},{0x2a,0x2a,0x2a},{0x2a,0x2a,0x2a},{0x2a,0x2a,0x2a},{0x2a,0x2a,0x2a},{0x2a,0x2a,0x2a},{0x2a,0x2a,0x2a},{0x2a,0x2a,0x2a},
00503   {0x3f,0x3f,0x3f},{0x3f,0x3f,0x3f},{0x3f,0x3f,0x3f},{0x3f,0x3f,0x3f},{0x3f,0x3f,0x3f},{0x3f,0x3f,0x3f},{0x3f,0x3f,0x3f},{0x3f,0x3f,0x3f},
00504   {0x00,0x00,0x00},{0x00,0x00,0x00},{0x00,0x00,0x00},{0x00,0x00,0x00},{0x00,0x00,0x00},{0x00,0x00,0x00},{0x00,0x00,0x00},{0x00,0x00,0x00},
00505   {0x2a,0x2a,0x2a},{0x2a,0x2a,0x2a},{0x2a,0x2a,0x2a},{0x2a,0x2a,0x2a},{0x2a,0x2a,0x2a},{0x2a,0x2a,0x2a},{0x2a,0x2a,0x2a},{0x2a,0x2a,0x2a},
00506   {0x2a,0x2a,0x2a},{0x2a,0x2a,0x2a},{0x2a,0x2a,0x2a},{0x2a,0x2a,0x2a},{0x2a,0x2a,0x2a},{0x2a,0x2a,0x2a},{0x2a,0x2a,0x2a},{0x2a,0x2a,0x2a},
00507   {0x3f,0x3f,0x3f},{0x3f,0x3f,0x3f},{0x3f,0x3f,0x3f},{0x3f,0x3f,0x3f},{0x3f,0x3f,0x3f},{0x3f,0x3f,0x3f},{0x3f,0x3f,0x3f},{0x3f,0x3f,0x3f} 
00508 };
00509 
00510 static Bit8u ega_palette[64][3]=
00511 {
00512   {0x00,0x00,0x00}, {0x00,0x00,0x2a}, {0x00,0x2a,0x00}, {0x00,0x2a,0x2a}, {0x2a,0x00,0x00}, {0x2a,0x00,0x2a}, {0x2a,0x15,0x00}, {0x2a,0x2a,0x2a},
00513   {0x00,0x00,0x00}, {0x00,0x00,0x2a}, {0x00,0x2a,0x00}, {0x00,0x2a,0x2a}, {0x2a,0x00,0x00}, {0x2a,0x00,0x2a}, {0x2a,0x15,0x00}, {0x2a,0x2a,0x2a},
00514   {0x15,0x15,0x15}, {0x15,0x15,0x3f}, {0x15,0x3f,0x15}, {0x15,0x3f,0x3f}, {0x3f,0x15,0x15}, {0x3f,0x15,0x3f}, {0x3f,0x3f,0x15}, {0x3f,0x3f,0x3f},
00515   {0x15,0x15,0x15}, {0x15,0x15,0x3f}, {0x15,0x3f,0x15}, {0x15,0x3f,0x3f}, {0x3f,0x15,0x15}, {0x3f,0x15,0x3f}, {0x3f,0x3f,0x15}, {0x3f,0x3f,0x3f},
00516   {0x00,0x00,0x00}, {0x00,0x00,0x2a}, {0x00,0x2a,0x00}, {0x00,0x2a,0x2a}, {0x2a,0x00,0x00}, {0x2a,0x00,0x2a}, {0x2a,0x15,0x00}, {0x2a,0x2a,0x2a},
00517   {0x00,0x00,0x00}, {0x00,0x00,0x2a}, {0x00,0x2a,0x00}, {0x00,0x2a,0x2a}, {0x2a,0x00,0x00}, {0x2a,0x00,0x2a}, {0x2a,0x15,0x00}, {0x2a,0x2a,0x2a},
00518   {0x15,0x15,0x15}, {0x15,0x15,0x3f}, {0x15,0x3f,0x15}, {0x15,0x3f,0x3f}, {0x3f,0x15,0x15}, {0x3f,0x15,0x3f}, {0x3f,0x3f,0x15}, {0x3f,0x3f,0x3f},
00519   {0x15,0x15,0x15}, {0x15,0x15,0x3f}, {0x15,0x3f,0x15}, {0x15,0x3f,0x3f}, {0x3f,0x15,0x15}, {0x3f,0x15,0x3f}, {0x3f,0x3f,0x15}, {0x3f,0x3f,0x3f}
00520 };
00521 
00522 static Bit8u cga_palette[16][3]=
00523 {
00524         {0x00,0x00,0x00}, {0x00,0x00,0x2a}, {0x00,0x2a,0x00}, {0x00,0x2a,0x2a}, {0x2a,0x00,0x00}, {0x2a,0x00,0x2a}, {0x2a,0x15,0x00}, {0x2a,0x2a,0x2a},
00525         {0x15,0x15,0x15}, {0x15,0x15,0x3f}, {0x15,0x3f,0x15}, {0x15,0x3f,0x3f}, {0x3f,0x15,0x15}, {0x3f,0x15,0x3f}, {0x3f,0x3f,0x15}, {0x3f,0x3f,0x3f},
00526 };
00527 
00528 static Bit8u cga_palette_2[64][3]=
00529 {
00530         {0x00,0x00,0x00}, {0x00,0x00,0x2a}, {0x00,0x2a,0x00}, {0x00,0x2a,0x2a}, {0x2a,0x00,0x00}, {0x2a,0x00,0x2a}, {0x2a,0x15,0x00}, {0x2a,0x2a,0x2a},
00531         {0x00,0x00,0x00}, {0x00,0x00,0x2a}, {0x00,0x2a,0x00}, {0x00,0x2a,0x2a}, {0x2a,0x00,0x00}, {0x2a,0x00,0x2a}, {0x2a,0x15,0x00}, {0x2a,0x2a,0x2a},
00532         {0x15,0x15,0x15}, {0x15,0x15,0x3f}, {0x15,0x3f,0x15}, {0x15,0x3f,0x3f}, {0x3f,0x15,0x15}, {0x3f,0x15,0x3f}, {0x3f,0x3f,0x15}, {0x3f,0x3f,0x3f},
00533         {0x15,0x15,0x15}, {0x15,0x15,0x3f}, {0x15,0x3f,0x15}, {0x15,0x3f,0x3f}, {0x3f,0x15,0x15}, {0x3f,0x15,0x3f}, {0x3f,0x3f,0x15}, {0x3f,0x3f,0x3f},
00534         {0x00,0x00,0x00}, {0x00,0x00,0x2a}, {0x00,0x2a,0x00}, {0x00,0x2a,0x2a}, {0x2a,0x00,0x00}, {0x2a,0x00,0x2a}, {0x2a,0x15,0x00}, {0x2a,0x2a,0x2a},
00535         {0x00,0x00,0x00}, {0x00,0x00,0x2a}, {0x00,0x2a,0x00}, {0x00,0x2a,0x2a}, {0x2a,0x00,0x00}, {0x2a,0x00,0x2a}, {0x2a,0x15,0x00}, {0x2a,0x2a,0x2a},
00536         {0x15,0x15,0x15}, {0x15,0x15,0x3f}, {0x15,0x3f,0x15}, {0x15,0x3f,0x3f}, {0x3f,0x15,0x15}, {0x3f,0x15,0x3f}, {0x3f,0x3f,0x15}, {0x3f,0x3f,0x3f},
00537         {0x15,0x15,0x15}, {0x15,0x15,0x3f}, {0x15,0x3f,0x15}, {0x15,0x3f,0x3f}, {0x3f,0x15,0x15}, {0x3f,0x15,0x3f}, {0x3f,0x3f,0x15}, {0x3f,0x3f,0x3f},
00538 };
00539 
00540 static Bit8u vga_palette[248][3]=
00541 {
00542   {0x00,0x00,0x00},{0x00,0x00,0x2a},{0x00,0x2a,0x00},{0x00,0x2a,0x2a},{0x2a,0x00,0x00},{0x2a,0x00,0x2a},{0x2a,0x15,0x00},{0x2a,0x2a,0x2a},
00543   {0x15,0x15,0x15},{0x15,0x15,0x3f},{0x15,0x3f,0x15},{0x15,0x3f,0x3f},{0x3f,0x15,0x15},{0x3f,0x15,0x3f},{0x3f,0x3f,0x15},{0x3f,0x3f,0x3f},
00544   {0x00,0x00,0x00},{0x05,0x05,0x05},{0x08,0x08,0x08},{0x0b,0x0b,0x0b},{0x0e,0x0e,0x0e},{0x11,0x11,0x11},{0x14,0x14,0x14},{0x18,0x18,0x18},
00545   {0x1c,0x1c,0x1c},{0x20,0x20,0x20},{0x24,0x24,0x24},{0x28,0x28,0x28},{0x2d,0x2d,0x2d},{0x32,0x32,0x32},{0x38,0x38,0x38},{0x3f,0x3f,0x3f},
00546   {0x00,0x00,0x3f},{0x10,0x00,0x3f},{0x1f,0x00,0x3f},{0x2f,0x00,0x3f},{0x3f,0x00,0x3f},{0x3f,0x00,0x2f},{0x3f,0x00,0x1f},{0x3f,0x00,0x10},
00547   {0x3f,0x00,0x00},{0x3f,0x10,0x00},{0x3f,0x1f,0x00},{0x3f,0x2f,0x00},{0x3f,0x3f,0x00},{0x2f,0x3f,0x00},{0x1f,0x3f,0x00},{0x10,0x3f,0x00},
00548   {0x00,0x3f,0x00},{0x00,0x3f,0x10},{0x00,0x3f,0x1f},{0x00,0x3f,0x2f},{0x00,0x3f,0x3f},{0x00,0x2f,0x3f},{0x00,0x1f,0x3f},{0x00,0x10,0x3f},
00549   {0x1f,0x1f,0x3f},{0x27,0x1f,0x3f},{0x2f,0x1f,0x3f},{0x37,0x1f,0x3f},{0x3f,0x1f,0x3f},{0x3f,0x1f,0x37},{0x3f,0x1f,0x2f},{0x3f,0x1f,0x27},
00550 
00551   {0x3f,0x1f,0x1f},{0x3f,0x27,0x1f},{0x3f,0x2f,0x1f},{0x3f,0x37,0x1f},{0x3f,0x3f,0x1f},{0x37,0x3f,0x1f},{0x2f,0x3f,0x1f},{0x27,0x3f,0x1f},
00552   {0x1f,0x3f,0x1f},{0x1f,0x3f,0x27},{0x1f,0x3f,0x2f},{0x1f,0x3f,0x37},{0x1f,0x3f,0x3f},{0x1f,0x37,0x3f},{0x1f,0x2f,0x3f},{0x1f,0x27,0x3f},
00553   {0x2d,0x2d,0x3f},{0x31,0x2d,0x3f},{0x36,0x2d,0x3f},{0x3a,0x2d,0x3f},{0x3f,0x2d,0x3f},{0x3f,0x2d,0x3a},{0x3f,0x2d,0x36},{0x3f,0x2d,0x31},
00554   {0x3f,0x2d,0x2d},{0x3f,0x31,0x2d},{0x3f,0x36,0x2d},{0x3f,0x3a,0x2d},{0x3f,0x3f,0x2d},{0x3a,0x3f,0x2d},{0x36,0x3f,0x2d},{0x31,0x3f,0x2d},
00555   {0x2d,0x3f,0x2d},{0x2d,0x3f,0x31},{0x2d,0x3f,0x36},{0x2d,0x3f,0x3a},{0x2d,0x3f,0x3f},{0x2d,0x3a,0x3f},{0x2d,0x36,0x3f},{0x2d,0x31,0x3f},
00556   {0x00,0x00,0x1c},{0x07,0x00,0x1c},{0x0e,0x00,0x1c},{0x15,0x00,0x1c},{0x1c,0x00,0x1c},{0x1c,0x00,0x15},{0x1c,0x00,0x0e},{0x1c,0x00,0x07},
00557   {0x1c,0x00,0x00},{0x1c,0x07,0x00},{0x1c,0x0e,0x00},{0x1c,0x15,0x00},{0x1c,0x1c,0x00},{0x15,0x1c,0x00},{0x0e,0x1c,0x00},{0x07,0x1c,0x00},
00558   {0x00,0x1c,0x00},{0x00,0x1c,0x07},{0x00,0x1c,0x0e},{0x00,0x1c,0x15},{0x00,0x1c,0x1c},{0x00,0x15,0x1c},{0x00,0x0e,0x1c},{0x00,0x07,0x1c},
00559 
00560   {0x0e,0x0e,0x1c},{0x11,0x0e,0x1c},{0x15,0x0e,0x1c},{0x18,0x0e,0x1c},{0x1c,0x0e,0x1c},{0x1c,0x0e,0x18},{0x1c,0x0e,0x15},{0x1c,0x0e,0x11},
00561   {0x1c,0x0e,0x0e},{0x1c,0x11,0x0e},{0x1c,0x15,0x0e},{0x1c,0x18,0x0e},{0x1c,0x1c,0x0e},{0x18,0x1c,0x0e},{0x15,0x1c,0x0e},{0x11,0x1c,0x0e},
00562   {0x0e,0x1c,0x0e},{0x0e,0x1c,0x11},{0x0e,0x1c,0x15},{0x0e,0x1c,0x18},{0x0e,0x1c,0x1c},{0x0e,0x18,0x1c},{0x0e,0x15,0x1c},{0x0e,0x11,0x1c},
00563   {0x14,0x14,0x1c},{0x16,0x14,0x1c},{0x18,0x14,0x1c},{0x1a,0x14,0x1c},{0x1c,0x14,0x1c},{0x1c,0x14,0x1a},{0x1c,0x14,0x18},{0x1c,0x14,0x16},
00564   {0x1c,0x14,0x14},{0x1c,0x16,0x14},{0x1c,0x18,0x14},{0x1c,0x1a,0x14},{0x1c,0x1c,0x14},{0x1a,0x1c,0x14},{0x18,0x1c,0x14},{0x16,0x1c,0x14},
00565   {0x14,0x1c,0x14},{0x14,0x1c,0x16},{0x14,0x1c,0x18},{0x14,0x1c,0x1a},{0x14,0x1c,0x1c},{0x14,0x1a,0x1c},{0x14,0x18,0x1c},{0x14,0x16,0x1c},
00566   {0x00,0x00,0x10},{0x04,0x00,0x10},{0x08,0x00,0x10},{0x0c,0x00,0x10},{0x10,0x00,0x10},{0x10,0x00,0x0c},{0x10,0x00,0x08},{0x10,0x00,0x04},
00567   {0x10,0x00,0x00},{0x10,0x04,0x00},{0x10,0x08,0x00},{0x10,0x0c,0x00},{0x10,0x10,0x00},{0x0c,0x10,0x00},{0x08,0x10,0x00},{0x04,0x10,0x00},
00568 
00569   {0x00,0x10,0x00},{0x00,0x10,0x04},{0x00,0x10,0x08},{0x00,0x10,0x0c},{0x00,0x10,0x10},{0x00,0x0c,0x10},{0x00,0x08,0x10},{0x00,0x04,0x10},
00570   {0x08,0x08,0x10},{0x0a,0x08,0x10},{0x0c,0x08,0x10},{0x0e,0x08,0x10},{0x10,0x08,0x10},{0x10,0x08,0x0e},{0x10,0x08,0x0c},{0x10,0x08,0x0a},
00571   {0x10,0x08,0x08},{0x10,0x0a,0x08},{0x10,0x0c,0x08},{0x10,0x0e,0x08},{0x10,0x10,0x08},{0x0e,0x10,0x08},{0x0c,0x10,0x08},{0x0a,0x10,0x08},
00572   {0x08,0x10,0x08},{0x08,0x10,0x0a},{0x08,0x10,0x0c},{0x08,0x10,0x0e},{0x08,0x10,0x10},{0x08,0x0e,0x10},{0x08,0x0c,0x10},{0x08,0x0a,0x10},
00573   {0x0b,0x0b,0x10},{0x0c,0x0b,0x10},{0x0d,0x0b,0x10},{0x0f,0x0b,0x10},{0x10,0x0b,0x10},{0x10,0x0b,0x0f},{0x10,0x0b,0x0d},{0x10,0x0b,0x0c},
00574   {0x10,0x0b,0x0b},{0x10,0x0c,0x0b},{0x10,0x0d,0x0b},{0x10,0x0f,0x0b},{0x10,0x10,0x0b},{0x0f,0x10,0x0b},{0x0d,0x10,0x0b},{0x0c,0x10,0x0b},
00575   {0x0b,0x10,0x0b},{0x0b,0x10,0x0c},{0x0b,0x10,0x0d},{0x0b,0x10,0x0f},{0x0b,0x10,0x10},{0x0b,0x0f,0x10},{0x0b,0x0d,0x10},{0x0b,0x0c,0x10}
00576 };
00577 VideoModeBlock * CurMode = NULL;
00578 
00579 static bool SetCurMode(VideoModeBlock modeblock[],Bit16u mode) {
00580         Bitu i=0;
00581         while (modeblock[i].mode!=0xffff) {
00582                 if (modeblock[i].mode!=mode)
00583                         i++;
00584                 /* Hack for VBE 1.2 modes and 24/32bpp ambiguity UNLESS the user changed the mode */
00585                 else if (modeblock[i].mode >= 0x100 && modeblock[i].mode <= 0x11F &&
00586             !(modeblock[i].special & _USER_MODIFIED) &&
00587                         ((modeblock[i].type == M_LIN32 && !vesa12_modes_32bpp) ||
00588                         (modeblock[i].type == M_LIN24 && vesa12_modes_32bpp))) {
00589                         /* ignore */
00590                         i++;
00591                 }
00592         /* ignore deleted modes */
00593         else if (modeblock[i].type == M_ERROR) {
00594             /* ignore */
00595             i++;
00596         }
00597             /* ignore disabled modes */
00598         else if (modeblock[i].special & _USER_DISABLED) {
00599             /* ignore */
00600             i++;
00601         }
00602                 else {
00603                         if ((!int10.vesa_oldvbe) || (ModeList_VGA[i].mode<0x120)) {
00604                                 CurMode=&modeblock[i];
00605                                 return true;
00606                         }
00607                         return false;
00608                 }
00609         }
00610         return false;
00611 }
00612 
00613 static void SetTextLines(void) {
00614         // check for scanline backwards compatibility (VESA text modes??)
00615         switch (real_readb(BIOSMEM_SEG,BIOSMEM_MODESET_CTL)&0x90) {
00616         case 0x80: // 200 lines emulation
00617                 if (CurMode->mode <= 3) {
00618                         CurMode = &ModeList_VGA_Text_200lines[CurMode->mode];
00619                 } else if (CurMode->mode == 7) {
00620                         CurMode = &ModeList_VGA_Text_350lines[4];
00621                 }
00622                 break;
00623         case 0x00: // 350 lines emulation
00624                 if (CurMode->mode <= 3) {
00625                         CurMode = &ModeList_VGA_Text_350lines[CurMode->mode];
00626                 } else if (CurMode->mode == 7) {
00627                         CurMode = &ModeList_VGA_Text_350lines[4];
00628                 }
00629                 break;
00630         }
00631 }
00632 
00633 bool INT10_SetCurMode(void) {
00634         bool mode_changed=false;
00635         Bit16u bios_mode=(Bit16u)real_readb(BIOSMEM_SEG,BIOSMEM_CURRENT_MODE);
00636         if (CurMode == NULL || CurMode->mode != bios_mode) {
00637                 switch (machine) {
00638                 case MCH_CGA:
00639                         if (bios_mode<7) mode_changed=SetCurMode(ModeList_OTHER,bios_mode);
00640                         break;
00641                 case MCH_MCGA:
00642                         mode_changed=SetCurMode(ModeList_MCGA,bios_mode);
00643                         break;
00644                 case TANDY_ARCH_CASE:
00645                         if (bios_mode!=7 && bios_mode<=0xa) mode_changed=SetCurMode(ModeList_OTHER,bios_mode);
00646                         break;
00647                 case MCH_MDA:
00648                 case MCH_HERC:
00649                         break;
00650                 case MCH_EGA:
00651                         mode_changed=SetCurMode(ModeList_EGA,bios_mode);
00652                         break;
00653                 case VGA_ARCH_CASE:
00654                         switch (svgaCard) {
00655                         case SVGA_TsengET4K:
00656                         case SVGA_TsengET3K:
00657                                 mode_changed=SetCurMode(ModeList_VGA_Tseng,bios_mode);
00658                                 break;
00659                         case SVGA_ParadisePVGA1A:
00660                                 mode_changed=SetCurMode(ModeList_VGA_Paradise,bios_mode);
00661                                 break;
00662                         case SVGA_S3Trio:
00663                                 if (bios_mode>=0x68 && CurMode->mode==(bios_mode+0x98)) break;
00664                         default:
00665                                 mode_changed=SetCurMode(ModeList_VGA,bios_mode);
00666                                 break;
00667                         }
00668                         if (mode_changed && bios_mode<=3) {
00669                                 switch (real_readb(BIOSMEM_SEG,BIOSMEM_MODESET_CTL)&0x90) {
00670                                 case 0x00:
00671                                         CurMode=&ModeList_VGA_Text_350lines[bios_mode];
00672                                         break;
00673                                 case 0x80:
00674                                         CurMode=&ModeList_VGA_Text_200lines[bios_mode];
00675                                         break;
00676                                 }
00677                         }
00678                         break;
00679                 default:
00680                         break;
00681                 }
00682         }
00683         return mode_changed;
00684 }
00685 
00686 static void FinishSetMode(bool clearmem) {
00687         /* Clear video memory if needs be */
00688         if (clearmem) {
00689         switch (CurMode->type) {
00690         case M_TANDY16:
00691         case M_CGA4:
00692             if ((machine==MCH_PCJR) && (CurMode->mode >= 9)) {
00693                 // PCJR cannot access the full 32k at 0xb800
00694                 for (Bit16u ct=0;ct<16*1024;ct++) {
00695                     // 0x1800 is the last 32k block in 128k, as set in the CRTCPU_PAGE register 
00696                     real_writew(0x1800,ct*2,0x0000);
00697                 }
00698                 break;
00699             }
00700             // fall-through
00701                 case M_CGA2:
00702             if (machine == MCH_MCGA && CurMode->mode == 0x11) {
00703                 for (Bit16u ct=0;ct<32*1024;ct++) {
00704                     real_writew( 0xa000,ct*2,0x0000);
00705                 }
00706             }
00707             else {
00708                 for (Bit16u ct=0;ct<16*1024;ct++) {
00709                     real_writew( 0xb800,ct*2,0x0000);
00710                 }
00711             }
00712                         break;
00713                 case M_TEXT: {
00714                         Bit16u max = (Bit16u)(CurMode->ptotal*CurMode->plength)>>1;
00715                         if (CurMode->mode == 7) {
00716                                 for (Bit16u ct=0;ct<max;ct++) real_writew(0xB000,ct*2,0x0720);
00717                         }
00718                         else {
00719                                 for (Bit16u ct=0;ct<max;ct++) real_writew(0xB800,ct*2,0x0720);
00720                         }
00721                         break;
00722                 }
00723                 case M_EGA:     
00724                 case M_VGA:
00725                 case M_LIN8:
00726                 case M_LIN4:
00727                 case M_LIN15:
00728                 case M_LIN16:
00729                 case M_LIN24:
00730                 case M_LIN32:
00731         case M_PACKED4:
00732                         /* Hack we just access the memory directly */
00733                         memset(vga.mem.linear,0,vga.mem.memsize);
00734                         break;
00735                 default:
00736                         break;
00737                 }
00738         }
00739         /* Setup the BIOS */
00740         if (CurMode->mode<128) real_writeb(BIOSMEM_SEG,BIOSMEM_CURRENT_MODE,(Bit8u)CurMode->mode);
00741         else real_writeb(BIOSMEM_SEG,BIOSMEM_CURRENT_MODE,(Bit8u)(CurMode->mode-0x98)); //Looks like the s3 bios
00742         real_writew(BIOSMEM_SEG,BIOSMEM_NB_COLS,(Bit16u)CurMode->twidth);
00743         real_writew(BIOSMEM_SEG,BIOSMEM_PAGE_SIZE,(Bit16u)CurMode->plength);
00744         real_writew(BIOSMEM_SEG,BIOSMEM_CRTC_ADDRESS,((CurMode->mode==7 )|| (CurMode->mode==0x0f)) ? 0x3b4 : 0x3d4);
00745         real_writeb(BIOSMEM_SEG,BIOSMEM_NB_ROWS,(Bit8u)(CurMode->theight-1));
00746         real_writew(BIOSMEM_SEG,BIOSMEM_CHAR_HEIGHT,(Bit16u)CurMode->cheight);
00747         real_writeb(BIOSMEM_SEG,BIOSMEM_VIDEO_CTL,(0x60|(clearmem?0:0x80)));
00748         real_writeb(BIOSMEM_SEG,BIOSMEM_SWITCHES,0x09);
00749 
00750         // this is an index into the dcc table:
00751         if (IS_VGA_ARCH) real_writeb(BIOSMEM_SEG,BIOSMEM_DCC_INDEX,0x0b);
00752 
00753         // Set cursor shape
00754         if (CurMode->type==M_TEXT) {
00755                 INT10_SetCursorShape(CURSOR_SCAN_LINE_NORMAL, CURSOR_SCAN_LINE_END);
00756         }
00757         // Set cursor pos for page 0..7
00758         for (Bit8u ct=0;ct<8;ct++) INT10_SetCursorPos(0,0,ct);
00759         // Set active page 0
00760         INT10_SetActivePage(0);
00761         /* Set some interrupt vectors */
00762         if (CurMode->mode<=3 || CurMode->mode==7) {
00763                 RealSetVec(0x43,int10.rom.font_8_first);
00764         } else {
00765                 switch (CurMode->cheight) {
00766                 case 8:RealSetVec(0x43,int10.rom.font_8_first);break;
00767                 case 14:RealSetVec(0x43,int10.rom.font_14);break;
00768                 case 16:RealSetVec(0x43,int10.rom.font_16);break;
00769                 }
00770         }
00771         /* FIXME */
00772         VGA_DAC_UpdateColorPalette();
00773 }
00774 
00775 extern bool en_int33;
00776 
00777 bool INT10_SetVideoMode_OTHER(Bit16u mode,bool clearmem) {
00778         switch (machine) {
00779         case MCH_CGA:
00780         case MCH_AMSTRAD:
00781                 if (mode>6) return false;
00782         case TANDY_ARCH_CASE:
00783                 if (mode>0xa) return false;
00784                 if (mode==7) mode=0; // PCJR defaults to 0 on illegal mode 7
00785                 if (!SetCurMode(ModeList_OTHER,mode)) {
00786                         LOG(LOG_INT10,LOG_ERROR)("Trying to set illegal mode %X",mode);
00787                         return false;
00788                 }
00789                 break;
00790         case MCH_MCGA:
00791         if (!SetCurMode(ModeList_MCGA,mode)) {
00792             LOG(LOG_INT10,LOG_ERROR)("Trying to set illegal mode %X",mode);
00793             return false;
00794         }
00795         break;
00796     case MCH_MDA:
00797     case MCH_HERC:
00798                 // Allow standard color modes if equipment word is not set to mono (Victory Road)
00799                 if ((real_readw(BIOSMEM_SEG,BIOSMEM_INITIAL_MODE)&0x30)!=0x30 && mode<7) {
00800                         SetCurMode(ModeList_OTHER,mode);
00801                         FinishSetMode(clearmem);
00802                         return true;
00803                 }
00804                 CurMode=&Hercules_Mode;
00805                 mode=7; // in case the video parameter table is modified
00806                 break;
00807         default:
00808                 break;
00809         }
00810         LOG(LOG_INT10,LOG_NORMAL)("Set Video Mode %X",mode);
00811 
00812         /* Setup the CRTC */
00813         Bit16u crtc_base=(machine==MCH_HERC || machine==MCH_MDA) ? 0x3b4 : 0x3d4;
00814 
00815     if (machine == MCH_MCGA) {
00816         // unlock CRTC regs 0-7
00817         unsigned char x;
00818 
00819         IO_WriteB(crtc_base,0x10);
00820         x = IO_ReadB(crtc_base+1);
00821         IO_WriteB(crtc_base+1,x & 0x7F);
00822     }
00823 
00824         //Horizontal total
00825         IO_WriteW(crtc_base,(Bit16u)(0x00 | (CurMode->htotal) << 8));
00826     if (machine == MCH_MCGA) {
00827         //Horizontal displayed
00828         IO_WriteW(crtc_base,(Bit16u)(0x01 | (CurMode->hdispend-1) << 8));
00829         //Horizontal sync position
00830         IO_WriteW(crtc_base,(Bit16u)(0x02 | (CurMode->hdispend) << 8));
00831     }
00832     else {
00833         //Horizontal displayed
00834         IO_WriteW(crtc_base,(Bit16u)(0x01 | (CurMode->hdispend) << 8));
00835         //Horizontal sync position
00836         IO_WriteW(crtc_base,(Bit16u)(0x02 | (CurMode->hdispend+1) << 8));
00837     }
00838     //Horizontal sync width, seems to be fixed to 0xa, for cga at least, hercules has 0xf
00839         // PCjr doubles sync width in high resolution modes, good for aspect correction
00840         // newer "compatible" CGA BIOS does the same
00841         // The IBM CGA card seems to limit retrace pulse widths
00842         Bitu syncwidth;
00843         if(machine==MCH_HERC || machine==MCH_MDA) syncwidth = 0xf;
00844         else if(CurMode->hdispend==80) syncwidth = 0xc;
00845         else syncwidth = 0x6;
00846         
00847         IO_WriteW(crtc_base,(Bit16u)(0x03 | (syncwidth) << 8));
00849         IO_WriteW(crtc_base,(Bit16u)(0x04 | (CurMode->vtotal) << 8));
00850         //Vertical total adjust, 6 for cga,hercules,tandy
00851         IO_WriteW(crtc_base,(Bit16u)(0x05 | (6) << 8));
00852         //Vertical displayed
00853         IO_WriteW(crtc_base,(Bit16u)(0x06 | (CurMode->vdispend) << 8));
00854         //Vertical sync position
00855         IO_WriteW(crtc_base,(Bit16u)(0x07 | (CurMode->vdispend + ((CurMode->vtotal - CurMode->vdispend)/2)-1) << 8));
00856         //Maximum scanline
00857         Bit8u scanline,crtpage;
00858         scanline=8;
00859         switch(CurMode->type) {
00860         case M_TEXT: // text mode character height
00861                 if (machine==MCH_HERC || machine==MCH_MDA) scanline=14;
00862                 else scanline=8;
00863                 break;
00864     case M_CGA2: // graphics mode: even/odd banks interleaved
00865         if (machine == MCH_MCGA && CurMode->mode >= 0x11)
00866             scanline = 1; // as seen on real hardware, modes 0x11 and 0x13 have max scanline register == 0x00
00867         else
00868             scanline = 2;
00869         break;
00870     case M_VGA: // MCGA
00871         if (machine == MCH_MCGA)
00872             scanline = 1; // as seen on real hardware, modes 0x11 and 0x13 have max scanline register == 0x00
00873         else
00874             scanline = 2;
00875         break;
00876         case M_CGA4:
00877                 if (CurMode->mode!=0xa) scanline=2;
00878                 else scanline=4;
00879                 break;
00880         case M_TANDY16:
00881                 if (CurMode->mode!=0x9) scanline=2;
00882                 else scanline=4;
00883                 break;
00884         default:
00885                 break;
00886         }
00887 
00888     if (machine == MCH_MCGA) {
00889         IO_Write(0x3c8,0);
00890         for (unsigned int i=0;i<248;i++) {
00891             IO_Write(0x3c9,vga_palette[i][0]);
00892             IO_Write(0x3c9,vga_palette[i][1]);
00893             IO_Write(0x3c9,vga_palette[i][2]);
00894         }
00895                 IO_Write(0x3c6,0xff); //Reset Pelmask
00896     }
00897 
00898         IO_WriteW(crtc_base,0x09 | (scanline-1u) << 8u);
00899         //Setup the CGA palette using VGA DAC palette
00900         for (Bit8u ct=0;ct<16;ct++) VGA_DAC_SetEntry(ct,cga_palette[ct][0],cga_palette[ct][1],cga_palette[ct][2]);
00901         //Setup the tandy palette
00902         for (Bit8u ct=0;ct<16;ct++) VGA_DAC_CombineColor(ct,ct);
00903         //Setup the special registers for each machine type
00904         Bit8u mode_control_list[0xa+1]={
00905                 0x2c,0x28,0x2d,0x29,    //0-3
00906                 0x2a,0x2e,0x1e,0x29,    //4-7
00907                 0x2a,0x2b,0x3b                  //8-a
00908         };
00909         Bit8u mode_control_list_pcjr[0xa+1]={
00910                 0x0c,0x08,0x0d,0x09,    //0-3
00911                 0x0a,0x0e,0x0e,0x09,    //4-7           
00912                 0x1a,0x1b,0x0b                  //8-a
00913         };
00914         Bit8u mode_control,color_select;
00915         switch (machine) {
00916         case MCH_MDA:
00917         case MCH_HERC:
00918                 IO_WriteB(0x3b8,0x28);  // TEXT mode and blinking characters
00919 
00920                 Herc_Palette();
00921                 VGA_DAC_CombineColor(0,0);
00922 
00923                 real_writeb(BIOSMEM_SEG,BIOSMEM_CURRENT_MSR,0x29); // attribute controls blinking
00924                 break;
00925         case MCH_AMSTRAD:
00926                 IO_WriteB( 0x3d9, 0x0f );
00927         case MCH_CGA:
00928         case MCH_MCGA:
00929         if (CurMode->mode == 0x13 && machine == MCH_MCGA)
00930             mode_control=0x0a;
00931         else if (CurMode->mode == 0x11 && machine == MCH_MCGA)
00932             mode_control=0x1e;
00933         else if (CurMode->mode < sizeof(mode_control_list))
00934             mode_control=mode_control_list[CurMode->mode];
00935         else
00936             mode_control=0x00;
00937 
00938                 if (CurMode->mode == 0x6) color_select=0x3f;
00939         else if (CurMode->mode == 0x11) color_select=0x3f;
00940                 else color_select=0x30;
00941                 IO_WriteB(0x3d8,mode_control);
00942                 IO_WriteB(0x3d9,color_select);
00943                 real_writeb(BIOSMEM_SEG,BIOSMEM_CURRENT_MSR,mode_control);
00944                 real_writeb(BIOSMEM_SEG,BIOSMEM_CURRENT_PAL,color_select);
00945                 if (mono_cga) Mono_CGA_Palette();
00946 
00947         if (machine == MCH_MCGA) {
00948             unsigned char mcga_mode = 0x10;
00949 
00950             if (CurMode->type == M_VGA)
00951                 mcga_mode |= 0x01;//320x200 256-color
00952             else if (CurMode->type == M_CGA2 && CurMode->sheight > 240)
00953                 mcga_mode |= 0x02;//640x480 2-color
00954 
00955             /* real hardware: BIOS sets the "hardware computes horizontal timings" bits for mode 0-3 */
00956             if (CurMode->mode <= 0x03)
00957                 mcga_mode |= 0x08;//hardware computes horizontal timing
00958 
00959             /* real hardware: unknown bit 2 is set for all modes except 640x480 2-color */
00960             if (CurMode->mode != 0x11)
00961                 mcga_mode |= 0x04;//unknown bit?
00962 
00963             /* real hardware: unknown bit 5 if set for all 640-wide modes */
00964             if (CurMode->swidth >= 500)
00965                 mcga_mode |= 0x20;//unknown bit?
00966 
00967             /* write protect registers 0-7 if INT 10h mode 2 or 3 to mirror real hardware
00968              * behavior observed through CRTC register dumps on MCGA hardware */
00969             if (CurMode->mode == 2 || CurMode->mode == 3)
00970                 mcga_mode |= 0x80;
00971 
00972             IO_WriteW(crtc_base,0x10 | (mcga_mode) << 8);
00973         }
00974                 break;
00975         case MCH_TANDY:
00976                 /* Init some registers */
00977                 IO_WriteB(0x3da,0x1);IO_WriteB(0x3de,0xf);              //Palette mask always 0xf
00978                 IO_WriteB(0x3da,0x2);IO_WriteB(0x3de,0x0);              //black border
00979                 IO_WriteB(0x3da,0x3);                                                   //Tandy color overrides?
00980                 switch (CurMode->mode) {
00981                 case 0x8:       
00982                         IO_WriteB(0x3de,0x14);break;
00983                 case 0x9:
00984                         IO_WriteB(0x3de,0x14);break;
00985                 case 0xa:
00986                         IO_WriteB(0x3de,0x0c);break;
00987                 default:
00988                         IO_WriteB(0x3de,0x0);break;
00989                 }
00990                 // write palette
00991                 for(Bit8u i = 0; i < 16; i++) {
00992                         IO_WriteB(0x3da,i+0x10);
00993                         IO_WriteB(0x3de,i);
00994                 }
00995                 //Clear extended mapping
00996                 IO_WriteB(0x3da,0x5);
00997                 IO_WriteB(0x3de,0x0);
00998                 //Clear monitor mode
00999                 IO_WriteB(0x3da,0x8);
01000                 IO_WriteB(0x3de,0x0);
01001                 crtpage=(CurMode->mode>=0x9) ? 0xf6 : 0x3f;
01002                 IO_WriteB(0x3df,crtpage);
01003                 real_writeb(BIOSMEM_SEG,BIOSMEM_CRTCPU_PAGE,crtpage);
01004                 mode_control=mode_control_list[CurMode->mode];
01005                 if (CurMode->mode == 0x6 || CurMode->mode==0xa) color_select=0x3f;
01006                 else color_select=0x30;
01007                 IO_WriteB(0x3d8,mode_control);
01008                 IO_WriteB(0x3d9,color_select);
01009                 real_writeb(BIOSMEM_SEG,BIOSMEM_CURRENT_MSR,mode_control);
01010                 real_writeb(BIOSMEM_SEG,BIOSMEM_CURRENT_PAL,color_select);
01011                 break;
01012         case MCH_PCJR:
01013                 /* Init some registers */
01014                 IO_ReadB(0x3da);
01015                 IO_WriteB(0x3da,0x1);IO_WriteB(0x3da,0xf);              //Palette mask always 0xf
01016                 IO_WriteB(0x3da,0x2);IO_WriteB(0x3da,0x0);              //black border
01017                 IO_WriteB(0x3da,0x3);
01018                 if (CurMode->mode<=0x04) IO_WriteB(0x3da,0x02);
01019                 else if (CurMode->mode==0x06) IO_WriteB(0x3da,0x08);
01020                 else IO_WriteB(0x3da,0x00);
01021 
01022                 /* set CRT/Processor page register */
01023                 if (CurMode->mode<0x04) crtpage=0x3f;
01024                 else if (CurMode->mode>=0x09) crtpage=0xf6;
01025                 else crtpage=0x7f;
01026                 IO_WriteB(0x3df,crtpage);
01027                 real_writeb(BIOSMEM_SEG,BIOSMEM_CRTCPU_PAGE,crtpage);
01028 
01029                 mode_control=mode_control_list_pcjr[CurMode->mode];
01030                 IO_WriteB(0x3da,0x0);IO_WriteB(0x3da,mode_control);
01031                 real_writeb(BIOSMEM_SEG,BIOSMEM_CURRENT_MSR,mode_control);
01032 
01033                 if (CurMode->mode == 0x6 || CurMode->mode==0xa) color_select=0x3f;
01034                 else color_select=0x30;
01035                 real_writeb(BIOSMEM_SEG,BIOSMEM_CURRENT_PAL,color_select);
01036                 INT10_SetColorSelect(1);
01037                 INT10_SetBackgroundBorder(0);
01038                 break;
01039         default:
01040                 break;
01041         }
01042 
01043         // Check if the program wants us to use a custom mode table
01044         RealPt vparams = RealGetVec(0x1d);
01045         if (vparams != 0 && (vparams != BIOS_VIDEO_TABLE_LOCATION) && (mode < 8)) {
01046                 // load crtc parameters from video params table
01047                 Bit16u crtc_block_index = 0;
01048                 if (mode < 2) crtc_block_index = 0;
01049                 else if (mode < 4) crtc_block_index = 1;
01050                 else if (mode < 7) crtc_block_index = 2;
01051                 else if (mode == 7) crtc_block_index = 3; // MDA mono mode; invalid for others
01052                 else if (mode < 9) crtc_block_index = 2;
01053                 else crtc_block_index = 3; // Tandy/PCjr modes
01054 
01055                 // init CRTC registers
01056                 for (Bit16u i = 0; i < 16; i++)
01057                         IO_WriteW(crtc_base, (uint16_t)(i | (real_readb(RealSeg(vparams), 
01058                                 RealOff(vparams) + i + crtc_block_index*16) << 8)));
01059         }
01060         FinishSetMode(clearmem);
01061 
01062         if (en_int33) INT10_SetCurMode();
01063 
01064         return true;
01065 }
01066 
01067 bool unmask_irq0_on_int10_setmode = true;
01068 
01069 bool INT10_SetVideoMode(Bit16u mode) {
01070         //LOG_MSG("set mode %x",mode);
01071         bool clearmem=true;Bitu i;
01072         if (mode>=0x100) {
01073                 if ((mode & 0x4000) && int10.vesa_nolfb) return false;
01074                 if (mode & 0x8000) clearmem=false;
01075                 mode&=0xfff;
01076         }
01077         if ((mode<0x100) && (mode & 0x80)) {
01078                 clearmem=false;
01079                 mode-=0x80;
01080         }
01081 
01082     if (unmask_irq0_on_int10_setmode) {
01083         /* setting the video mode unmasks certain IRQs as a matter of course */
01084         PIC_SetIRQMask(0,false); /* Enable system timer */
01085     }
01086 
01087         int10.vesa_setmode=0xffff;
01088         LOG(LOG_INT10,LOG_NORMAL)("Set Video Mode %X",mode);
01089         if (!IS_EGAVGA_ARCH) return INT10_SetVideoMode_OTHER(mode,clearmem);
01090 
01091         /* First read mode setup settings from bios area */
01092 //      Bit8u video_ctl=real_readb(BIOSMEM_SEG,BIOSMEM_VIDEO_CTL);
01093 //      Bit8u vga_switches=real_readb(BIOSMEM_SEG,BIOSMEM_SWITCHES);
01094         Bit8u modeset_ctl=real_readb(BIOSMEM_SEG,BIOSMEM_MODESET_CTL);
01095 
01096         if (IS_VGA_ARCH) {
01097                 if (svga.accepts_mode) {
01098                         if (!svga.accepts_mode(mode)) return false;
01099                 }
01100 
01101                 switch(svgaCard) {
01102                 case SVGA_TsengET4K:
01103                 case SVGA_TsengET3K:
01104                         if (!SetCurMode(ModeList_VGA_Tseng,mode)){
01105                                 LOG(LOG_INT10,LOG_ERROR)("VGA:Trying to set illegal mode %X",mode);
01106                                 return false;
01107                         }
01108                         break;
01109                 case SVGA_ParadisePVGA1A:
01110                         if (!SetCurMode(ModeList_VGA_Paradise,mode)){
01111                                 LOG(LOG_INT10,LOG_ERROR)("VGA:Trying to set illegal mode %X",mode);
01112                                 return false;
01113                         }
01114                         break;
01115                 default:
01116                         if (!SetCurMode(ModeList_VGA,mode)){
01117                                 LOG(LOG_INT10,LOG_ERROR)("VGA:Trying to set illegal mode %X",mode);
01118                                 return false;
01119                         }
01120                 }
01121                 if (CurMode->type==M_TEXT) SetTextLines();
01122 
01123         // INT 10h modeset will always clear 8-bit DAC mode (by VESA BIOS standards)
01124         vga_8bit_dac = false;
01125         VGA_DAC_UpdateColorPalette();
01126     } else {
01127                 if (!SetCurMode(ModeList_EGA,mode)){
01128                         LOG(LOG_INT10,LOG_ERROR)("EGA:Trying to set illegal mode %X",mode);
01129                         return false;
01130                 }
01131         }
01132 
01133         /* Setup the VGA to the correct mode */
01134         // turn off video
01135         IO_Write(0x3c4,0); IO_Write(0x3c5,1); // reset
01136         IO_Write(0x3c4,1); IO_Write(0x3c5,0x20); // screen off
01137 
01138         Bit16u crtc_base;
01139         bool mono_mode=(mode == 7) || (mode==0xf);  
01140         if (mono_mode) crtc_base=0x3b4;
01141         else crtc_base=0x3d4;
01142 
01143         /* Setup MISC Output Register */
01144         Bit8u misc_output=0x2 | (mono_mode ? 0x0 : 0x1);
01145 
01146         if (machine==MCH_EGA) {
01147                 // 16MHz clock for 350-line EGA modes except mode F
01148                 if ((CurMode->vdispend==350) && (mode!=0xf)) misc_output|=0x4;
01149         } else {
01150                 // 28MHz clock for 9-pixel wide chars
01151                 if ((CurMode->type==M_TEXT) && (CurMode->cwidth==9)) misc_output|=0x4;
01152         }
01153 
01154         switch (CurMode->vdispend) {
01155         case 400: 
01156                 misc_output|=0x60;
01157                 break;
01158         case 480:
01159                 misc_output|=0xe0;
01160                 break;
01161         case 350:
01162                 misc_output|=0xa0;
01163                 break;
01164         case 200:
01165         default:
01166                 misc_output|=0x20;
01167         }
01168         IO_Write(0x3c2,misc_output);            //Setup for 3b4 or 3d4
01169         
01170         if (IS_VGA_ARCH && (svgaCard == SVGA_S3Trio)) {
01171         // unlock the S3 registers
01172                 IO_Write(crtc_base,0x38);IO_Write(crtc_base+1u,0x48);   //Register lock 1
01173                 IO_Write(crtc_base,0x39);IO_Write(crtc_base+1u,0xa5);   //Register lock 2
01174                 IO_Write(0x3c4,0x8);IO_Write(0x3c5,0x06);
01175                 // Disable MMIO here so we can read / write memory
01176                 IO_Write(crtc_base,0x53);IO_Write(crtc_base+1u,0x0);
01177         }
01178         
01179         /* Program Sequencer */
01180         Bit8u seq_data[SEQ_REGS];
01181         memset(seq_data,0,SEQ_REGS);
01182         
01183         seq_data[0] = 0x3;      // not reset
01184         seq_data[1] = 0x21;     // screen still disabled, will be enabled at end of setmode
01185         seq_data[4] = 0x04;     // odd/even disable
01186         
01187         if (CurMode->special & _EGA_HALF_CLOCK) seq_data[1]|=0x08; //Check for half clock
01188         if ((machine==MCH_EGA) && (CurMode->special & _EGA_HALF_CLOCK)) seq_data[1]|=0x02;
01189 
01190         if (IS_VGA_ARCH || (IS_EGA_ARCH && vga.mem.memsize >= 0x20000))
01191         seq_data[4]|=0x02;      //More than 64kb
01192     else if (IS_EGA_ARCH && CurMode->vdispend==350) {
01193         seq_data[4] &= ~0x04; // turn on odd/even
01194         seq_data[1] |= 0x04; // half clock
01195     }
01196 
01197         switch (CurMode->type) {
01198         case M_TEXT:
01199                 if (CurMode->cwidth==9) seq_data[1] &= ~1;
01200                 seq_data[2]|=0x3;                               //Enable plane 0 and 1
01201                 seq_data[4]|=0x01;                              //Alpanumeric
01202                 seq_data[4]&=~0x04;                             //odd/even enable
01203                 break;
01204         case M_CGA2:
01205                 if (IS_EGAVGA_ARCH) {
01206                         seq_data[2]|=0x1;                       //Enable plane 0. Most VGA cards treat it as a 640x200 variant of the MCGA 2-color mode, with bit 13 remapped for interlace
01207                 }
01208                 break;
01209         case M_CGA4:
01210                 if (IS_EGAVGA_ARCH) {
01211                         seq_data[2]|=0x3;                       //Enable plane 0 and 1
01212                         seq_data[4]&=~0x04;                     //odd/even enable
01213                 }
01214                 break;
01215         case M_LIN4:
01216         case M_EGA:
01217                 seq_data[2]|=0xf;                               //Enable all planes for writing
01218                 break;
01219         case M_LIN8:                                            //Seems to have the same reg layout from testing
01220         case M_LIN15:
01221         case M_LIN16:
01222         case M_LIN24:
01223         case M_LIN32:
01224     case M_PACKED4:
01225         case M_VGA:
01226                 seq_data[2]|=0xf;                               //Enable all planes for writing
01227                 seq_data[4]|=0x8;                               //Graphics - Chained
01228                 break;
01229         default:
01230                 break;
01231         }
01232         for (Bit8u ct=0;ct<SEQ_REGS;ct++) {
01233                 IO_Write(0x3c4,ct);
01234                 IO_Write(0x3c5,seq_data[ct]);
01235         }
01236 
01237         /* NTS: S3 INT 10 modesetting code below sets this bit anyway when writing CRTC register 0x31.
01238          *      It needs to be done as I/O port write so that Windows 95 can virtualize it properly when
01239          *      we're called to set INT10 mode 3 (from within virtual 8086 mode) when opening a DOS box.
01240          *
01241          *      If we just set it directly, then the generic S3 driver in Windows 95 cannot trap the I/O
01242          *      and prevent our own INT 10h handler from setting the VGA memory mapping into "compatible
01243          *      chain 4" mode, and then any non accelerated drawing from the Windows driver becomes a
01244          *      garbled mess spread out across the screen (due to the weird way that VGA planar memory
01245          *      is "chained" on SVGA chipsets).
01246          *
01247          *      The S3 linear framebuffer isn't affected by VGA chained mode, which is why only the
01248          *      generic S3 driver was affected by this bug, since the generic S3 driver is the one that
01249          *      uses only VGA access (0xA0000-0xAFFFF) and SVGA bank switching while the more specific
01250          *      "S3 Trio32 PCI" driver uses the linear framebuffer.
01251          *
01252          *      But to avoid breaking other SVGA emulation in DOSBox-X, we still set this manually for
01253          *      other VGA/SVGA emulation cases, just not S3 Trio emulation. */
01254         if (svgaCard != SVGA_S3Trio)
01255                 vga.config.compatible_chain4 = true; // this may be changed by SVGA chipset emulation
01256 
01257         if( machine==MCH_AMSTRAD )
01258         {
01259                 vga.amstrad.mask_plane = 0x07070707;
01260                 vga.amstrad.write_plane = 0x0F;
01261                 vga.amstrad.read_plane = 0x00;
01262                 vga.amstrad.border_color = 0x00;
01263         }
01264 
01265         /* Program CRTC */
01266         /* First disable write protection */
01267         IO_Write(crtc_base,0x11);
01268         IO_Write(crtc_base+1u,IO_Read(crtc_base+1u)&0x7f);
01269         /* Clear all the regs */
01270         for (Bit8u ct=0x0;ct<=0x18;ct++) {
01271                 IO_Write(crtc_base,ct);IO_Write(crtc_base+1u,0);
01272         }
01273         Bit8u overflow=0;Bit8u max_scanline=0;
01274         Bit8u ver_overflow=0;Bit8u hor_overflow=0;
01275         /* Horizontal Total */
01276         IO_Write(crtc_base,0x00);IO_Write(crtc_base+1u,(Bit8u)(CurMode->htotal-5));
01277         hor_overflow|=((CurMode->htotal-5) & 0x100) >> 8;
01278         /* Horizontal Display End */
01279         IO_Write(crtc_base,0x01);IO_Write(crtc_base+1u,(Bit8u)(CurMode->hdispend-1));
01280         hor_overflow|=((CurMode->hdispend-1) & 0x100) >> 7;
01281         /* Start horizontal Blanking */
01282         IO_Write(crtc_base,0x02);IO_Write(crtc_base+1u,(Bit8u)CurMode->hdispend);
01283         hor_overflow|=((CurMode->hdispend) & 0x100) >> 6;
01284         /* End horizontal Blanking */
01285         Bitu blank_end=(CurMode->htotal-2) & 0x7f;
01286         IO_Write(crtc_base,0x03);IO_Write(crtc_base+1u,0x80|(blank_end & 0x1f));
01287 
01288         /* Start Horizontal Retrace */
01289         Bitu ret_start;
01290         if ((CurMode->special & _EGA_HALF_CLOCK) && (CurMode->type!=M_CGA2)) ret_start = (CurMode->hdispend+3);
01291         else if (CurMode->type==M_TEXT) ret_start = (CurMode->hdispend+5);
01292         else ret_start = (CurMode->hdispend+4);
01293         IO_Write(crtc_base,0x04);IO_Write(crtc_base+1u,(Bit8u)ret_start);
01294         hor_overflow|=(ret_start & 0x100) >> 4;
01295 
01296         /* End Horizontal Retrace */
01297         Bitu ret_end;
01298         if (CurMode->special & _EGA_HALF_CLOCK) {
01299                 if (CurMode->type==M_CGA2) ret_end=0;   // mode 6
01300                 else if (CurMode->special & _DOUBLESCAN) ret_end = (CurMode->htotal-18) & 0x1f;
01301                 else ret_end = ((CurMode->htotal-18) & 0x1f) | 0x20; // mode 0&1 have 1 char sync delay
01302         } else if (CurMode->type==M_TEXT) ret_end = (CurMode->htotal-3) & 0x1f;
01303         else ret_end = (CurMode->htotal-4) & 0x1f;
01304         
01305         IO_Write(crtc_base,0x05);IO_Write(crtc_base+1u,(Bit8u)(ret_end | (blank_end & 0x20) << 2));
01306 
01307         /* Vertical Total */
01308         IO_Write(crtc_base,0x06);IO_Write(crtc_base+1u,(Bit8u)(CurMode->vtotal-2));
01309         overflow|=((CurMode->vtotal-2) & 0x100) >> 8;
01310         overflow|=((CurMode->vtotal-2) & 0x200) >> 4;
01311         ver_overflow|=((CurMode->vtotal-2) & 0x400) >> 10;
01312 
01313         Bitu vretrace;
01314         if (IS_VGA_ARCH) {
01315                 switch (CurMode->vdispend) {
01316                 case 400: vretrace=CurMode->vdispend+12;
01317                                 break;
01318                 case 480: vretrace=CurMode->vdispend+10;
01319                                 break;
01320                 case 350: vretrace=CurMode->vdispend+37;
01321                                 break;
01322                 default: vretrace=CurMode->vdispend+12;
01323                 }
01324         } else {
01325                 switch (CurMode->vdispend) {
01326                 case 350: vretrace=CurMode->vdispend;
01327                                 break;
01328                 default: vretrace=CurMode->vdispend+24;
01329                 }
01330         }
01331 
01332         /* Vertical Retrace Start */
01333         IO_Write(crtc_base,0x10);IO_Write(crtc_base+1u,(Bit8u)vretrace);
01334         overflow|=(vretrace & 0x100) >> 6;
01335         overflow|=(vretrace & 0x200) >> 2;
01336         ver_overflow|=(vretrace & 0x400) >> 6;
01337 
01338         /* Vertical Retrace End */
01339         IO_Write(crtc_base,0x11);IO_Write(crtc_base+1u,(vretrace+2) & 0xF);
01340 
01341         /* Vertical Display End */
01342         IO_Write(crtc_base,0x12);IO_Write(crtc_base+1u,(Bit8u)(CurMode->vdispend-1));
01343         overflow|=((CurMode->vdispend-1) & 0x100) >> 7;
01344         overflow|=((CurMode->vdispend-1) & 0x200) >> 3;
01345         ver_overflow|=((CurMode->vdispend-1) & 0x400) >> 9;
01346         
01347         Bitu vblank_trim;
01348         if (IS_VGA_ARCH) {
01349                 switch (CurMode->vdispend) {
01350                 case 400: vblank_trim=6;
01351                                 break;
01352                 case 480: vblank_trim=7;
01353                                 break;
01354                 case 350: vblank_trim=5;
01355                                 break;
01356                 default: vblank_trim=8;
01357                 }
01358         } else {
01359                 switch (CurMode->vdispend) {
01360                 case 350: vblank_trim=0;
01361                                 break;
01362                 default: vblank_trim=23;
01363                 }
01364         }
01365 
01366         /* Vertical Blank Start */
01367         IO_Write(crtc_base,0x15);IO_Write(crtc_base+1u,(Bit8u)(CurMode->vdispend+vblank_trim));
01368         overflow|=((CurMode->vdispend+vblank_trim) & 0x100) >> 5;
01369         max_scanline|=((CurMode->vdispend+vblank_trim) & 0x200) >> 4;
01370         ver_overflow|=((CurMode->vdispend+vblank_trim) & 0x400) >> 8;
01371 
01372         /* Vertical Blank End */
01373         IO_Write(crtc_base,0x16);IO_Write(crtc_base+1u,(Bit8u)(CurMode->vtotal-vblank_trim-2));
01374 
01375         /* Line Compare */
01376         Bitu line_compare=(CurMode->vtotal < 1024) ? 1023 : 2047;
01377         IO_Write(crtc_base,0x18);IO_Write(crtc_base+1u,line_compare&0xff);
01378         overflow|=(line_compare & 0x100) >> 4;
01379         max_scanline|=(line_compare & 0x200) >> 3;
01380         ver_overflow|=(line_compare & 0x400) >> 4;
01381         Bit8u underline=0;
01382         /* Maximum scanline / Underline Location */
01383         if (CurMode->special & _DOUBLESCAN) max_scanline|=0x80;
01384         if (CurMode->special & _REPEAT1) max_scanline|=0x01;
01385 
01386         switch (CurMode->type) {
01387         case M_TEXT:
01388                 if(IS_VGA_ARCH) {
01389                         switch(modeset_ctl & 0x90) {
01390                         case 0x0: // 350-lines mode: 8x14 font
01391                                 max_scanline |= (14-1);
01392                                 break;
01393                         default: // reserved
01394                         case 0x10: // 400 lines 8x16 font
01395                 max_scanline|=CurMode->cheight-1;
01396                                 break;
01397                         case 0x80: // 200 lines: 8x8 font and doublescan
01398                                 max_scanline |= (8-1);
01399                                 max_scanline |= 0x80;
01400                                 break;
01401                         }
01402                 } else max_scanline |= CurMode->cheight-1;
01403                 underline=(Bit8u)(mono_mode ? CurMode->cheight-1 : 0x1f); // mode 7 uses underline position
01404                 break;
01405         case M_VGA:
01406                 underline=0x40;
01407                 break;
01408         case M_LIN8:
01409         case M_LIN15:
01410         case M_LIN16:
01411         case M_LIN24:
01412         case M_LIN32:
01413                 underline=0x60;                 //Seems to enable the every 4th clock on my s3
01414                 break;
01415         default:
01416             /* do NOT apply this to VESA BIOS modes */
01417                 if (CurMode->mode < 0x100 && CurMode->vdispend==350) underline=0x0f;
01418                 break;
01419         }
01420 
01421         IO_Write(crtc_base,0x09);IO_Write(crtc_base+1u,max_scanline);
01422         IO_Write(crtc_base,0x14);IO_Write(crtc_base+1u,underline);
01423 
01424         /* OverFlow */
01425         IO_Write(crtc_base,0x07);IO_Write(crtc_base+1u,overflow);
01426 
01427         if (svgaCard == SVGA_S3Trio) {
01428                 /* Extended Horizontal Overflow */
01429                 IO_Write(crtc_base,0x5d);IO_Write(crtc_base+1u,hor_overflow);
01430                 /* Extended Vertical Overflow */
01431                 IO_Write(crtc_base,0x5e);IO_Write(crtc_base+1u,ver_overflow);
01432         }
01433 
01434         /* Offset Register */
01435         Bitu offset;
01436         switch (CurMode->type) {
01437         case M_LIN8:
01438                 offset = CurMode->swidth/8;
01439                 break;
01440         case M_LIN15:
01441         case M_LIN16:
01442                 offset = 2 * CurMode->swidth/8;
01443                 break;
01444         case M_LIN24:
01445                 offset = 3 * CurMode->swidth/8;
01446                 break;
01447         case M_LIN32:
01448                 offset = 4 * CurMode->swidth/8;
01449                 break;
01450     case M_EGA:
01451         if (IS_EGA_ARCH && vga.mem.memsize < 0x20000 && CurMode->vdispend==350)
01452             offset = CurMode->hdispend/4;
01453         else
01454             offset = CurMode->hdispend/2;
01455                 break;
01456         default:
01457         offset = CurMode->hdispend/2;
01458         break;
01459     }
01460         IO_Write(crtc_base,0x13);
01461         IO_Write(crtc_base + 1u,offset & 0xff);
01462 
01463         if (svgaCard == SVGA_S3Trio) {
01464                 /* Extended System Control 2 Register  */
01465                 /* This register actually has more bits but only use the extended offset ones */
01466                 IO_Write(crtc_base,0x51);
01467                 IO_Write(crtc_base + 1u,(Bit8u)((offset & 0x300) >> 4));
01468                 /* Clear remaining bits of the display start */
01469                 IO_Write(crtc_base,0x69);
01470                 IO_Write(crtc_base + 1u,0);
01471                 /* Extended Vertical Overflow */
01472                 IO_Write(crtc_base,0x5e);IO_Write(crtc_base+1u,ver_overflow);
01473         }
01474 
01475         /* Mode Control */
01476         Bit8u mode_control=0;
01477 
01478         switch (CurMode->type) {
01479         case M_CGA2:
01480                 mode_control=0xc2; // 0x06 sets address wrap.
01481                 break;
01482         case M_CGA4:
01483                 mode_control=0xa2;
01484                 break;
01485         case M_LIN4:
01486         case M_EGA:
01487         if (CurMode->mode==0x11) // 0x11 also sets address wrap.  thought maybe all 2 color modes did but 0x0f doesn't.
01488             mode_control=0xc3; // so.. 0x11 or 0x0f a one off?
01489         else
01490             mode_control=0xe3;
01491 
01492         if (IS_EGA_ARCH && vga.mem.memsize < 0x20000 && CurMode->vdispend==350)
01493             mode_control &= ~0x40; // word mode
01494                 break;
01495         case M_TEXT:
01496         case M_VGA:
01497         case M_LIN8:
01498         case M_LIN15:
01499         case M_LIN16:
01500         case M_LIN24:
01501         case M_LIN32:
01502     case M_PACKED4:
01503                 mode_control=0xa3;
01504                 if (CurMode->special & _VGA_PIXEL_DOUBLE)
01505                         mode_control |= 0x08;
01506                 break;
01507         default:
01508                 break;
01509         }
01510 
01511     if (IS_EGA_ARCH && vga.mem.memsize < 0x20000)
01512         mode_control &= ~0x20; // address wrap bit 13
01513 
01514     IO_Write(crtc_base, 0x17); IO_Write(crtc_base + 1u, mode_control);
01515         /* Renable write protection */
01516         IO_Write(crtc_base,0x11);
01517         IO_Write(crtc_base+1u,IO_Read(crtc_base+1u)|0x80);
01518 
01519         if (svgaCard == SVGA_S3Trio) {
01520                 /* Setup the correct clock */
01521                 if (CurMode->mode>=0x100) {
01522                         misc_output|=0xef;              //Select clock 3 
01523                         Bitu clock=CurMode->vtotal*8*CurMode->htotal*70;
01524                         if(CurMode->type==M_LIN15 || CurMode->type==M_LIN16) clock/=2;
01525                         VGA_SetClock(3,clock/1000);
01526                 }
01527                 Bit8u misc_control_2;
01528                 /* Setup Pixel format */
01529                 switch (CurMode->type) {
01530                 case M_LIN8:
01531                 default:
01532                         misc_control_2=0x00;
01533                         break;
01534                 case M_LIN15:
01535                         misc_control_2=0x30;
01536                         break;
01537                 case M_LIN16:
01538                         misc_control_2=0x50;
01539                         break;
01540                 case M_LIN24:
01541                         misc_control_2=0x70; /* FIXME: Is this right? I have no other reference than comments in vga_s3.cpp and s3freak's patch */
01542                         break;
01543                 case M_LIN32:
01544                         misc_control_2=0xd0;
01545                         break;
01546         case M_PACKED4://HACK
01547                         misc_control_2=0xf0;
01548                         break;
01549                 }
01550                 IO_WriteB(crtc_base,0x67);IO_WriteB(crtc_base+1u,misc_control_2);
01551         }
01552 
01553         /* Write Misc Output */
01554         IO_Write(0x3c2,misc_output);
01555         /* Program Graphics controller */
01556         Bit8u gfx_data[GFX_REGS];
01557         memset(gfx_data,0,GFX_REGS);
01558         gfx_data[0x7]=0xf;                              /* Color don't care */
01559         gfx_data[0x8]=0xff;                             /* BitMask */
01560         switch (CurMode->type) {
01561         case M_TEXT:
01562                 gfx_data[0x5]|=0x10;            //Odd-Even Mode
01563                 gfx_data[0x6]|=mono_mode ? 0x0a : 0x0e;         //Either b800 or b000, chain odd/even enable
01564                 break;
01565         case M_LIN8:
01566         case M_LIN15:
01567         case M_LIN16:
01568         case M_LIN24:
01569         case M_LIN32:
01570     case M_PACKED4:
01571         gfx_data[0x5] |= 0x40;          //256 color mode
01572         if (int10_vesa_map_as_128kb)
01573             gfx_data[0x6] |= 0x01;      //graphics mode at 0xa000-bffff
01574         else
01575             gfx_data[0x6] |= 0x05;      //graphics mode at 0xa000-affff
01576         break;
01577         case M_VGA:
01578                 gfx_data[0x5]|=0x40;            //256 color mode
01579                 gfx_data[0x6]|=0x05;            //graphics mode at 0xa000-affff
01580                 break;
01581         case M_LIN4:
01582         case M_EGA:
01583         if (IS_EGA_ARCH && vga.mem.memsize < 0x20000 && CurMode->vdispend==350) {
01584             gfx_data[0x5]|=0x10;                //Odd-Even Mode
01585             gfx_data[0x6]|=0x02;                //Odd-Even Mode
01586                 gfx_data[0x7]=0x5;                      /* Color don't care */
01587         }
01588                 gfx_data[0x6]|=0x05;            //graphics mode at 0xa000-affff
01589                 break;
01590         case M_CGA4:
01591                 gfx_data[0x5]|=0x20;            //CGA mode
01592                 gfx_data[0x6]|=0x0f;            //graphics mode at at 0xb800=0xbfff
01593                 if (IS_EGAVGA_ARCH) gfx_data[0x5]|=0x10;
01594                 break;
01595         case M_CGA2:
01596                 gfx_data[0x6]|=0x0d;            //graphics mode at at 0xb800=0xbfff, chain odd/even disabled
01597                 break;
01598         default:
01599                 break;
01600         }
01601         for (Bit8u ct=0;ct<GFX_REGS;ct++) {
01602                 IO_Write(0x3ce,ct);
01603                 IO_Write(0x3cf,gfx_data[ct]);
01604         }
01605         Bit8u att_data[ATT_REGS];
01606         memset(att_data,0,ATT_REGS);
01607         att_data[0x12]=0xf;                             //Always have all color planes enabled
01608         /* Program Attribute Controller */
01609         switch (CurMode->type) {
01610         case M_EGA:
01611         case M_LIN4:
01612                 att_data[0x10]=0x01;            //Color Graphics
01613                 switch (CurMode->mode) {
01614                 case 0x0f:
01615                         att_data[0x12]=0x05;    // planes 0 and 2 enabled
01616                         att_data[0x10]|=0x0a;   // monochrome and blinking
01617         
01618                         att_data[0x01]=0x08; // low-intensity
01619                         att_data[0x04]=0x18; // blink-on case
01620                         att_data[0x05]=0x18; // high-intensity
01621                         att_data[0x09]=0x08; // low-intensity in blink-off case
01622                         att_data[0x0d]=0x18; // high-intensity in blink-off
01623                         break;
01624                 case 0x11:
01625                         for (i=1;i<16;i++) att_data[i]=0x3f;
01626                         break;
01627                 case 0x10:
01628                 case 0x12: 
01629                         goto att_text16;
01630                 default:
01631                         if ( CurMode->type == M_LIN4 )
01632                                 goto att_text16;
01633                         for (Bit8u ct=0;ct<8;ct++) {
01634                                 att_data[ct]=ct;
01635                                 att_data[ct+8]=ct+0x10;
01636                         }
01637                         break;
01638                 }
01639                 break;
01640         case M_TANDY16:
01641                 att_data[0x10]=0x01;            //Color Graphics
01642                 for (Bit8u ct=0;ct<16;ct++) att_data[ct]=ct;
01643                 break;
01644         case M_TEXT:
01645                 if (CurMode->cwidth==9) {
01646                         att_data[0x13]=0x08;    //Pel panning on 8, although we don't have 9 dot text mode
01647                         att_data[0x10]=0x0C;    //Color Text with blinking, 9 Bit characters
01648                 } else {
01649                         att_data[0x13]=0x00;
01650                         att_data[0x10]=0x08;    //Color Text with blinking, 8 Bit characters
01651                 }
01652                 real_writeb(BIOSMEM_SEG,BIOSMEM_CURRENT_PAL,0x30);
01653 att_text16:
01654                 if (CurMode->mode==7) {
01655                         att_data[0]=0x00;
01656                         att_data[8]=0x10;
01657                         for (i=1; i<8; i++) {
01658                                 att_data[i]=0x08;
01659                                 att_data[i+8]=0x18;
01660                         }
01661                 } else {
01662                         for (Bit8u ct=0;ct<8;ct++) {
01663                                 att_data[ct]=ct;
01664                                 att_data[ct+8]=ct+0x38;
01665                         }
01666                         att_data[0x06]=0x14;            //Odd Color 6 yellow/brown.
01667                 }
01668                 break;
01669         case M_CGA2:
01670                 att_data[0x10]=0x01;            //Color Graphics
01671                 att_data[0]=0x0;
01672                 for (i=1;i<0x10;i++) att_data[i]=0x17;
01673                 att_data[0x12]=0x1;                     //Only enable 1 plane
01674                 real_writeb(BIOSMEM_SEG,BIOSMEM_CURRENT_PAL,0x3f);
01675                 break;
01676         case M_CGA4:
01677                 att_data[0x12]=0x3;                     //Only enable 2 planes
01678                 att_data[0x10]=0x01;            //Color Graphics
01679                 att_data[0]=0x0;
01680                 att_data[1]=0x13;
01681                 att_data[2]=0x15;
01682                 att_data[3]=0x17;
01683                 att_data[4]=0x02;
01684                 att_data[5]=0x04;
01685                 att_data[6]=0x06;
01686                 att_data[7]=0x07;
01687                 for (Bit8u ct=0x8;ct<0x10;ct++) 
01688                         att_data[ct] = ct + 0x8;
01689                 real_writeb(BIOSMEM_SEG,BIOSMEM_CURRENT_PAL,0x30);
01690                 break;
01691         case M_VGA:
01692         case M_LIN8:
01693         case M_LIN15:
01694         case M_LIN16:
01695         case M_LIN24:
01696         case M_LIN32:
01697     case M_PACKED4:
01698                 for (Bit8u ct=0;ct<16;ct++) att_data[ct]=ct;
01699                 att_data[0x10]=0x41;            //Color Graphics 8-bit
01700                 break;
01701         default:
01702                 break;
01703         }
01704         IO_Read(mono_mode ? 0x3ba : 0x3da);
01705         if ((modeset_ctl & 8)==0) {
01706                 for (Bit8u ct=0;ct<ATT_REGS;ct++) {
01707                         IO_Write(0x3c0,ct);
01708                         IO_Write(0x3c0,att_data[ct]);
01709                 }
01710                 vga.config.pel_panning = 0;
01711                 IO_Write(0x3c0,0x20); IO_Write(0x3c0,0x00); //Disable palette access
01712                 IO_Write(0x3c6,0xff); //Reset Pelmask
01713                 /* Setup the DAC */
01714                 IO_Write(0x3c8,0);
01715                 switch (CurMode->type) {
01716                 case M_EGA:
01717                         if (CurMode->mode>0xf) {
01718                                 goto dac_text16;
01719                         } else if (CurMode->mode==0xf) {
01720                                 for (i=0;i<64;i++) {
01721                                         IO_Write(0x3c9,mtext_s3_palette[i][0]);
01722                                         IO_Write(0x3c9,mtext_s3_palette[i][1]);
01723                                         IO_Write(0x3c9,mtext_s3_palette[i][2]);
01724                                 }
01725                         } else {
01726                                 for (i=0;i<64;i++) {
01727                                         IO_Write(0x3c9,ega_palette[i][0]);
01728                                         IO_Write(0x3c9,ega_palette[i][1]);
01729                                         IO_Write(0x3c9,ega_palette[i][2]);
01730                                 }
01731                         }
01732                         break;
01733                 case M_CGA2:
01734                 case M_CGA4:
01735                 case M_TANDY16:
01736                         for (i=0;i<64;i++) {
01737                                 IO_Write(0x3c9,cga_palette_2[i][0]);
01738                                 IO_Write(0x3c9,cga_palette_2[i][1]);
01739                                 IO_Write(0x3c9,cga_palette_2[i][2]);
01740                         }
01741                         break;
01742                 case M_TEXT:
01743                         if (CurMode->mode==7) {
01744                                 if ((IS_VGA_ARCH) && (svgaCard == SVGA_S3Trio)) {
01745                                         for (i=0;i<64;i++) {
01746                                                 IO_Write(0x3c9,mtext_s3_palette[i][0]);
01747                                                 IO_Write(0x3c9,mtext_s3_palette[i][1]);
01748                                                 IO_Write(0x3c9,mtext_s3_palette[i][2]);
01749                                         }
01750                                 } else {
01751                                         for (i=0;i<64;i++) {
01752                                                 IO_Write(0x3c9,mtext_palette[i][0]);
01753                                                 IO_Write(0x3c9,mtext_palette[i][1]);
01754                                                 IO_Write(0x3c9,mtext_palette[i][2]);
01755                                         }
01756                                 }
01757                                 break;
01758                         } //FALLTHROUGH!!!!
01759                 case M_LIN4: //Added for CAD Software
01760 dac_text16:
01761                         for (i=0;i<64;i++) {
01762                                 IO_Write(0x3c9,text_palette[i][0]);
01763                                 IO_Write(0x3c9,text_palette[i][1]);
01764                                 IO_Write(0x3c9,text_palette[i][2]);
01765                         }
01766                         break;
01767                 case M_VGA:
01768                 case M_LIN8:
01769                 case M_LIN15:
01770                 case M_LIN16:
01771                 case M_LIN24:
01772                 case M_LIN32:
01773         case M_PACKED4:
01774                         // IBM and clones use 248 default colors in the palette for 256-color mode.
01775                         // The last 8 colors of the palette are only initialized to 0 at BIOS init.
01776                         // Palette index is left at 0xf8 as on most clones, IBM leaves it at 0x10.
01777                         for (i=0;i<248;i++) {
01778                                 IO_Write(0x3c9,vga_palette[i][0]);
01779                                 IO_Write(0x3c9,vga_palette[i][1]);
01780                                 IO_Write(0x3c9,vga_palette[i][2]);
01781                         }
01782                         break;
01783                 default:
01784                         break;
01785                 }
01786                 if (IS_VGA_ARCH) {
01787                         /* check if gray scale summing is enabled */
01788                         if (modeset_ctl & 2) INT10_PerformGrayScaleSumming(0,256);
01789                 }
01790         /* make sure the DAC index is reset on modeset */
01791                 IO_Write(0x3c7,0); /* according to src/hardware/vga_dac.cpp this sets read_index=0 and write_index=1 */
01792                 IO_Write(0x3c8,0); /* so set write_index=0 */
01793         } else {
01794                 for (Bit8u ct=0x10;ct<ATT_REGS;ct++) {
01795                         if (ct==0x11) continue; // skip overscan register
01796                         IO_Write(0x3c0,ct);
01797                         IO_Write(0x3c0,att_data[ct]);
01798                 }
01799                 vga.config.pel_panning = 0;
01800         }
01801         /* Write palette register data to dynamic save area if pointer is non-zero */
01802         RealPt vsavept=real_readd(BIOSMEM_SEG,BIOSMEM_VS_POINTER);
01803         RealPt dsapt=real_readd(RealSeg(vsavept),RealOff(vsavept)+4);
01804         if (dsapt) {
01805                 for (Bit8u ct=0;ct<0x10;ct++) {
01806                         real_writeb(RealSeg(dsapt),RealOff(dsapt)+ct,att_data[ct]);
01807                 }
01808                 real_writeb(RealSeg(dsapt),RealOff(dsapt)+0x10,0); // overscan
01809         }
01810         /* Setup some special stuff for different modes */
01811         Bit8u feature=real_readb(BIOSMEM_SEG,BIOSMEM_INITIAL_MODE);
01812         switch (CurMode->type) {
01813         case M_CGA2:
01814                 feature=(feature&~0x30)|0x20;
01815                 real_writeb(BIOSMEM_SEG,BIOSMEM_CURRENT_MSR,0x1e);
01816                 break;
01817         case M_CGA4:
01818                 feature=(feature&~0x30)|0x20;
01819                 if (CurMode->mode==4) real_writeb(BIOSMEM_SEG,BIOSMEM_CURRENT_MSR,0x2a);
01820                 else if (CurMode->mode==5) real_writeb(BIOSMEM_SEG,BIOSMEM_CURRENT_MSR,0x2e);
01821                 else real_writeb(BIOSMEM_SEG,BIOSMEM_CURRENT_MSR,0x2);
01822                 break;
01823         case M_TANDY16:
01824                 feature=(feature&~0x30)|0x20;
01825                 break;
01826         case M_TEXT:
01827                 feature=(feature&~0x30)|0x20;
01828                 switch (CurMode->mode) {
01829                 case 0:real_writeb(BIOSMEM_SEG,BIOSMEM_CURRENT_MSR,0x2c);break;
01830                 case 1:real_writeb(BIOSMEM_SEG,BIOSMEM_CURRENT_MSR,0x28);break;
01831                 case 2:real_writeb(BIOSMEM_SEG,BIOSMEM_CURRENT_MSR,0x2d);break;
01832                 case 3:
01833                 case 7:real_writeb(BIOSMEM_SEG,BIOSMEM_CURRENT_MSR,0x29);break;
01834                 }
01835                 break;
01836         case M_LIN4:
01837         case M_EGA:     
01838         case M_VGA:
01839                 feature=(feature&~0x30);
01840                 break;
01841         default:
01842                 break;
01843         }
01844         // disabled, has to be set in bios.cpp exclusively
01845 //      real_writeb(BIOSMEM_SEG,BIOSMEM_INITIAL_MODE,feature);
01846 
01847         if (svgaCard == SVGA_S3Trio) {
01848                 /* Setup the CPU Window */
01849                 IO_Write(crtc_base,0x6a);
01850                 IO_Write(crtc_base+1u,0);
01851                 /* Setup the linear frame buffer */
01852                 IO_Write(crtc_base,0x59);
01853                 IO_Write(crtc_base+1u,(Bit8u)((S3_LFB_BASE >> 24)&0xff));
01854                 IO_Write(crtc_base,0x5a);
01855                 IO_Write(crtc_base+1u,(Bit8u)((S3_LFB_BASE >> 16)&0xff));
01856                 IO_Write(crtc_base,0x6b); // BIOS scratchpad
01857                 IO_Write(crtc_base+1u,(Bit8u)((S3_LFB_BASE >> 24)&0xff));
01858                 
01859                 /* Setup some remaining S3 registers */
01860                 IO_Write(crtc_base,0x41); // BIOS scratchpad
01861                 IO_Write(crtc_base+1u,0x88);
01862                 IO_Write(crtc_base,0x52); // extended BIOS scratchpad
01863                 IO_Write(crtc_base+1u,0x80);
01864 
01865                 IO_Write(0x3c4,0x15);
01866                 IO_Write(0x3c5,0x03);
01867 
01868                 IO_Write(crtc_base,0x45);
01869                 IO_Write(crtc_base+1u,0x00);
01870 
01871                 // Accellerator setup 
01872                 Bitu reg_50=S3_XGA_8BPP;
01873                 switch (CurMode->type) {
01874                         case M_LIN15:
01875                         case M_LIN16: reg_50|=S3_XGA_16BPP; break;
01876                         case M_LIN32: reg_50|=S3_XGA_32BPP; break;
01877                         default: break;
01878                 }
01879                 switch(CurMode->swidth) {
01880                         case 640:  reg_50|=S3_XGA_640; break;
01881                         case 800:  reg_50|=S3_XGA_800; break;
01882                         case 1024: reg_50|=S3_XGA_1024; break;
01883                         case 1152: reg_50|=S3_XGA_1152; break;
01884                         case 1280: reg_50|=S3_XGA_1280; break;
01885                         case 1600: reg_50|=S3_XGA_1600; break;
01886                         default: break;
01887                 }
01888                 IO_WriteB(crtc_base,0x50); IO_WriteB(crtc_base+1u,(Bit8u)reg_50);
01889 
01890                 Bit8u reg_31, reg_3a;
01891                 switch (CurMode->type) {
01892                         case M_LIN15:
01893                         case M_LIN16:
01894                         case M_LIN24:
01895                         case M_LIN32:
01896             case M_PACKED4:
01897                                 reg_3a=0x15;
01898                                 break;
01899                         case M_LIN8:
01900                                 // S3VBE20 does it this way. The other double pixel bit does not
01901                                 // seem to have an effect on the Trio64.
01902                                 if(CurMode->special&_S3_PIXEL_DOUBLE) reg_3a=0x5;
01903                                 else reg_3a=0x15;
01904                                 break;
01905                         default:
01906                                 reg_3a=5;
01907                                 break;
01908                 }
01909 
01910         unsigned char s3_mode = 0x00;
01911                 
01912                 switch (CurMode->type) {
01913                 case M_LIN4: // <- Theres a discrepance with real hardware on this
01914                 case M_LIN8:
01915                 case M_LIN15:
01916                 case M_LIN16:
01917                 case M_LIN24:
01918                 case M_LIN32:
01919         case M_PACKED4:
01920                         reg_31 = 9;
01921                         break;
01922                 default:
01923                         reg_31 = 5;
01924                         break;
01925                 }
01926 
01927         /* SVGA text modes need the 256k+ access bit */
01928         if (CurMode->mode >= 0x100 && !int10.vesa_nolfb)
01929             reg_31 |= 8; /* enable 256k+ access */
01930 
01931         /* whether to enable the linear framebuffer */
01932         if (CurMode->mode >= 0x100 && !int10.vesa_nolfb)
01933             s3_mode |= 0x10; /* enable LFB */
01934 
01935                 IO_Write(crtc_base,0x3a);IO_Write(crtc_base+1u,reg_3a);
01936                 IO_Write(crtc_base,0x31);IO_Write(crtc_base+1u,reg_31); //Enable banked memory and 256k+ access
01937 
01938                 IO_Write(crtc_base,0x58);
01939                 if (vga.mem.memsize >= (4*1024*1024))
01940                         IO_Write(crtc_base+1u,0x3 | s3_mode);           // 4+ MB window
01941                 else if (vga.mem.memsize >= (2*1024*1024))
01942                         IO_Write(crtc_base+1u,0x2 | s3_mode);           // 2 MB window
01943                 else
01944                         IO_Write(crtc_base+1u,0x1 | s3_mode);           // 1 MB window
01945 
01946                 IO_Write(crtc_base,0x38);IO_Write(crtc_base+1u,0x48);   //Register lock 1
01947                 IO_Write(crtc_base,0x39);IO_Write(crtc_base+1u,0xa5);   //Register lock 2
01948         } else if (svga.set_video_mode) {
01949                 VGA_ModeExtraData modeData;
01950                 modeData.ver_overflow = ver_overflow;
01951                 modeData.hor_overflow = hor_overflow;
01952                 modeData.offset = offset;
01953                 modeData.modeNo = CurMode->mode;
01954                 modeData.htotal = CurMode->htotal;
01955                 modeData.vtotal = CurMode->vtotal;
01956                 svga.set_video_mode(crtc_base, &modeData);
01957         }
01958 
01959         FinishSetMode(clearmem);
01960 
01961         /* Set vga attrib register into defined state */
01962         IO_Read(mono_mode ? 0x3ba : 0x3da);
01963         IO_Write(0x3c0,0x20);
01964         IO_Read(mono_mode ? 0x3ba : 0x3da);
01965 
01966         /* Load text mode font */
01967         if (CurMode->type==M_TEXT) {
01968                 INT10_ReloadFont();
01969         }
01970         // Enable screen memory access
01971         IO_Write(0x3c4,1); IO_Write(0x3c5,seq_data[1] & ~0x20);
01972         //LOG_MSG("setmode end");
01973 
01974         if (en_int33) INT10_SetCurMode();
01975 
01976         return true;
01977 }
01978 
01979 Bitu VideoModeMemSize(Bitu mode) {
01980         if (!IS_VGA_ARCH)
01981                 return 0;
01982 
01983         VideoModeBlock* modelist = NULL;
01984 
01985         switch (svgaCard) {
01986         case SVGA_TsengET4K:
01987         case SVGA_TsengET3K:
01988                 modelist = ModeList_VGA_Tseng;
01989                 break;
01990         case SVGA_ParadisePVGA1A:
01991                 modelist = ModeList_VGA_Paradise;
01992                 break;
01993         default:
01994                 modelist = ModeList_VGA;
01995                 break;
01996         }
01997 
01998         VideoModeBlock* vmodeBlock = NULL;
01999         Bitu i=0;
02000         while (modelist[i].mode!=0xffff) {
02001                 if (modelist[i].mode==mode) {
02002                         /* Hack for VBE 1.2 modes and 24/32bpp ambiguity */
02003                         if (modelist[i].mode >= 0x100 && modelist[i].mode <= 0x11F &&
02004                 !(modelist[i].special & _USER_MODIFIED) &&
02005                                 ((modelist[i].type == M_LIN32 && !vesa12_modes_32bpp) ||
02006                                  (modelist[i].type == M_LIN24 && vesa12_modes_32bpp))) {
02007                                 /* ignore */
02008                         }
02009                         else {
02010                                 vmodeBlock = &modelist[i];
02011                                 break;
02012                         }
02013                 }
02014                 i++;
02015         }
02016 
02017         if (!vmodeBlock)
02018                 return ~0ul;
02019 
02020         switch(vmodeBlock->type) {
02021     case M_PACKED4:
02022                 if (mode >= 0x100 && !allow_vesa_4bpp_packed) return ~0ul;
02023                 return vmodeBlock->swidth*vmodeBlock->sheight/2;
02024         case M_LIN4:
02025                 if (mode >= 0x100 && !allow_vesa_4bpp) return ~0ul;
02026                 return vmodeBlock->swidth*vmodeBlock->sheight/2;
02027         case M_LIN8:
02028                 if (mode >= 0x100 && !allow_vesa_8bpp) return ~0ul;
02029                 return vmodeBlock->swidth*vmodeBlock->sheight;
02030         case M_LIN15:
02031                 if (mode >= 0x100 && !allow_vesa_15bpp) return ~0ul;
02032                 return vmodeBlock->swidth*vmodeBlock->sheight*2;
02033         case M_LIN16:
02034                 if (mode >= 0x100 && !allow_vesa_16bpp) return ~0ul;
02035                 return vmodeBlock->swidth*vmodeBlock->sheight*2;
02036         case M_LIN24:
02037                 if (mode >= 0x100 && !allow_vesa_24bpp) return ~0ul;
02038                 return vmodeBlock->swidth*vmodeBlock->sheight*3;
02039         case M_LIN32:
02040                 if (mode >= 0x100 && !allow_vesa_32bpp) return ~0ul;
02041                 return vmodeBlock->swidth*vmodeBlock->sheight*4;
02042         case M_TEXT:
02043                 if (mode >= 0x100 && !allow_vesa_tty) return ~0ul;
02044                 return vmodeBlock->twidth*vmodeBlock->theight*2;
02045         default:
02046                 break;
02047         }
02048         // Return 0 for all other types, those always fit in memory
02049         return 0;
02050 }
02051 
02052 Bitu INT10_WriteVESAModeList(Bitu max_modes);
02053 
02054 /* ====================== VESAMOED.COM ====================== */
02055 class VESAMOED : public Program {
02056 public:
02057         void Run(void) {
02058         size_t array_i = 0;
02059         std::string arg,tmp;
02060                 bool got_opt=false;
02061         int mode = -1;
02062         int fmt = -1;
02063         int w = -1,h = -1;
02064         int ch = -1;
02065         int newmode = -1;
02066         signed char enable = -1;
02067         bool doDelete = false;
02068         bool modefind = false;
02069                 
02070         cmd->BeginOpt();
02071         while (cmd->GetOpt(/*&*/arg)) {
02072                         got_opt=true;
02073             if (arg == "?" || arg == "help") {
02074                 doHelp();
02075                 break;
02076             }
02077             else if (arg == "mode") {
02078                 cmd->NextOptArgv(/*&*/tmp);
02079 
02080                 if (tmp == "find") {
02081                     modefind = true;
02082                 }
02083                 else if (isdigit(tmp[0])) {
02084                     mode = (int)strtoul(tmp.c_str(),NULL,0);
02085                 }
02086                 else {
02087                     WriteOut("Unknown mode '%s'\n",tmp.c_str());
02088                     return;
02089                 }
02090             }
02091             else if (arg == "fmt") {
02092                 cmd->NextOptArgv(/*&*/tmp);
02093 
02094                      if (tmp == "LIN4")
02095                     fmt = M_LIN4;
02096                 else if (tmp == "LIN8")
02097                     fmt = M_LIN8;
02098                 else if (tmp == "LIN15")
02099                     fmt = M_LIN15;
02100                 else if (tmp == "LIN16")
02101                     fmt = M_LIN16;
02102                 else if (tmp == "LIN24")
02103                     fmt = M_LIN24;
02104                 else if (tmp == "LIN32")
02105                     fmt = M_LIN32;
02106                 else if (tmp == "TEXT")
02107                     fmt = M_TEXT;
02108                 else {
02109                     WriteOut("Unknown format '%s'\n",tmp.c_str());
02110                     return;
02111                 }
02112             }
02113             else if (arg == "w") {
02114                 cmd->NextOptArgv(/*&*/tmp);
02115                 w = (int)strtoul(tmp.c_str(),NULL,0);
02116             }
02117             else if (arg == "h") {
02118                 cmd->NextOptArgv(/*&*/tmp);
02119                 h = (int)strtoul(tmp.c_str(),NULL,0);
02120             }
02121             else if (arg == "ch") {
02122                 cmd->NextOptArgv(/*&*/tmp);
02123                 ch = (int)strtoul(tmp.c_str(),NULL,0);
02124             }
02125             else if (arg == "newmode") {
02126                 cmd->NextOptArgv(/*&*/tmp);
02127 
02128                 if (isdigit(tmp[0])) {
02129                     newmode = (int)strtoul(tmp.c_str(),NULL,0);
02130                 }
02131                 else {
02132                     WriteOut("Unknown newmode '%s'\n",tmp.c_str());
02133                     return;
02134                 }
02135             }
02136             else if (arg == "delete") {
02137                 doDelete = true;
02138             }
02139             // NTS: If you're wondering why we support disabled modes (modes listed but cannot be set),
02140             //      there are plenty of scenarios on actual hardware where this occurs. Laptops, for
02141             //      example, have SVGA chipsets that can go up to 1600x1200, but the BIOS will disable
02142             //      anything above the native resolution of the laptop's LCD display unless an
02143             //      external monitor is attached at boot-up.
02144             else if (arg == "disable") {
02145                 enable = 0;
02146             }
02147             else if (arg == "enable") {
02148                 enable = 1;
02149             }
02150             else {
02151                 WriteOut("Unknown switch %s",arg.c_str());
02152                 return;
02153             }
02154         }
02155         cmd->EndOpt();
02156                 if(!got_opt) {
02157             doHelp();
02158             return;
02159         }
02160 
02161         if (modefind) {
02162             if (w < 0 && h < 0 && fmt < 0)
02163                 return;
02164 
02165             while (ModeList_VGA[array_i].mode != 0xFFFF) {
02166                 bool match = true;
02167 
02168                      if (w > 0 && (Bitu)w != ModeList_VGA[array_i].swidth)
02169                     match = false;
02170                 else if (h > 0 && (Bitu)h != ModeList_VGA[array_i].sheight)
02171                     match = false;
02172                 else if (fmt >= 0 && (Bitu)fmt != ModeList_VGA[array_i].type)
02173                     match = false;
02174                 else if (ModeList_VGA[array_i].type == M_ERROR)
02175                     match = false;
02176                 else if (ModeList_VGA[array_i].mode <= 0x13)
02177                     match = false;
02178 
02179                 if (!match)
02180                     array_i++;
02181                 else
02182                     break;
02183             }
02184         }
02185         else {
02186             while (ModeList_VGA[array_i].mode != 0xFFFF) {
02187                 if (ModeList_VGA[array_i].mode == (Bitu)mode)
02188                     break;
02189 
02190                 array_i++;
02191             }
02192         }
02193 
02194         if (ModeList_VGA[array_i].mode == 0xFFFF) {
02195             WriteOut("Mode not found\n");
02196             return;
02197         }
02198         else if (ModeList_VGA[array_i].mode <= 0x13) {
02199             WriteOut("Editing base VGA modes is not allowed\n");
02200             return;
02201         }
02202         else if (modefind) {
02203             WriteOut("Found mode 0x%x\n",(unsigned int)ModeList_VGA[array_i].mode);
02204         }
02205 
02206         if (enable == 0)
02207             ModeList_VGA[array_i].special |= (Bit16u)  _USER_DISABLED;
02208         else if (enable == 1)
02209             ModeList_VGA[array_i].special &= (Bit16u)(~_USER_DISABLED);
02210 
02211         if (doDelete) {
02212             if (ModeList_VGA[array_i].type != M_ERROR)
02213                 WriteOut("Mode 0x%x deleted\n",ModeList_VGA[array_i].mode);
02214             else
02215                 WriteOut("Mode 0x%x already deleted\n",ModeList_VGA[array_i].mode);
02216 
02217             ModeList_VGA[array_i].type = M_ERROR;
02218             INT10_WriteVESAModeList(int10.rom.vesa_alloc_modes);
02219             return;
02220         }
02221 
02222         if (fmt < 0 && ModeList_VGA[array_i].type == M_ERROR) {
02223             WriteOut("Mode 0x%x is still deleted. Set a format with -fmt to un-delete\n",ModeList_VGA[array_i].mode);
02224             return;
02225         }
02226 
02227         if (!modefind && (w > 0 || h > 0 || fmt >= 0 || ch > 0)) {
02228             WriteOut("Changing mode 0x%x parameters\n",(unsigned int)ModeList_VGA[array_i].mode);
02229 
02230             ModeList_VGA[array_i].special |= _USER_MODIFIED;
02231 
02232             if (fmt >= 0) {
02233                 ModeList_VGA[array_i].type = (VGAModes)fmt;
02234                 /* will require reprogramming width in some cases! */
02235                 if (w < 0) w = (int)ModeList_VGA[array_i].swidth;
02236             }
02237             if (w > 0) {
02238                 /* enforce alignment to avoid problems with modesetting code */
02239                 {
02240                     unsigned int aln = 8;
02241 
02242                     if (ModeList_VGA[array_i].type == M_LIN4)
02243                         aln = 16u;
02244 
02245                     w += (int)(aln / 2u);
02246                     w -= (int)((unsigned int)w % aln);
02247                     if (w == 0u) w = (int)aln;
02248                 }
02249 
02250                 ModeList_VGA[array_i].swidth = (Bitu)w;
02251                 if (ModeList_VGA[array_i].type == M_LIN15 || ModeList_VGA[array_i].type == M_LIN16) {
02252                     ModeList_VGA[array_i].hdispend = (Bitu)w / 4;
02253                     ModeList_VGA[array_i].htotal = ModeList_VGA[array_i].hdispend + 40;
02254                 }
02255                 else {
02256                     ModeList_VGA[array_i].hdispend = (Bitu)w / 8;
02257                     ModeList_VGA[array_i].htotal = ModeList_VGA[array_i].hdispend + 20;
02258                 }
02259             }
02260             if (h > 0) {
02261                 ModeList_VGA[array_i].sheight = (Bitu)h;
02262 
02263                 if (h >= 340)
02264                     ModeList_VGA[array_i].special &= (Bit16u)(~_REPEAT1);
02265                 else
02266                     ModeList_VGA[array_i].special |= (Bit16u)  _REPEAT1;
02267 
02268                 if (ModeList_VGA[array_i].special & _REPEAT1)
02269                     ModeList_VGA[array_i].vdispend = (Bitu)h * 2u;
02270                 else
02271                     ModeList_VGA[array_i].vdispend = (Bitu)h;
02272 
02273                 ModeList_VGA[array_i].vtotal = ModeList_VGA[array_i].vdispend + 49;
02274             }
02275             if (ch == 8 || ch == 14 || ch == 16)
02276                 ModeList_VGA[array_i].cheight = (Bitu)ch;
02277 
02278             ModeList_VGA[array_i].twidth = ModeList_VGA[array_i].swidth / ModeList_VGA[array_i].cwidth;
02279             ModeList_VGA[array_i].theight = ModeList_VGA[array_i].sheight / ModeList_VGA[array_i].cheight;
02280             INT10_WriteVESAModeList(int10.rom.vesa_alloc_modes);
02281         }
02282 
02283         if (newmode >= 0x40) {
02284             WriteOut("Mode 0x%x moved to mode 0x%x\n",(unsigned int)ModeList_VGA[array_i].mode,(unsigned int)newmode);
02285             ModeList_VGA[array_i].mode = (Bit16u)newmode;
02286             INT10_WriteVESAModeList(int10.rom.vesa_alloc_modes);
02287         }
02288 
02289         /* if the new mode cannot fit in available memory, then mark as disabled */
02290         {
02291             unsigned int pitch = 0;
02292 
02293             switch (ModeList_VGA[array_i].type) {
02294                 case M_LIN4:
02295                 case M_PACKED4:
02296                     pitch = (unsigned int)(ModeList_VGA[array_i].swidth / 8) * 4u; /* not totally accurate but close enough */
02297                     break;
02298                 case M_LIN8:
02299                     pitch = (unsigned int)ModeList_VGA[array_i].swidth;
02300                     break;
02301                 case M_LIN15:
02302                 case M_LIN16:
02303                     pitch = (unsigned int)ModeList_VGA[array_i].swidth * 2u;
02304                     break;
02305                 case M_LIN24:
02306                     pitch = (unsigned int)ModeList_VGA[array_i].swidth * 3u;
02307                     break;
02308                 case M_LIN32:
02309                     pitch = (unsigned int)ModeList_VGA[array_i].swidth * 4u;
02310                     break;
02311                 default:
02312                     break;
02313             }
02314 
02315             if ((pitch * ModeList_VGA[array_i].sheight) > vga.mem.memsize) {
02316                 /* NTS: Actually we don't mark as disabled, the VESA mode query function will
02317                  *      report as disabled automatically for the same check we do. This just
02318                  *      lets the user know. */
02319                 WriteOut("WARNING: Mode %u x %u as specified exceeds video memory, will be disabled\n",
02320                         ModeList_VGA[array_i].swidth,
02321                         ModeList_VGA[array_i].sheight);
02322             }
02323         }
02324     }
02325     void doHelp(void) {
02326         WriteOut("VESAMOED VESA BIOS mode editor utility\n");
02327         WriteOut("\n");
02328         WriteOut("NOTE: Due to architectual limitations of VBE emulation,\n");
02329         WriteOut("      Adding new modes is not allowed.\n");
02330         WriteOut("\n");
02331         WriteOut("  -mode <x>               VBE video mode to edit.\n");
02332         WriteOut("                            Specify video mode in decimal or hexadecimal,\n");
02333         WriteOut("                            or specify 'find' to match by fmt, width, height.\n");
02334         WriteOut("  -fmt <x>                Change pixel format, or mode to find.\n");
02335         WriteOut("                            LIN4, LIN8, LIN15, LIN16,\n");
02336         WriteOut("                            LIN24, LIN32, TEXT\n");
02337         WriteOut("  -w <x>                  Change width (in pixels), or mode to find.\n");
02338         WriteOut("  -h <x>                  Change height (in pixels), or mode to find.\n");
02339         WriteOut("  -ch <x>                 Change char height (in pixels), or mode to find.\n");
02340         WriteOut("  -newmode <x>            Change video mode number\n");
02341         WriteOut("  -delete                 Delete video mode\n");
02342         WriteOut("  -disable                Disable video mode (list but do not allow setting)\n");
02343         WriteOut("  -enable                 Enable video mode\n");
02344     }
02345 };
02346 
02347 void VESAMOED_ProgramStart(Program * * make) {
02348         *make=new VESAMOED;
02349 }
02350