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src/ints/int10_modes.cpp
00001 /*
00002  *  Copyright (C) 2002-2015  The DOSBox Team
00003  *
00004  *  This program is free software; you can redistribute it and/or modify
00005  *  it under the terms of the GNU General Public License as published by
00006  *  the Free Software Foundation; either version 2 of the License, or
00007  *  (at your option) any later version.
00008  *
00009  *  This program is distributed in the hope that it will be useful,
00010  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
00011  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
00012  *  GNU General Public License for more details.
00013  *
00014  *  You should have received a copy of the GNU General Public License
00015  *  along with this program; if not, write to the Free Software
00016  *  Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
00017  */
00018 
00019 
00020 #include <string.h>
00021 
00022 #include "dosbox.h"
00023 #include "mem.h"
00024 #include "inout.h"
00025 #include "int10.h"
00026 #include "mouse.h"
00027 #include "vga.h"
00028 #include "bios.h"
00029 #include "programs.h"
00030 
00031 #define SEQ_REGS 0x05
00032 #define GFX_REGS 0x09
00033 #define ATT_REGS 0x15
00034 
00035 extern bool int10_vesa_map_as_128kb;
00036 extern bool allow_vesa_lowres_modes;
00037 extern bool allow_vesa_4bpp_packed;
00038 extern bool vesa12_modes_32bpp;
00039 extern bool allow_vesa_32bpp;
00040 extern bool allow_vesa_24bpp;
00041 extern bool allow_vesa_16bpp;
00042 extern bool allow_vesa_15bpp;
00043 extern bool allow_vesa_8bpp;
00044 extern bool allow_vesa_4bpp;
00045 extern bool allow_vesa_tty;
00046 
00047 VideoModeBlock ModeList_VGA[]={
00048 /* mode  ,type     ,sw  ,sh  ,tw ,th ,cw,ch ,pt,pstart  ,plength,htot,vtot,hde,vde special flags */
00049 { 0x000  ,M_TEXT   ,360 ,400 ,40 ,25 ,9 ,16 ,8 ,0xB8000 ,0x0800 ,50  ,449 ,40 ,400 ,_EGA_HALF_CLOCK     },
00050 { 0x001  ,M_TEXT   ,360 ,400 ,40 ,25 ,9 ,16 ,8 ,0xB8000 ,0x0800 ,50  ,449 ,40 ,400 ,_EGA_HALF_CLOCK     },
00051 { 0x002  ,M_TEXT   ,720 ,400 ,80 ,25 ,9 ,16 ,8 ,0xB8000 ,0x1000 ,100 ,449 ,80 ,400 ,0   },
00052 { 0x003  ,M_TEXT   ,720 ,400 ,80 ,25 ,9 ,16 ,8 ,0xB8000 ,0x1000 ,100 ,449 ,80 ,400 ,0   },
00053 { 0x004  ,M_CGA4   ,320 ,200 ,40 ,25 ,8 ,8  ,1 ,0xB8000 ,0x4000 ,50  ,449 ,40 ,400 ,_EGA_HALF_CLOCK     | _DOUBLESCAN | _REPEAT1},
00054 { 0x005  ,M_CGA4   ,320 ,200 ,40 ,25 ,8 ,8  ,1 ,0xB8000 ,0x4000 ,50  ,449 ,40 ,400 ,_EGA_HALF_CLOCK     | _DOUBLESCAN | _REPEAT1},
00055 { 0x006  ,M_CGA2   ,640 ,200 ,80 ,25 ,8 ,8  ,1 ,0xB8000 ,0x4000 ,100 ,449 ,80 ,400 ,_DOUBLESCAN | _REPEAT1},
00056 { 0x007  ,M_TEXT   ,720 ,400 ,80 ,25 ,9 ,16 ,8 ,0xB0000 ,0x1000 ,100 ,449 ,80 ,400 ,0   },
00057 
00058 { 0x00D  ,M_EGA    ,320 ,200 ,40 ,25 ,8 ,8  ,8 ,0xA0000 ,0x2000 ,50  ,449 ,40 ,400 ,_EGA_HALF_CLOCK     | _DOUBLESCAN   },
00059 { 0x00E  ,M_EGA    ,640 ,200 ,80 ,25 ,8 ,8  ,4 ,0xA0000 ,0x4000 ,100 ,449 ,80 ,400 ,_DOUBLESCAN },
00060 { 0x00F  ,M_EGA    ,640 ,350 ,80 ,25 ,8 ,14 ,2 ,0xA0000 ,0x8000 ,100 ,449 ,80 ,350 ,0   },/*was EGA_2*/
00061 { 0x010  ,M_EGA    ,640 ,350 ,80 ,25 ,8 ,14 ,2 ,0xA0000 ,0x8000 ,100 ,449 ,80 ,350 ,0   },
00062 { 0x011  ,M_EGA    ,640 ,480 ,80 ,30 ,8 ,16 ,1 ,0xA0000 ,0xA000 ,100 ,525 ,80 ,480 ,0   },/*was EGA_2 */
00063 { 0x012  ,M_EGA    ,640 ,480 ,80 ,30 ,8 ,16 ,1 ,0xA0000 ,0xA000 ,100 ,525 ,80 ,480 ,0   },
00064 { 0x013  ,M_VGA    ,320 ,200 ,40 ,25 ,8 ,8  ,1 ,0xA0000 ,0x2000 ,100 ,449 ,80 ,400 ,_REPEAT1   },
00065 
00066 { 0x054  ,M_TEXT   ,1056,344, 132,43, 8,  8, 1 ,0xB8000 ,0x4000, 160, 449, 132,344, 0   },
00067 { 0x055  ,M_TEXT   ,1056,400, 132,25, 8, 16, 1 ,0xB8000 ,0x2000, 160, 449, 132,400, 0   },
00068 
00069 /* Alias of mode 101 */
00070 { 0x069  ,M_LIN8   ,640 ,480 ,80 ,30 ,8 ,16 ,1 ,0xA0000 ,0x10000,100 ,525 ,80 ,480 ,0   },
00071 /* Alias of mode 102 */
00072 { 0x06A  ,M_LIN4   ,800 ,600 ,100,37 ,8 ,16 ,1 ,0xA0000 ,0x10000,128 ,663 ,100,600 ,0   },
00073 
00074 /* Follow vesa 1.2 for first 0x20 */
00075 { 0x100  ,M_LIN8   ,640 ,400 ,80 ,25 ,8 ,16 ,1 ,0xA0000 ,0x10000,100 ,449 ,80 ,400 ,0   },
00076 { 0x101  ,M_LIN8   ,640 ,480 ,80 ,30 ,8 ,16 ,1 ,0xA0000 ,0x10000,100 ,525 ,80 ,480 , _VGA_PIXEL_DOUBLE },
00077 { 0x102  ,M_LIN4   ,800 ,600 ,100,37 ,8 ,16 ,1 ,0xA0000 ,0x10000,132 ,628 ,100,600 ,0   },
00078 { 0x103  ,M_LIN8   ,800 ,600 ,100,37 ,8 ,16 ,1 ,0xA0000 ,0x10000,132 ,628 ,100,600 ,0   },
00079 { 0x104  ,M_LIN4   ,1024,768 ,128,48 ,8 ,16 ,1 ,0xA0000 ,0x10000,168 ,806 ,128,768 ,0   },
00080 { 0x105  ,M_LIN8   ,1024,768 ,128,48 ,8 ,16 ,1 ,0xA0000 ,0x10000,168 ,806 ,128,768 ,0   },
00081 { 0x106  ,M_LIN4   ,1280,1024,160,64 ,8 ,16 ,1 ,0xA0000 ,0x10000,212 ,1066,160,1024,0   },
00082 { 0x107  ,M_LIN8   ,1280,1024,160,64 ,8 ,16 ,1 ,0xA0000 ,0x10000,212 ,1066,160,1024,0   },
00083 
00084 /* VESA text modes */ 
00085 { 0x108  ,M_TEXT   ,640 ,480,  80,60, 8,  8 ,2 ,0xB8000 ,0x4000, 100 ,525 ,80 ,480 ,0   },
00086 { 0x109  ,M_TEXT   ,1056,400, 132,25, 8, 16, 1 ,0xB8000 ,0x2000, 160, 449, 132,400, 0   },
00087 { 0x10A  ,M_TEXT   ,1056,688, 132,43, 8,  8, 1 ,0xB8000 ,0x4000, 160, 449, 132,344, 0   },
00088 { 0x10B  ,M_TEXT   ,1056,400, 132,50, 8,  8, 1 ,0xB8000 ,0x4000, 160, 449, 132,400, 0   },
00089 { 0x10C  ,M_TEXT   ,1056,480, 132,60, 8,  8, 2 ,0xB8000 ,0x4000, 160, 531, 132,480, 0   },
00090 
00091 /* VESA higher color modes.
00092  * Note v1.2 of the VESA BIOS extensions explicitly states modes 0x10F, 0x112, 0x115, 0x118 are 8:8:8 (24-bit) not 8:8:8:8 (32-bit).
00093  * This also fixes COMA "Parhaat" 1997 demo, by offering a true 24bpp mode so that it doesn't try to draw 24bpp on a 32bpp VESA linear framebuffer.
00094  * NTS: The 24bpp modes listed here will not be available to the DOS game/demo if the user says that the VBE 1.2 modes are 32bpp,
00095  *      instead the redefinitions in the next block will apply to allow M_LIN32. To use the 24bpp modes here, you must set 'vesa vbe 1.2 modes are 32bpp=false' */
00096 { 0x10D  ,M_LIN15  ,320 ,200 ,40 ,25 ,8 ,8  ,1 ,0xA0000 ,0x10000,100 ,449 ,80 ,400 , _REPEAT1 },
00097 { 0x10E  ,M_LIN16  ,320 ,200 ,40 ,25 ,8 ,8  ,1 ,0xA0000 ,0x10000,100 ,449 ,80 ,400 , _REPEAT1 },
00098 { 0x10F  ,M_LIN24  ,320 ,200 ,40 ,25 ,8 ,8  ,1 ,0xA0000 ,0x10000,50  ,449 ,40 ,400 , _REPEAT1 },
00099 { 0x110  ,M_LIN15  ,640 ,480 ,80 ,30 ,8 ,16 ,1 ,0xA0000 ,0x10000,200 ,525 ,160,480 ,0   },
00100 { 0x111  ,M_LIN16  ,640 ,480 ,80 ,30 ,8 ,16 ,1 ,0xA0000 ,0x10000,200 ,525 ,160,480 ,0   },
00101 { 0x112  ,M_LIN24  ,640 ,480 ,80 ,30 ,8 ,16 ,1 ,0xA0000 ,0x10000,100 ,525 ,80 ,480 ,0   },
00102 { 0x113  ,M_LIN15  ,800 ,600 ,100,37 ,8 ,16 ,1 ,0xA0000 ,0x10000,264 ,628 ,200,600 ,0   },
00103 { 0x114  ,M_LIN16  ,800 ,600 ,100,37 ,8 ,16 ,1 ,0xA0000 ,0x10000,264 ,628 ,200,600 ,0   },
00104 { 0x115  ,M_LIN24  ,800 ,600 ,100,37 ,8 ,16 ,1 ,0xA0000 ,0x10000,132 ,628 ,100,600 ,0   },
00105 { 0x116  ,M_LIN15  ,1024,768 ,128,48 ,8 ,16 ,1 ,0xA0000 ,0x10000,336 ,806 ,256,768 ,0   },
00106 { 0x117  ,M_LIN16  ,1024,768 ,128,48 ,8 ,16 ,1 ,0xA0000 ,0x10000,336 ,806 ,256,768 ,0   },
00107 { 0x118  ,M_LIN24  ,1024,768 ,128,48 ,8 ,16 ,1 ,0xA0000 ,0x10000,168 ,806 ,128,768 ,0   },
00108 
00109 /* But of course... there are other demos that assume mode 0x10F is 32bpp!
00110  * So we have another definition of those modes that overlaps some of the same mode numbers above.
00111  * This allows "Phenomena" demo to use 32bpp 320x200 mode if you set 'vesa vbe 1.2 modes are 32bpp=true'.
00112  * The code will allow either this block's mode 0x10F (LIN32), or the previous block's mode 0x10F (LIN24), but not both. */
00113 { 0x10F  ,M_LIN32  ,320 ,200 ,40 ,25 ,8 ,8  ,1 ,0xA0000 ,0x10000,50  ,449 ,40 ,400 , _REPEAT1 },
00114 { 0x112  ,M_LIN32  ,640 ,480 ,80 ,30 ,8 ,16 ,1 ,0xA0000 ,0x10000,100 ,525 ,80 ,480 ,0   },
00115 { 0x115  ,M_LIN32  ,800 ,600 ,100,37 ,8 ,16 ,1 ,0xA0000 ,0x10000,132 ,628 ,100,600 ,0   },
00116 { 0x118  ,M_LIN32  ,1024,768 ,128,48 ,8 ,16 ,1 ,0xA0000 ,0x10000,168 ,806 ,128,768 ,0   },
00117 
00118 /* RGBX 8:8:8:8 modes. These were once the M_LIN32 modes DOSBox mapped to 0x10F-0x11B prior to implementing M_LIN24. */
00119 { 0x210  ,M_LIN32  ,320 ,200 ,40 ,25 ,8 ,8  ,1 ,0xA0000 ,0x10000,50  ,449 ,40 ,400 , _REPEAT1 },
00120 { 0x211  ,M_LIN32  ,640 ,480 ,80 ,30 ,8 ,16 ,1 ,0xA0000 ,0x10000,100 ,525 ,80 ,480 ,0   },
00121 { 0x212  ,M_LIN32  ,800 ,600 ,100,37 ,8 ,16 ,1 ,0xA0000 ,0x10000,132 ,628 ,100,600 ,0   },
00122 { 0x214  ,M_LIN32  ,1024,768 ,128,48 ,8 ,16 ,1 ,0xA0000 ,0x10000,168 ,806 ,128,768 ,0   },
00123 
00124 { 0x215  ,M_LIN24  ,320 ,200 ,40 ,25 ,8 ,8  ,1 ,0xA0000 ,0x10000,50  ,449 ,40 ,400 , _REPEAT1 },
00125 { 0x216  ,M_LIN24  ,640 ,480 ,80 ,30 ,8 ,16 ,1 ,0xA0000 ,0x10000,100 ,525 ,80 ,480 ,0   },
00126 { 0x217  ,M_LIN24  ,800 ,600 ,100,37 ,8 ,16 ,1 ,0xA0000 ,0x10000,132 ,628 ,100,600 ,0   },
00127 { 0x218  ,M_LIN24  ,1024,768 ,128,48 ,8 ,16 ,1 ,0xA0000 ,0x10000,168 ,806 ,128,768 ,0   },
00128 
00129 /* those should be interlaced but ok */
00130 { 0x119  ,M_LIN15  ,1280,1024,160,64 ,8 ,16 ,1 ,0xA0000 ,0x10000,424 ,1066,320,1024,0   },
00131 { 0x11A  ,M_LIN16  ,1280,1024,160,64 ,8 ,16 ,1 ,0xA0000 ,0x10000,424 ,1066,320,1024,0   },
00132 
00133 { 0x11C  ,M_LIN8   ,640 ,350 ,80 ,25 ,8 ,14 ,2 ,0xA0000 ,0x10000,100 ,449 ,80 ,350 ,0   },
00134 // special mode for Birth demo by Incognita
00135 { 0x11D  ,M_LIN15  ,640 ,350 ,80 ,25 ,8 ,14 ,1 ,0xA0000 ,0x10000,200 ,449 ,160,350 ,0   },
00136 { 0x11F  ,M_LIN16  ,640 ,350 ,80 ,25 ,8 ,14 ,1 ,0xA0000 ,0x10000,200 ,449 ,160,350 ,0   },
00137 { 0x120  ,M_LIN8   ,1600,1200,200,75 ,8 ,16 ,1 ,0xA0000 ,0x10000,264 ,1240,200,1200,0   },
00138 { 0x142  ,M_LIN32  ,640 ,350 ,80 ,25 ,8 ,14 ,2 ,0xA0000 ,0x10000 ,100 ,449 ,80 ,350 ,0  },
00139 
00140 // FIXME: Find an old S3 Trio and dump the VESA modelist, then arrange this modelist to match
00141 { 0x150  ,M_LIN8   ,320 ,480 ,40 ,60 ,8 ,8  ,1 ,0xA0000 ,0x10000,100 ,525 ,80 ,480 , _S3_PIXEL_DOUBLE  },
00142 { 0x151  ,M_LIN8   ,320 ,240 ,40 ,30 ,8 ,8  ,1 ,0xA0000 ,0x10000,100 ,525 ,80 ,480 , _S3_PIXEL_DOUBLE | _REPEAT1 },
00143 { 0x152  ,M_LIN8   ,320 ,400 ,40 ,50 ,8 ,8  ,1 ,0xA0000 ,0x10000,100 ,449 ,80 ,400 , _S3_PIXEL_DOUBLE  },
00144 // For S3 Trio emulation this mode must exist as mode 0x153 else RealTech "Countdown" will crash
00145 // if you select VGA 320x200 with S3 acceleration.
00146 { 0x153  ,M_LIN8   ,320 ,200 ,40 ,25 ,8 ,8  ,1 ,0xA0000 ,0x10000,100 ,449 ,80 ,400 , _S3_PIXEL_DOUBLE | _REPEAT1 },
00147 
00148 { 0x15C ,M_LIN8,    512 ,384 ,64 ,48 ,8, 8  ,1 ,0xA0000 ,0x10000,168 ,806 ,128,768 , _S3_PIXEL_DOUBLE | _DOUBLESCAN },
00149 { 0x159 ,M_LIN8,    400 ,300 ,50 ,37 ,8 ,8  ,1 ,0xA0000 ,0x10000,132 ,628 ,100,600 , _S3_PIXEL_DOUBLE | _DOUBLESCAN },
00150 { 0x15D ,M_LIN16,   512 ,384 ,64 ,48 ,8, 16 ,1 ,0xA0000 ,0x10000,168 ,806 ,128,768 , _S3_PIXEL_DOUBLE | _DOUBLESCAN },
00151 { 0x15A ,M_LIN16,   400 ,300 ,50 ,37 ,8 ,16 ,1 ,0xA0000 ,0x10000,132 ,628 ,100,600 , _S3_PIXEL_DOUBLE | _DOUBLESCAN },
00152 
00153 { 0x160  ,M_LIN15  ,320 ,240 ,40 ,30 ,8 ,8  ,1 ,0xA0000 ,0x10000,100 ,525 , 80 ,480 , _REPEAT1 },
00154 { 0x161  ,M_LIN15  ,320 ,400 ,40 ,50 ,8 ,8  ,1 ,0xA0000 ,0x10000,100 ,449 , 80 ,400 ,0 },
00155 { 0x162  ,M_LIN15  ,320 ,480 ,40 ,60 ,8 ,8  ,1 ,0xA0000 ,0x10000,100 ,525 , 80 ,480 ,0 },
00156 { 0x165  ,M_LIN15  ,640 ,400 ,80 ,25 ,8 ,16 ,1 ,0xA0000 ,0x10000,200 ,449 ,160 ,400 ,0   },
00157 
00158 // hack: 320x200x16bpp for "Process" demo (1997) with apparently hard-coded VBE mode
00159 { 0x136  ,M_LIN16  ,320 ,240 ,40 ,30 ,8 ,8  ,1 ,0xA0000 ,0x10000,100 ,525 , 80 ,480 , _REPEAT1 },
00160 
00161 // hack: 320x480x256-color alias for Habitual demo. doing this removes the need to run S3VBE20.EXE before running the demo.
00162 //       the reason it has to be this particular video mode is because HABITUAL.EXE does not query modes, it simply assumes
00163 //       that mode 0x166 is this particular mode and errors out if it can't set it.
00164 { 0x166  ,M_LIN8   ,320 ,480 ,40 ,60 ,8 ,8  ,1 ,0xA0000 ,0x10000,100 ,525 ,80 ,480 , _S3_PIXEL_DOUBLE  },
00165 
00166 { 0x170  ,M_LIN16  ,320 ,240 ,40 ,30 ,8 ,8  ,1 ,0xA0000 ,0x10000,100 ,525 , 80 ,480 , _REPEAT1 },
00167 { 0x171  ,M_LIN16  ,320 ,400 ,40 ,50 ,8 ,8  ,1 ,0xA0000 ,0x10000,100 ,449 , 80 ,400 ,0 },
00168 { 0x172  ,M_LIN16  ,320 ,480 ,40 ,60 ,8 ,8  ,1 ,0xA0000 ,0x10000,100 ,525 , 80 ,480 ,0 },
00169 { 0x175  ,M_LIN16  ,640 ,400 ,80 ,25 ,8 ,16 ,1 ,0xA0000 ,0x10000,200 ,449 ,160 ,400 ,0   },
00170 
00171 { 0x190  ,M_LIN32  ,320 ,240 ,40 ,30 ,8 ,8  ,1 ,0xA0000 ,0x10000, 50 ,525 ,40 ,480 , _REPEAT1 },
00172 { 0x191  ,M_LIN32  ,320 ,400 ,40 ,50 ,8 ,8  ,1 ,0xA0000 ,0x10000, 50 ,449 ,40 ,400 ,0 },
00173 { 0x192  ,M_LIN32  ,320 ,480 ,40 ,60 ,8 ,8  ,1 ,0xA0000 ,0x10000, 50 ,525 ,40 ,480 ,0 },
00174 
00175 // S3 specific modes
00176 { 0x207  ,M_LIN8        ,1152,864,160,64 ,8 ,16 ,1 ,0xA0000 ,0x10000,182 ,948 ,144,864 ,0       },
00177 { 0x209  ,M_LIN15       ,1152,864,160,64 ,8 ,16 ,1 ,0xA0000 ,0x10000,364 ,948 ,288,864 ,0       },
00178 { 0x20A  ,M_LIN16       ,1152,864,160,64 ,8 ,16 ,1 ,0xA0000 ,0x10000,364 ,948 ,288,864 ,0       },
00179 { 0x20B  ,M_LIN32       ,1152, 864,160,64 ,8 ,16 ,1 ,0xA0000 ,0x10000,182 ,948 ,144,864 ,0      },
00180 { 0x213  ,M_LIN32   ,640 ,400,80 ,25 ,8 ,16 ,1 ,0xA0000 ,0x10000,100 ,449 ,80 ,400 ,0   },
00181 
00182 // Some custom modes
00183 
00184 // 720x480 3:2 modes
00185 { 0x21B  ,M_LIN4   ,720 ,480 ,90 ,30 ,8 ,16 ,1 ,0xA0000 ,0x10000,132 ,525 ,90  ,480 ,0  },
00186 { 0x21C  ,M_LIN8   ,720 ,480 ,90 ,30 ,8 ,16 ,1 ,0xA0000 ,0x10000,132 ,525 ,90  ,480 ,0  },
00187 { 0x21D  ,M_LIN15  ,720 ,480 ,90 ,30 ,8 ,16 ,1 ,0xA0000 ,0x10000,264 ,525 ,180 ,480 ,0  },
00188 { 0x21E  ,M_LIN16  ,720 ,480 ,90 ,30 ,8 ,16 ,1 ,0xA0000 ,0x10000,264 ,525 ,180 ,480 ,0  },
00189 { 0x21F  ,M_LIN32  ,720 ,480 ,90 ,30 ,8 ,16 ,1 ,0xA0000 ,0x10000,132 ,525 ,90  ,480 ,0  },
00190 
00191 // 848x480 16:9 modes
00192 { 0x220  ,M_LIN4   ,848 ,480 ,106,30 ,8 ,16 ,1 ,0xA0000 ,0x10000,132 ,525 ,106 ,480 ,0  },
00193 { 0x221  ,M_LIN8   ,848 ,480 ,106,30 ,8 ,16 ,1 ,0xA0000 ,0x10000,132 ,525 ,106 ,480 ,0  },
00194 { 0x222  ,M_LIN15  ,848 ,480 ,106,30 ,8 ,16 ,1 ,0xA0000 ,0x10000,264 ,525 ,212 ,480 ,0  },
00195 { 0x223  ,M_LIN16  ,848 ,480 ,106,30 ,8 ,16 ,1 ,0xA0000 ,0x10000,264 ,525 ,212 ,480 ,0  },
00196 { 0x224  ,M_LIN32  ,848 ,480 ,106,30 ,8 ,16 ,1 ,0xA0000 ,0x10000,132 ,525 ,106 ,480 ,0  },
00197 
00198 // 1280x800 8:5 modes
00199 { 0x225  ,M_LIN4   ,1280,800 ,160,50 ,8 ,16 ,1 ,0xA0000 ,0x10000,200 ,880 ,160 ,800 ,0  },
00200 { 0x226  ,M_LIN8   ,1280,800 ,160,50 ,8 ,16 ,1 ,0xA0000 ,0x10000,200 ,880 ,160 ,800 ,0  },
00201 { 0x227  ,M_LIN15  ,1280,800 ,160,50 ,8 ,16 ,1 ,0xA0000 ,0x10000,400 ,880 ,320 ,800 ,0  },
00202 { 0x228  ,M_LIN16  ,1280,800 ,160,50 ,8 ,16 ,1 ,0xA0000 ,0x10000,400 ,880 ,320 ,800 ,0  },
00203 { 0x229  ,M_LIN32  ,1280,800 ,160,50 ,8 ,16 ,1 ,0xA0000 ,0x10000,200 ,880 ,160 ,800 ,0  },
00204 { 0x300  ,M_LIN24  ,1280,800 ,160,50 ,8 ,16 ,1 ,0xA0000 ,0x10000,200 ,880 ,160 ,800 ,0  },
00205 
00206 // 1280x960 4:3 modes
00207 { 0x22a  ,M_LIN4   ,1280,960 ,160,60 ,8 ,16 ,1 ,0xA0000 ,0x10000,200 ,1020,160 ,960 ,0  },
00208 { 0x22b  ,M_LIN8   ,1280,960 ,160,60 ,8 ,16 ,1 ,0xA0000 ,0x10000,200 ,1020,160 ,960 ,0  },
00209 { 0x22c  ,M_LIN15  ,1280,960 ,160,60 ,8 ,16 ,1 ,0xA0000 ,0x10000,400 ,1020,320 ,960 ,0  },
00210 { 0x22d  ,M_LIN16  ,1280,960 ,160,60 ,8 ,16 ,1 ,0xA0000 ,0x10000,400 ,1020,320 ,960 ,0  },
00211 { 0x22e  ,M_LIN32  ,1280,960 ,160,60 ,8 ,16 ,1 ,0xA0000 ,0x10000,200 ,1020,160 ,960 ,0  },
00212 { 0x301  ,M_LIN24  ,1280,960 ,160,60 ,8 ,16 ,1 ,0xA0000 ,0x10000,200 ,1020,160 ,960 ,0  },
00213 
00214 // 1280x1024 5:4 rest
00215 { 0x22f  ,M_LIN32  ,1280,1024,160,64 ,8 ,16 ,1 ,0xA0000 ,0x10000,212 ,1066,160,1024,0   },
00216 { 0x302  ,M_LIN24  ,1280,1024,160,64 ,8 ,16 ,1 ,0xA0000 ,0x10000,212 ,1066,160,1024,0   },
00217 
00218 // 1400x1050 4:3 - 4bpp requires a hdisplayend value that is even, so round up
00219 { 0x250  ,M_LIN4   ,1400,1050,175,66 ,8 ,16 ,1 ,0xA0000 ,0x10000,220 ,1100,176 ,1050,0  },
00220 { 0x230  ,M_LIN8   ,1400,1050,175,66 ,8 ,16 ,1 ,0xA0000 ,0x10000,220 ,1100,175 ,1050,0  },
00221 { 0x231  ,M_LIN15  ,1400,1050,175,66 ,8 ,16 ,1 ,0xA0000 ,0x10000,440 ,1100,350 ,1050,0  },
00222 { 0x232  ,M_LIN16  ,1400,1050,175,66 ,8 ,16 ,1 ,0xA0000 ,0x10000,440 ,1100,350 ,1050,0  },
00223 { 0x233  ,M_LIN32  ,1400,1050,175,66 ,8 ,16 ,1 ,0xA0000 ,0x10000,220 ,1100,175 ,1050,0  },
00224 { 0x303  ,M_LIN24  ,1400,1050,175,66 ,8 ,16 ,1 ,0xA0000 ,0x10000,220 ,1100,175 ,1050,0  },
00225 
00226 // 1440x900 8:5 modes
00227 { 0x234  ,M_LIN4   ,1440, 900,180,56 ,8 ,16 ,1 ,0xA0000 ,0x10000,220 , 980,180 , 900,0  },
00228 { 0x235  ,M_LIN8   ,1440, 900,180,56 ,8 ,16 ,1 ,0xA0000 ,0x10000,220 , 980,180 , 900,0  },
00229 { 0x236  ,M_LIN15  ,1440, 900,180,56 ,8 ,16 ,1 ,0xA0000 ,0x10000,440 , 980,360 , 900,0  },
00230 { 0x237  ,M_LIN16  ,1440, 900,180,56 ,8 ,16 ,1 ,0xA0000 ,0x10000,440 , 980,360 , 900,0  },
00231 { 0x238  ,M_LIN32  ,1440, 900,180,56 ,8 ,16 ,1 ,0xA0000 ,0x10000,220 , 980,180 , 900,0  },
00232 
00233 // 1600x1200 4:3 rest - 32bpp needs more than 4 megs
00234 { 0x239  ,M_LIN4   ,1600,1200,200,75 ,8 ,16 ,1 ,0xA0000 ,0x10000,264 ,1240,200, 1200,0  },
00235 { 0x23a  ,M_LIN15  ,1600,1200,200,75 ,8 ,16 ,1 ,0xA0000 ,0x10000,500 ,1240,400 ,1200,0  },
00236 { 0x23b  ,M_LIN16  ,1600,1200,200,75 ,8 ,16 ,1 ,0xA0000 ,0x10000,500 ,1240,400 ,1200,0  },
00237 { 0x23c  ,M_LIN32  ,1600,1200,200,75 ,8 ,16 ,1 ,0xA0000 ,0x10000,264 ,1240,200 ,1200,0  },
00238 
00239 // 1280x720 16:9 modes
00240 { 0x23D  ,M_LIN4   ,1280,720 ,160,45 ,8 ,16 ,1 ,0xA0000 ,0x10000,176 ,792 ,160 ,720 ,0  },
00241 { 0x23E  ,M_LIN8   ,1280,720 ,160,45 ,8 ,16 ,1 ,0xA0000 ,0x10000,176 ,792 ,160 ,720 ,0  },
00242 { 0x23F  ,M_LIN15  ,1280,720 ,160,45 ,8 ,16 ,1 ,0xA0000 ,0x10000,352 ,792 ,320 ,720 ,0  },
00243 { 0x240  ,M_LIN16  ,1280,720 ,160,45 ,8 ,16 ,1 ,0xA0000 ,0x10000,352 ,792 ,320 ,720 ,0  },
00244 { 0x241  ,M_LIN32  ,1280,720 ,160,45 ,8 ,16 ,1 ,0xA0000 ,0x10000,176 ,792 ,160 ,720 ,0  },
00245 { 0x303  ,M_LIN24  ,1280,720 ,160,45 ,8 ,16 ,1 ,0xA0000 ,0x10000,176 ,792 ,160 ,720 ,0  },
00246 
00247 // 1920x1080 16:9 modes
00248 { 0x242  ,M_LIN4   ,1920,1080,240,67 ,8 ,16 ,1 ,0xA0000 ,0x10000,264 ,1188,240 ,1080,0  },
00249 { 0x243  ,M_LIN8   ,1920,1080,240,67 ,8 ,16 ,1 ,0xA0000 ,0x10000,264 ,1188,240 ,1080,0  },
00250 { 0x244  ,M_LIN15  ,1920,1080,240,67 ,8 ,16 ,1 ,0xA0000 ,0x10000,528 ,1188,480 ,1080,0  },
00251 { 0x245  ,M_LIN16  ,1920,1080,240,67 ,8 ,16 ,1 ,0xA0000 ,0x10000,528 ,1188,480 ,1080,0  },
00252 { 0x246  ,M_LIN32  ,1920,1080,240,67 ,8 ,16 ,1 ,0xA0000 ,0x10000,264 ,1188,240 ,1080,0  },
00253 { 0x304  ,M_LIN24  ,1920,1080,240,67 ,8 ,16 ,1 ,0xA0000 ,0x10000,264 ,1188,240 ,1080,0  },
00254 
00255 // 960x720 4:3 modes
00256 { 0x247  ,M_LIN4   ,960,720 ,160,45 ,8 ,16 ,1 ,0xA0000 ,0x10000,144 ,792 ,120 ,720 ,0   },
00257 { 0x248  ,M_LIN8   ,960,720 ,160,45 ,8 ,16 ,1 ,0xA0000 ,0x10000,144 ,792 ,120 ,720 ,0   },
00258 { 0x249  ,M_LIN15  ,960,720 ,160,45 ,8 ,16 ,1 ,0xA0000 ,0x10000,288 ,792 ,240 ,720 ,0  },
00259 { 0x24A  ,M_LIN16  ,960,720 ,160,45 ,8 ,16 ,1 ,0xA0000 ,0x10000,288 ,792 ,240 ,720 ,0  },
00260 { 0x24B  ,M_LIN32  ,960,720 ,160,45 ,8 ,16 ,1 ,0xA0000 ,0x10000,144 ,792 ,120 ,720 ,0  },
00261 
00262 // 1440x1080 16:9 modes
00263 { 0x24C  ,M_LIN4   ,1440,1080,240,67 ,8 ,16 ,1 ,0xA0000 ,0x10000,200 ,1188,180 ,1080,0  },
00264 { 0x24D  ,M_LIN8   ,1440,1080,240,67 ,8 ,16 ,1 ,0xA0000 ,0x10000,200 ,1188,180 ,1080,0  },
00265 { 0x24E  ,M_LIN15  ,1440,1080,240,67 ,8 ,16 ,1 ,0xA0000 ,0x10000,400 ,1188,360 ,1080,0  },
00266 { 0x24F  ,M_LIN16  ,1440,1080,240,67 ,8 ,16 ,1 ,0xA0000 ,0x10000,400 ,1188,360 ,1080,0  },
00267 { 0x2F0  ,M_LIN32  ,1440,1080,240,67 ,8 ,16 ,1 ,0xA0000 ,0x10000,200 ,1188,180 ,1080,0  },
00268 
00269 // packed 16-color (4bpp) modes seen on a Toshiba Libretto VESA BIOS (Chips & Technologies 65550)
00270 { 0x25F  ,M_PACKED4,320 ,200 ,40 ,25 ,8 ,8  ,1 ,0xA0000 ,0x10000,50  ,449 ,40  ,400 , _REPEAT1 },
00271 { 0x260  ,M_PACKED4,640 ,400 ,80 ,25 ,8 ,16 ,1 ,0xA0000 ,0x10000,100 ,449 ,80  ,400 ,0  },
00272 { 0x261  ,M_PACKED4,640 ,480 ,80 ,30 ,8 ,16 ,1 ,0xA0000 ,0x10000,100 ,525 ,80  ,480 ,0  },
00273 { 0x262  ,M_PACKED4,720 ,480 ,90 ,30 ,8 ,16 ,1 ,0xA0000 ,0x10000,132 ,525 ,90  ,480 ,0  },
00274 { 0x263  ,M_PACKED4,800 ,600 ,100,37 ,8 ,16 ,1 ,0xA0000 ,0x10000,128 ,663 ,100 ,600 ,0  },
00275 { 0x264  ,M_PACKED4,848 ,480 ,106,30 ,8 ,16 ,1 ,0xA0000 ,0x10000,132 ,525 ,106 ,480 ,0  },
00276 { 0x265  ,M_PACKED4,1024,768 ,128,48 ,8 ,16 ,1 ,0xA0000 ,0x10000,168 ,806 ,128 ,768 ,0  },
00277 { 0x266  ,M_PACKED4,1280,720 ,160,45 ,8 ,16 ,1 ,0xA0000 ,0x10000,176 ,792 ,160 ,720 ,0  },
00278 { 0x267  ,M_PACKED4,1280,1024,160,64 ,8 ,16 ,1 ,0xA0000 ,0x10000,212 ,1066,160 ,1024,0  },
00279 { 0x268  ,M_PACKED4,1440,900 ,180,56 ,8 ,16 ,1 ,0xA0000 ,0x10000,220 ,980 ,180 ,900 ,0  },
00280 { 0x269  ,M_PACKED4,1400,1050,175,66 ,8 ,16 ,1 ,0xA0000 ,0x10000,220 ,1100,176 ,1050,0  },
00281 { 0x26A  ,M_PACKED4,1600,1200,200,75 ,8 ,16 ,1 ,0xA0000 ,0x10000,264 ,1240,200 ,1200,0  },
00282 { 0x26B  ,M_PACKED4,1920,1080,240,67 ,8 ,16 ,1 ,0xA0000 ,0x10000,264 ,1188,240 ,1080,0  },
00283 
00284 {0xFFFF  ,M_ERROR  ,0   ,0   ,0  ,0  ,0 ,0  ,0 ,0x00000 ,0x0000 ,0   ,0   ,0  ,0   ,0   },
00285 };
00286 
00287 VideoModeBlock ModeList_VGA_Text_200lines[]={
00288 /* mode  ,type     ,sw  ,sh  ,tw ,th ,cw,ch ,pt,pstart  ,plength,htot,vtot,hde,vde special flags */
00289 { 0x000  ,M_TEXT   ,320 ,200 ,40 ,25 ,8 , 8 ,8 ,0xB8000 ,0x0800 ,50  ,449 ,40 ,400 ,_EGA_HALF_CLOCK | _DOUBLESCAN},
00290 { 0x001  ,M_TEXT   ,320 ,200 ,40 ,25 ,8 , 8 ,8 ,0xB8000 ,0x0800 ,50  ,449 ,40 ,400 ,_EGA_HALF_CLOCK | _DOUBLESCAN},
00291 { 0x002  ,M_TEXT   ,640 ,200 ,80 ,25 ,8 , 8 ,8 ,0xB8000 ,0x1000 ,100 ,449 ,80 ,400 ,_DOUBLESCAN },
00292 { 0x003  ,M_TEXT   ,640 ,200 ,80 ,25 ,8 , 8 ,8 ,0xB8000 ,0x1000 ,100 ,449 ,80 ,400 ,_DOUBLESCAN }
00293 };
00294 
00295 VideoModeBlock ModeList_VGA_Text_350lines[]={
00296 /* mode  ,type     ,sw  ,sh  ,tw ,th ,cw,ch ,pt,pstart  ,plength,htot,vtot,hde,vde special flags */
00297 { 0x000  ,M_TEXT   ,320 ,350 ,40 ,25 ,8 ,14 ,8 ,0xB8000 ,0x0800 ,50  ,449 ,40 ,350 ,_EGA_HALF_CLOCK     },
00298 { 0x001  ,M_TEXT   ,320 ,350 ,40 ,25 ,8 ,14 ,8 ,0xB8000 ,0x0800 ,50  ,449 ,40 ,350 ,_EGA_HALF_CLOCK     },
00299 { 0x002  ,M_TEXT   ,640 ,350 ,80 ,25 ,8 ,14 ,8 ,0xB8000 ,0x1000 ,100 ,449 ,80 ,350 ,0   },
00300 { 0x003  ,M_TEXT   ,640 ,350 ,80 ,25 ,8 ,14 ,8 ,0xB8000 ,0x1000 ,100 ,449 ,80 ,350 ,0   },
00301 { 0x007  ,M_TEXT   ,720 ,350 ,80 ,25 ,9 ,14 ,8 ,0xB0000 ,0x1000 ,100 ,449 ,80 ,350 ,0   }
00302 };
00303 
00304 VideoModeBlock ModeList_VGA_Tseng[]={
00305 /* mode  ,type     ,sw  ,sh  ,tw ,th ,cw,ch ,pt,pstart  ,plength,htot,vtot,hde,vde special flags */
00306 { 0x000  ,M_TEXT   ,360 ,400 ,40 ,25 ,9 ,16 ,8 ,0xB8000 ,0x0800 ,50  ,449 ,40 ,400 ,_EGA_HALF_CLOCK     },
00307 { 0x001  ,M_TEXT   ,360 ,400 ,40 ,25 ,9 ,16 ,8 ,0xB8000 ,0x0800 ,50  ,449 ,40 ,400 ,_EGA_HALF_CLOCK     },
00308 { 0x002  ,M_TEXT   ,720 ,400 ,80 ,25 ,9 ,16 ,8 ,0xB8000 ,0x1000 ,100 ,449 ,80 ,400 ,0   },
00309 { 0x003  ,M_TEXT   ,720 ,400 ,80 ,25 ,9 ,16 ,8 ,0xB8000 ,0x1000 ,100 ,449 ,80 ,400 ,0   },
00310 { 0x004  ,M_CGA4   ,320 ,200 ,40 ,25 ,8 ,8  ,1 ,0xB8000 ,0x4000 ,50  ,449 ,40 ,400 ,_EGA_HALF_CLOCK     | _DOUBLESCAN | _REPEAT1},
00311 { 0x005  ,M_CGA4   ,320 ,200 ,40 ,25 ,8 ,8  ,1 ,0xB8000 ,0x4000 ,50  ,449 ,40 ,400 ,_EGA_HALF_CLOCK     | _DOUBLESCAN | _REPEAT1},
00312 { 0x006  ,M_CGA2   ,640 ,200 ,80 ,25 ,8 ,8  ,1 ,0xB8000 ,0x4000 ,100 ,449 ,80 ,400 ,_DOUBLESCAN | _REPEAT1},
00313 { 0x007  ,M_TEXT   ,720 ,400 ,80 ,25 ,9 ,16 ,8 ,0xB0000 ,0x1000 ,100 ,449 ,80 ,400 ,0   },
00314 
00315 { 0x00D  ,M_EGA    ,320 ,200 ,40 ,25 ,8 ,8  ,8 ,0xA0000 ,0x2000 ,50  ,449 ,40 ,400 ,_EGA_HALF_CLOCK     | _DOUBLESCAN   },
00316 { 0x00E  ,M_EGA    ,640 ,200 ,80 ,25 ,8 ,8  ,4 ,0xA0000 ,0x4000 ,100 ,449 ,80 ,400 ,_DOUBLESCAN },
00317 { 0x00F  ,M_EGA    ,640 ,350 ,80 ,25 ,8 ,14 ,2 ,0xA0000 ,0x8000 ,100 ,449 ,80 ,350 ,0   },
00318 { 0x010  ,M_EGA    ,640 ,350 ,80 ,25 ,8 ,14 ,2 ,0xA0000 ,0x8000 ,100 ,449 ,80 ,350 ,0   },
00319 { 0x011  ,M_EGA    ,640 ,480 ,80 ,30 ,8 ,16 ,1 ,0xA0000 ,0xA000 ,100 ,525 ,80 ,480 ,0   },
00320 { 0x012  ,M_EGA    ,640 ,480 ,80 ,30 ,8 ,16 ,1 ,0xA0000 ,0xA000 ,100 ,525 ,80 ,480 ,0   },
00321 { 0x013  ,M_VGA    ,320 ,200 ,40 ,25 ,8 ,8  ,1 ,0xA0000 ,0x2000 ,100 ,449 ,80 ,400 ,_REPEAT1   },
00322 
00323 { 0x018  ,M_TEXT   ,1056 ,688, 132,44, 8, 8, 1 ,0xB0000 ,0x4000, 192, 800, 132, 704, 0 },
00324 { 0x019  ,M_TEXT   ,1056 ,400, 132,25, 8, 16,1 ,0xB0000 ,0x2000, 192, 449, 132, 400, 0 },
00325 { 0x01A  ,M_TEXT   ,1056 ,400, 132,28, 8, 16,1 ,0xB0000 ,0x2000, 192, 449, 132, 448, 0 },
00326 { 0x022  ,M_TEXT   ,1056 ,688, 132,44, 8, 8, 1 ,0xB8000 ,0x4000, 192, 800, 132, 704, 0 },
00327 { 0x023  ,M_TEXT   ,1056 ,400, 132,25, 8, 16,1 ,0xB8000 ,0x2000, 192, 449, 132, 400, 0 },
00328 { 0x024  ,M_TEXT   ,1056 ,400, 132,28, 8, 16,1 ,0xB8000 ,0x2000, 192, 449, 132, 448, 0 },
00329 { 0x025  ,M_LIN4   ,640 ,480 ,80 ,30 ,8 ,16 ,1 ,0xA0000 ,0xA000 ,100 ,525 ,80 ,480 , 0 },
00330 { 0x029  ,M_LIN4   ,800 ,600 ,100,37 ,8 ,16 ,1 ,0xA0000 ,0xA000, 128 ,663 ,100,600 , 0 },
00331 { 0x02D  ,M_LIN8   ,640 ,350 ,80 ,21 ,8 ,16 ,1 ,0xA0000 ,0x10000,100 ,449 ,80 ,350 , 0 },
00332 { 0x02E  ,M_LIN8   ,640 ,480 ,80 ,30 ,8 ,16 ,1 ,0xA0000 ,0x10000,100 ,525 ,80 ,480 , 0 },
00333 { 0x02F  ,M_LIN8   ,640 ,400 ,80 ,25 ,8 ,16 ,1 ,0xA0000 ,0x10000,100 ,449 ,80 ,400 , 0 },/* ET4000 only */
00334 { 0x030  ,M_LIN8   ,800 ,600 ,100,37 ,8 ,16 ,1 ,0xA0000 ,0x10000,128 ,663 ,100,600 , 0 },
00335 { 0x036  ,M_LIN4   ,960 , 720,120,45 ,8 ,16 ,1 ,0xA0000 ,0xA000, 120 ,800 ,120,720 , 0 },/* STB only */
00336 { 0x037  ,M_LIN4   ,1024, 768,128,48 ,8 ,16 ,1 ,0xA0000 ,0xA000, 128 ,800 ,128,768 , 0 },
00337 { 0x038  ,M_LIN8   ,1024 ,768,128,48 ,8 ,16 ,1 ,0xA0000 ,0x10000,168 ,800 ,128,768 , 0 },/* ET4000 only */
00338 { 0x03D  ,M_LIN4   ,1280,1024,160,64 ,8 ,16 ,1 ,0xA0000 ,0xA000, 160 ,1152,160,1024, 0 },/* newer ET4000 */
00339 { 0x03E  ,M_LIN4   ,1280, 960,160,60 ,8 ,16 ,1 ,0xA0000 ,0xA000, 160 ,1024,160,960 , 0 },/* Definicon only */ 
00340 { 0x06A  ,M_LIN4   ,800 ,600 ,100,37 ,8 ,16 ,1 ,0xA0000 ,0xA000, 128 ,663 ,100,600 , 0 },/* newer ET4000 */
00341 
00342 // Sierra SC1148x Hi-Color DAC modes
00343 { 0x213  ,M_LIN15  ,320 ,200 ,40 ,25 ,8 ,8  ,1 ,0xA0000 ,0x10000,100 ,449 ,80 ,400 , _VGA_PIXEL_DOUBLE | _REPEAT1 },
00344 { 0x22D  ,M_LIN15  ,640 ,350 ,80 ,25 ,8 ,14 ,1 ,0xA0000 ,0x10000,200 ,449 ,160,350 , 0 },
00345 { 0x22E  ,M_LIN15  ,640 ,480 ,80 ,30 ,8 ,16 ,1 ,0xA0000 ,0x10000,200 ,525 ,160,480 , 0 },
00346 { 0x22F  ,M_LIN15  ,640 ,400 ,80 ,25 ,8 ,16 ,1 ,0xA0000 ,0x10000,200 ,449 ,160,400 , 0 },
00347 { 0x230  ,M_LIN15  ,800 ,600 ,100,37 ,8 ,16 ,1 ,0xA0000 ,0x10000,264 ,628 ,200,600 , 0 },
00348 
00349 {0xFFFF  ,M_ERROR  ,0   ,0   ,0  ,0  ,0 ,0  ,0 ,0x00000 ,0x0000 ,0   ,0   ,0  ,0   ,0   },
00350 };
00351 
00352 VideoModeBlock ModeList_VGA_Paradise[]={
00353 /* mode  ,type     ,sw  ,sh  ,tw ,th ,cw,ch ,pt,pstart  ,plength,htot,vtot,hde,vde special flags */
00354 { 0x000  ,M_TEXT   ,360 ,400 ,40 ,25 ,9 ,16 ,8 ,0xB8000 ,0x0800 ,50  ,449 ,40 ,400 ,_EGA_HALF_CLOCK     },
00355 { 0x001  ,M_TEXT   ,360 ,400 ,40 ,25 ,9 ,16 ,8 ,0xB8000 ,0x0800 ,50  ,449 ,40 ,400 ,_EGA_HALF_CLOCK     },
00356 { 0x002  ,M_TEXT   ,720 ,400 ,80 ,25 ,9 ,16 ,8 ,0xB8000 ,0x1000 ,100 ,449 ,80 ,400 ,0   },
00357 { 0x003  ,M_TEXT   ,720 ,400 ,80 ,25 ,9 ,16 ,8 ,0xB8000 ,0x1000 ,100 ,449 ,80 ,400 ,0   },
00358 { 0x004  ,M_CGA4   ,320 ,200 ,40 ,25 ,8 ,8  ,1 ,0xB8000 ,0x4000 ,50  ,449 ,40 ,400 ,_EGA_HALF_CLOCK     | _DOUBLESCAN | _REPEAT1},
00359 { 0x005  ,M_CGA4   ,320 ,200 ,40 ,25 ,8 ,8  ,1 ,0xB8000 ,0x4000 ,50  ,449 ,40 ,400 ,_EGA_HALF_CLOCK     | _DOUBLESCAN | _REPEAT1},
00360 { 0x006  ,M_CGA2   ,640 ,200 ,80 ,25 ,8 ,8  ,1 ,0xB8000 ,0x4000 ,100 ,449 ,80 ,400 ,_DOUBLESCAN | _REPEAT1},
00361 { 0x007  ,M_TEXT   ,720 ,400 ,80 ,25 ,9 ,16 ,8 ,0xB0000 ,0x1000 ,100 ,449 ,80 ,400 ,0   },
00362 
00363 { 0x00D  ,M_EGA    ,320 ,200 ,40 ,25 ,8 ,8  ,8 ,0xA0000 ,0x2000 ,50  ,449 ,40 ,400 ,_EGA_HALF_CLOCK     | _DOUBLESCAN   },
00364 { 0x00E  ,M_EGA    ,640 ,200 ,80 ,25 ,8 ,8  ,4 ,0xA0000 ,0x4000 ,100 ,449 ,80 ,400 ,_DOUBLESCAN },
00365 { 0x00F  ,M_EGA    ,640 ,350 ,80 ,25 ,8 ,14 ,2 ,0xA0000 ,0x8000 ,100 ,449 ,80 ,350 ,0   },
00366 { 0x010  ,M_EGA    ,640 ,350 ,80 ,25 ,8 ,14 ,2 ,0xA0000 ,0x8000 ,100 ,449 ,80 ,350 ,0   },
00367 { 0x011  ,M_EGA    ,640 ,480 ,80 ,30 ,8 ,16 ,1 ,0xA0000 ,0xA000 ,100 ,525 ,80 ,480 ,0   },
00368 { 0x012  ,M_EGA    ,640 ,480 ,80 ,30 ,8 ,16 ,1 ,0xA0000 ,0xA000 ,100 ,525 ,80 ,480 ,0   },
00369 { 0x013  ,M_VGA    ,320 ,200 ,40 ,25 ,8 ,8  ,1 ,0xA0000 ,0x2000 ,100 ,449 ,80 ,400 ,_REPEAT1 },
00370 
00371 { 0x054  ,M_TEXT   ,1056 ,688, 132,43, 8, 9, 1, 0xB0000, 0x4000, 192, 720, 132,688, 0 },
00372 { 0x055  ,M_TEXT   ,1056 ,400, 132,25, 8, 16,1, 0xB0000, 0x2000, 192, 449, 132,400, 0 },
00373 { 0x056  ,M_TEXT   ,1056 ,688, 132,43, 8, 9, 1, 0xB0000, 0x4000, 192, 720, 132,688, 0 },
00374 { 0x057  ,M_TEXT   ,1056 ,400, 132,25, 8, 16,1, 0xB0000, 0x2000, 192, 449, 132,400, 0 },
00375 { 0x058  ,M_LIN4   ,800 , 600, 100,37, 8, 16,1, 0xA0000, 0xA000, 128 ,663 ,100,600, 0 },
00376 { 0x05C  ,M_LIN8   ,800 , 600 ,100,37 ,8 ,16,1 ,0xA0000 ,0x10000,128 ,663 ,100,600, 0 },
00377 { 0x05D  ,M_LIN4   ,1024, 768, 128,48 ,8, 16,1, 0xA0000, 0x10000,128 ,800 ,128,768 ,0 }, // documented only on C00 upwards
00378 { 0x05E  ,M_LIN8   ,640 , 400, 80 ,25, 8, 16,1, 0xA0000, 0x10000,100 ,449 ,80 ,400, 0 },
00379 { 0x05F  ,M_LIN8   ,640 , 480, 80 ,30, 8, 16,1, 0xA0000, 0x10000,100 ,525 ,80 ,480, 0 },
00380 
00381 {0xFFFF  ,M_ERROR  ,0   ,0   ,0  ,0  ,0 ,0  ,0 ,0x00000 ,0x0000 ,0   ,0   ,0  ,0   ,0   },
00382 };
00383 
00384 /* NTS: I will *NOT* set the double scanline flag for 200 line modes.
00385  *      The modes listed here are intended to reflect the actual raster sent to the EGA monitor,
00386  *      not what you think looks better. EGA as far as I know, is either sent a 200-line mode,
00387  *      or a 350-line mode. There is no VGA-line 200 to 400 line doubling. */
00388 VideoModeBlock ModeList_EGA[]={
00389 /* mode  ,type     ,sw  ,sh  ,tw ,th ,cw,ch ,pt,pstart  ,plength,htot,vtot,hde,vde special flags */
00390 { 0x000  ,M_TEXT   ,320 ,350 ,40 ,25 ,8 ,14 ,8 ,0xB8000 ,0x0800 ,50  ,366 ,40 ,350 ,_EGA_HALF_CLOCK     },
00391 { 0x001  ,M_TEXT   ,320 ,350 ,40 ,25 ,8 ,14 ,8 ,0xB8000 ,0x0800 ,50  ,366 ,40 ,350 ,_EGA_HALF_CLOCK     },
00392 { 0x002  ,M_TEXT   ,640 ,350 ,80 ,25 ,8 ,14 ,8 ,0xB8000 ,0x1000 ,96  ,366 ,80 ,350 ,0   },
00393 { 0x003  ,M_TEXT   ,640 ,350 ,80 ,25 ,8 ,14 ,8 ,0xB8000 ,0x1000 ,96  ,366 ,80 ,350 ,0   },
00394 { 0x004  ,M_CGA4   ,320 ,200 ,40 ,25 ,8 ,8  ,1 ,0xB8000 ,0x4000 ,60  ,262 ,40 ,200 ,_EGA_HALF_CLOCK     | _REPEAT1},
00395 { 0x005  ,M_CGA4   ,320 ,200 ,40 ,25 ,8 ,8  ,1 ,0xB8000 ,0x4000 ,60  ,262 ,40 ,200 ,_EGA_HALF_CLOCK     | _REPEAT1},
00396 { 0x006  ,M_CGA2   ,640 ,200 ,80 ,25 ,8 ,8  ,1 ,0xB8000 ,0x4000 ,117 ,262 ,80 ,200 ,_REPEAT1},
00397 { 0x007  ,M_TEXT   ,720 ,350 ,80 ,25 ,9 ,14 ,8 ,0xB0000 ,0x1000 ,101 ,370 ,80 ,350 ,0   },
00398 
00399 { 0x00D  ,M_EGA    ,320 ,200 ,40 ,25 ,8 ,8  ,8 ,0xA0000 ,0x2000 ,60  ,262 ,40 ,200 ,_EGA_HALF_CLOCK     },
00400 { 0x00E  ,M_EGA    ,640 ,200 ,80 ,25 ,8 ,8  ,4 ,0xA0000 ,0x4000 ,117 ,262 ,80 ,200 ,0 },
00401 { 0x00F  ,M_EGA    ,640 ,350 ,80 ,25 ,8 ,14 ,2 ,0xA0000 ,0x8000 ,101 ,370 ,80 ,350 ,0   },
00402 { 0x010  ,M_EGA    ,640 ,350 ,80 ,25 ,8 ,14 ,2 ,0xA0000 ,0x8000 ,96  ,366 ,80 ,350 ,0   },
00403 
00404 {0xFFFF  ,M_ERROR  ,0   ,0   ,0  ,0  ,0 ,0  ,0 ,0x00000 ,0x0000 ,0   ,0   ,0  ,0   ,0   },
00405 };
00406 
00407 VideoModeBlock ModeList_OTHER[]={
00408 /* mode  ,type     ,sw  ,sh  ,tw ,th ,cw,ch ,pt,pstart  ,plength,htot,vtot,hde,vde ,special flags */
00409 { 0x000  ,M_TEXT   ,320 ,400 ,40 ,25 ,8 ,8  ,8 ,0xB8000 ,0x0800 ,56  ,31  ,40 ,25  ,0   },
00410 { 0x001  ,M_TEXT   ,320 ,400 ,40 ,25 ,8 ,8  ,8 ,0xB8000 ,0x0800 ,56  ,31  ,40 ,25  ,0   },
00411 { 0x002  ,M_TEXT   ,640 ,400 ,80 ,25 ,8 ,8  ,4 ,0xB8000 ,0x1000 ,113 ,31  ,80 ,25  ,0   },
00412 { 0x003  ,M_TEXT   ,640 ,400 ,80 ,25 ,8 ,8  ,4 ,0xB8000 ,0x1000 ,113 ,31  ,80 ,25  ,0   },
00413 { 0x004  ,M_CGA4   ,320 ,200 ,40 ,25 ,8 ,8  ,4 ,0xB8000 ,0x0800 ,56  ,127 ,40 ,100 ,0   },
00414 { 0x005  ,M_CGA4   ,320 ,200 ,40 ,25 ,8 ,8  ,4 ,0xB8000 ,0x0800 ,56  ,127 ,40 ,100 ,0   },
00415 { 0x006  ,M_CGA2   ,640 ,200 ,80 ,25 ,8 ,8  ,4 ,0xB8000 ,0x0800 ,56  ,127 ,40 ,100 ,0   },
00416 { 0x008  ,M_TANDY16,160 ,200 ,20 ,25 ,8 ,8  ,8 ,0xB8000 ,0x2000 ,56  ,127 ,40 ,100 ,0   },
00417 { 0x009  ,M_TANDY16,320 ,200 ,40 ,25 ,8 ,8  ,8 ,0xB8000 ,0x2000 ,113 ,63  ,80 ,50  ,0   },
00418 { 0x00A  ,M_CGA4   ,640 ,200 ,80 ,25 ,8 ,8  ,8 ,0xB8000 ,0x2000 ,113 ,63  ,80 ,50  ,0   },
00419 //{ 0x00E  ,M_TANDY16,640 ,200 ,80 ,25 ,8 ,8  ,8 ,0xA0000 ,0x10000 ,113 ,256 ,80 ,200 ,0   },
00420 {0xFFFF  ,M_ERROR  ,0   ,0   ,0  ,0  ,0 ,0  ,0 ,0x00000 ,0x0000 ,0   ,0   ,0  ,0   ,0   },
00421 };
00422 
00423 /* MCGA mode list.
00424  * These are based off of a register capture of actual MCGA hardware for each mode.
00425  * According to register captures, all modes seem to be consistently programmed as if
00426  * for 40x25 CGA modes, including 80x25 modes.
00427  *
00428  * These modes should generally make a 70Hz VGA compatible output, except 640x480 2-color MCGA
00429  * mode, which should make a 60Hz VGA compatible mode.
00430  *
00431  * Register values are CGA-like, meaning that the modes are defined in character clocks
00432  * horizontally and character cells vertically and the actual scan line numbers are determined
00433  * by the vertical param times max scanline.
00434  *
00435  * According to the register dump I made, vertical total values don't fully make sense and
00436  * may be nonsensical and handled differently for emulation purposes. They're weird.
00437  *
00438  * When I can figure out which ones are directly handled, doubled, or just ignored, I can
00439  * update this table and the emulation to match it.
00440  *
00441  * Until then, this is close enough. */
00442 VideoModeBlock ModeList_MCGA[]={
00443 /* mode  ,type     ,sw  ,sh  ,tw ,th ,cw,ch ,pt,pstart  ,plength,htot,vtot,hde,vde ,special flags */
00444 { 0x000  ,M_TEXT   ,320 ,400 ,40 ,25 ,8 ,16 ,8 ,0xB8000 ,0x0800 ,49  ,26  ,40 ,25  ,0   },
00445 { 0x001  ,M_TEXT   ,320 ,400 ,40 ,25 ,8 ,16 ,8 ,0xB8000 ,0x0800 ,49  ,26  ,40 ,25  ,0   },
00446 { 0x002  ,M_TEXT   ,640 ,400 ,80 ,25 ,8 ,16 ,8 ,0xB8000 ,0x1000 ,49  ,26  ,40 ,25  ,0   },
00447 { 0x003  ,M_TEXT   ,640 ,400 ,80 ,25 ,8 ,16 ,8 ,0xB8000 ,0x1000 ,49  ,26  ,40 ,25  ,0   },
00448 { 0x004  ,M_CGA4   ,320 ,200 ,40 ,25 ,8 ,8  ,1 ,0xB8000 ,0x4000 ,49  ,108 ,40 ,100 ,0   },
00449 { 0x005  ,M_CGA4   ,320 ,200 ,40 ,25 ,8 ,8  ,1 ,0xB8000 ,0x4000 ,49  ,108 ,40 ,100 ,0   },
00450 { 0x006  ,M_CGA2   ,640 ,200 ,80 ,25 ,8 ,8  ,1 ,0xB8000 ,0x4000 ,49  ,108 ,40 ,100 ,0   },
00451 { 0x011  ,M_CGA2   ,640 ,480 ,80 ,30 ,8 ,16 ,1 ,0xA0000 ,0xA000 ,49  ,127 ,40 ,120 ,0   }, // note 1
00452 { 0x013  ,M_VGA    ,320 ,200 ,40 ,25 ,8 ,8  ,1 ,0xA0000 ,0x2000 ,49  ,108 ,40 ,100 ,0   }, // note 1
00453 {0xFFFF  ,M_ERROR  ,0   ,0   ,0  ,0  ,0 ,0  ,0 ,0x00000 ,0x0000 ,0   ,0   ,0  ,0   ,0   },
00454 };
00455 // note 1: CGA-like 200-line vertical timing is programmed into the registers, and then the
00456 //         hardware doubles them again. The max scanline row is zero in these modes, so
00457 //         doubling twice is the only way it could work.
00458 
00459 VideoModeBlock Hercules_Mode=
00460 { 0x007  ,M_TEXT   ,640 ,400 ,80 ,25 ,8 ,14 ,1 ,0xB0000 ,0x1000 ,97 ,25  ,80 ,25  ,0    };
00461 
00462 VideoModeBlock PC98_Mode=
00463 { 0x000  ,M_PC98   ,640 ,400 ,80 ,25 ,8 ,14 ,1 ,0xA0000 ,0x1000 ,97 ,25  ,80 ,25  ,0    };
00464 
00465 static Bit8u text_palette[64][3]=
00466 {
00467   {0x00,0x00,0x00},{0x00,0x00,0x2a},{0x00,0x2a,0x00},{0x00,0x2a,0x2a},{0x2a,0x00,0x00},{0x2a,0x00,0x2a},{0x2a,0x2a,0x00},{0x2a,0x2a,0x2a},
00468   {0x00,0x00,0x15},{0x00,0x00,0x3f},{0x00,0x2a,0x15},{0x00,0x2a,0x3f},{0x2a,0x00,0x15},{0x2a,0x00,0x3f},{0x2a,0x2a,0x15},{0x2a,0x2a,0x3f},
00469   {0x00,0x15,0x00},{0x00,0x15,0x2a},{0x00,0x3f,0x00},{0x00,0x3f,0x2a},{0x2a,0x15,0x00},{0x2a,0x15,0x2a},{0x2a,0x3f,0x00},{0x2a,0x3f,0x2a},
00470   {0x00,0x15,0x15},{0x00,0x15,0x3f},{0x00,0x3f,0x15},{0x00,0x3f,0x3f},{0x2a,0x15,0x15},{0x2a,0x15,0x3f},{0x2a,0x3f,0x15},{0x2a,0x3f,0x3f},
00471   {0x15,0x00,0x00},{0x15,0x00,0x2a},{0x15,0x2a,0x00},{0x15,0x2a,0x2a},{0x3f,0x00,0x00},{0x3f,0x00,0x2a},{0x3f,0x2a,0x00},{0x3f,0x2a,0x2a},
00472   {0x15,0x00,0x15},{0x15,0x00,0x3f},{0x15,0x2a,0x15},{0x15,0x2a,0x3f},{0x3f,0x00,0x15},{0x3f,0x00,0x3f},{0x3f,0x2a,0x15},{0x3f,0x2a,0x3f},
00473   {0x15,0x15,0x00},{0x15,0x15,0x2a},{0x15,0x3f,0x00},{0x15,0x3f,0x2a},{0x3f,0x15,0x00},{0x3f,0x15,0x2a},{0x3f,0x3f,0x00},{0x3f,0x3f,0x2a},
00474   {0x15,0x15,0x15},{0x15,0x15,0x3f},{0x15,0x3f,0x15},{0x15,0x3f,0x3f},{0x3f,0x15,0x15},{0x3f,0x15,0x3f},{0x3f,0x3f,0x15},{0x3f,0x3f,0x3f}
00475 };
00476 
00477 static Bit8u mtext_palette[64][3]=
00478 {
00479   {0x00,0x00,0x00},{0x00,0x00,0x00},{0x00,0x00,0x00},{0x00,0x00,0x00},{0x00,0x00,0x00},{0x00,0x00,0x00},{0x00,0x00,0x00},{0x00,0x00,0x00},
00480   {0x2a,0x2a,0x2a},{0x2a,0x2a,0x2a},{0x2a,0x2a,0x2a},{0x2a,0x2a,0x2a},{0x2a,0x2a,0x2a},{0x2a,0x2a,0x2a},{0x2a,0x2a,0x2a},{0x2a,0x2a,0x2a},
00481   {0x00,0x00,0x00},{0x00,0x00,0x00},{0x00,0x00,0x00},{0x00,0x00,0x00},{0x00,0x00,0x00},{0x00,0x00,0x00},{0x00,0x00,0x00},{0x00,0x00,0x00},
00482   {0x3f,0x3f,0x3f},{0x3f,0x3f,0x3f},{0x3f,0x3f,0x3f},{0x3f,0x3f,0x3f},{0x3f,0x3f,0x3f},{0x3f,0x3f,0x3f},{0x3f,0x3f,0x3f},{0x3f,0x3f,0x3f},
00483   {0x00,0x00,0x00},{0x00,0x00,0x00},{0x00,0x00,0x00},{0x00,0x00,0x00},{0x00,0x00,0x00},{0x00,0x00,0x00},{0x00,0x00,0x00},{0x00,0x00,0x00},
00484   {0x2a,0x2a,0x2a},{0x2a,0x2a,0x2a},{0x2a,0x2a,0x2a},{0x2a,0x2a,0x2a},{0x2a,0x2a,0x2a},{0x2a,0x2a,0x2a},{0x2a,0x2a,0x2a},{0x2a,0x2a,0x2a},
00485   {0x00,0x00,0x00},{0x00,0x00,0x00},{0x00,0x00,0x00},{0x00,0x00,0x00},{0x00,0x00,0x00},{0x00,0x00,0x00},{0x00,0x00,0x00},{0x00,0x00,0x00},
00486   {0x3f,0x3f,0x3f},{0x3f,0x3f,0x3f},{0x3f,0x3f,0x3f},{0x3f,0x3f,0x3f},{0x3f,0x3f,0x3f},{0x3f,0x3f,0x3f},{0x3f,0x3f,0x3f},{0x3f,0x3f,0x3f} 
00487 };
00488 
00489 static Bit8u mtext_s3_palette[64][3]=
00490 {
00491   {0x00,0x00,0x00},{0x00,0x00,0x00},{0x00,0x00,0x00},{0x00,0x00,0x00},{0x00,0x00,0x00},{0x00,0x00,0x00},{0x00,0x00,0x00},{0x00,0x00,0x00},
00492   {0x2a,0x2a,0x2a},{0x2a,0x2a,0x2a},{0x2a,0x2a,0x2a},{0x2a,0x2a,0x2a},{0x2a,0x2a,0x2a},{0x2a,0x2a,0x2a},{0x2a,0x2a,0x2a},{0x2a,0x2a,0x2a},
00493   {0x2a,0x2a,0x2a},{0x2a,0x2a,0x2a},{0x2a,0x2a,0x2a},{0x2a,0x2a,0x2a},{0x2a,0x2a,0x2a},{0x2a,0x2a,0x2a},{0x2a,0x2a,0x2a},{0x2a,0x2a,0x2a},
00494   {0x3f,0x3f,0x3f},{0x3f,0x3f,0x3f},{0x3f,0x3f,0x3f},{0x3f,0x3f,0x3f},{0x3f,0x3f,0x3f},{0x3f,0x3f,0x3f},{0x3f,0x3f,0x3f},{0x3f,0x3f,0x3f},
00495   {0x00,0x00,0x00},{0x00,0x00,0x00},{0x00,0x00,0x00},{0x00,0x00,0x00},{0x00,0x00,0x00},{0x00,0x00,0x00},{0x00,0x00,0x00},{0x00,0x00,0x00},
00496   {0x2a,0x2a,0x2a},{0x2a,0x2a,0x2a},{0x2a,0x2a,0x2a},{0x2a,0x2a,0x2a},{0x2a,0x2a,0x2a},{0x2a,0x2a,0x2a},{0x2a,0x2a,0x2a},{0x2a,0x2a,0x2a},
00497   {0x2a,0x2a,0x2a},{0x2a,0x2a,0x2a},{0x2a,0x2a,0x2a},{0x2a,0x2a,0x2a},{0x2a,0x2a,0x2a},{0x2a,0x2a,0x2a},{0x2a,0x2a,0x2a},{0x2a,0x2a,0x2a},
00498   {0x3f,0x3f,0x3f},{0x3f,0x3f,0x3f},{0x3f,0x3f,0x3f},{0x3f,0x3f,0x3f},{0x3f,0x3f,0x3f},{0x3f,0x3f,0x3f},{0x3f,0x3f,0x3f},{0x3f,0x3f,0x3f} 
00499 };
00500 
00501 static Bit8u ega_palette[64][3]=
00502 {
00503   {0x00,0x00,0x00}, {0x00,0x00,0x2a}, {0x00,0x2a,0x00}, {0x00,0x2a,0x2a}, {0x2a,0x00,0x00}, {0x2a,0x00,0x2a}, {0x2a,0x15,0x00}, {0x2a,0x2a,0x2a},
00504   {0x00,0x00,0x00}, {0x00,0x00,0x2a}, {0x00,0x2a,0x00}, {0x00,0x2a,0x2a}, {0x2a,0x00,0x00}, {0x2a,0x00,0x2a}, {0x2a,0x15,0x00}, {0x2a,0x2a,0x2a},
00505   {0x15,0x15,0x15}, {0x15,0x15,0x3f}, {0x15,0x3f,0x15}, {0x15,0x3f,0x3f}, {0x3f,0x15,0x15}, {0x3f,0x15,0x3f}, {0x3f,0x3f,0x15}, {0x3f,0x3f,0x3f},
00506   {0x15,0x15,0x15}, {0x15,0x15,0x3f}, {0x15,0x3f,0x15}, {0x15,0x3f,0x3f}, {0x3f,0x15,0x15}, {0x3f,0x15,0x3f}, {0x3f,0x3f,0x15}, {0x3f,0x3f,0x3f},
00507   {0x00,0x00,0x00}, {0x00,0x00,0x2a}, {0x00,0x2a,0x00}, {0x00,0x2a,0x2a}, {0x2a,0x00,0x00}, {0x2a,0x00,0x2a}, {0x2a,0x15,0x00}, {0x2a,0x2a,0x2a},
00508   {0x00,0x00,0x00}, {0x00,0x00,0x2a}, {0x00,0x2a,0x00}, {0x00,0x2a,0x2a}, {0x2a,0x00,0x00}, {0x2a,0x00,0x2a}, {0x2a,0x15,0x00}, {0x2a,0x2a,0x2a},
00509   {0x15,0x15,0x15}, {0x15,0x15,0x3f}, {0x15,0x3f,0x15}, {0x15,0x3f,0x3f}, {0x3f,0x15,0x15}, {0x3f,0x15,0x3f}, {0x3f,0x3f,0x15}, {0x3f,0x3f,0x3f},
00510   {0x15,0x15,0x15}, {0x15,0x15,0x3f}, {0x15,0x3f,0x15}, {0x15,0x3f,0x3f}, {0x3f,0x15,0x15}, {0x3f,0x15,0x3f}, {0x3f,0x3f,0x15}, {0x3f,0x3f,0x3f}
00511 };
00512 
00513 static Bit8u cga_palette[16][3]=
00514 {
00515         {0x00,0x00,0x00}, {0x00,0x00,0x2a}, {0x00,0x2a,0x00}, {0x00,0x2a,0x2a}, {0x2a,0x00,0x00}, {0x2a,0x00,0x2a}, {0x2a,0x15,0x00}, {0x2a,0x2a,0x2a},
00516         {0x15,0x15,0x15}, {0x15,0x15,0x3f}, {0x15,0x3f,0x15}, {0x15,0x3f,0x3f}, {0x3f,0x15,0x15}, {0x3f,0x15,0x3f}, {0x3f,0x3f,0x15}, {0x3f,0x3f,0x3f},
00517 };
00518 
00519 static Bit8u cga_palette_2[64][3]=
00520 {
00521         {0x00,0x00,0x00}, {0x00,0x00,0x2a}, {0x00,0x2a,0x00}, {0x00,0x2a,0x2a}, {0x2a,0x00,0x00}, {0x2a,0x00,0x2a}, {0x2a,0x15,0x00}, {0x2a,0x2a,0x2a},
00522         {0x00,0x00,0x00}, {0x00,0x00,0x2a}, {0x00,0x2a,0x00}, {0x00,0x2a,0x2a}, {0x2a,0x00,0x00}, {0x2a,0x00,0x2a}, {0x2a,0x15,0x00}, {0x2a,0x2a,0x2a},
00523         {0x15,0x15,0x15}, {0x15,0x15,0x3f}, {0x15,0x3f,0x15}, {0x15,0x3f,0x3f}, {0x3f,0x15,0x15}, {0x3f,0x15,0x3f}, {0x3f,0x3f,0x15}, {0x3f,0x3f,0x3f},
00524         {0x15,0x15,0x15}, {0x15,0x15,0x3f}, {0x15,0x3f,0x15}, {0x15,0x3f,0x3f}, {0x3f,0x15,0x15}, {0x3f,0x15,0x3f}, {0x3f,0x3f,0x15}, {0x3f,0x3f,0x3f},
00525         {0x00,0x00,0x00}, {0x00,0x00,0x2a}, {0x00,0x2a,0x00}, {0x00,0x2a,0x2a}, {0x2a,0x00,0x00}, {0x2a,0x00,0x2a}, {0x2a,0x15,0x00}, {0x2a,0x2a,0x2a},
00526         {0x00,0x00,0x00}, {0x00,0x00,0x2a}, {0x00,0x2a,0x00}, {0x00,0x2a,0x2a}, {0x2a,0x00,0x00}, {0x2a,0x00,0x2a}, {0x2a,0x15,0x00}, {0x2a,0x2a,0x2a},
00527         {0x15,0x15,0x15}, {0x15,0x15,0x3f}, {0x15,0x3f,0x15}, {0x15,0x3f,0x3f}, {0x3f,0x15,0x15}, {0x3f,0x15,0x3f}, {0x3f,0x3f,0x15}, {0x3f,0x3f,0x3f},
00528         {0x15,0x15,0x15}, {0x15,0x15,0x3f}, {0x15,0x3f,0x15}, {0x15,0x3f,0x3f}, {0x3f,0x15,0x15}, {0x3f,0x15,0x3f}, {0x3f,0x3f,0x15}, {0x3f,0x3f,0x3f},
00529 };
00530 
00531 static Bit8u vga_palette[248][3]=
00532 {
00533   {0x00,0x00,0x00},{0x00,0x00,0x2a},{0x00,0x2a,0x00},{0x00,0x2a,0x2a},{0x2a,0x00,0x00},{0x2a,0x00,0x2a},{0x2a,0x15,0x00},{0x2a,0x2a,0x2a},
00534   {0x15,0x15,0x15},{0x15,0x15,0x3f},{0x15,0x3f,0x15},{0x15,0x3f,0x3f},{0x3f,0x15,0x15},{0x3f,0x15,0x3f},{0x3f,0x3f,0x15},{0x3f,0x3f,0x3f},
00535   {0x00,0x00,0x00},{0x05,0x05,0x05},{0x08,0x08,0x08},{0x0b,0x0b,0x0b},{0x0e,0x0e,0x0e},{0x11,0x11,0x11},{0x14,0x14,0x14},{0x18,0x18,0x18},
00536   {0x1c,0x1c,0x1c},{0x20,0x20,0x20},{0x24,0x24,0x24},{0x28,0x28,0x28},{0x2d,0x2d,0x2d},{0x32,0x32,0x32},{0x38,0x38,0x38},{0x3f,0x3f,0x3f},
00537   {0x00,0x00,0x3f},{0x10,0x00,0x3f},{0x1f,0x00,0x3f},{0x2f,0x00,0x3f},{0x3f,0x00,0x3f},{0x3f,0x00,0x2f},{0x3f,0x00,0x1f},{0x3f,0x00,0x10},
00538   {0x3f,0x00,0x00},{0x3f,0x10,0x00},{0x3f,0x1f,0x00},{0x3f,0x2f,0x00},{0x3f,0x3f,0x00},{0x2f,0x3f,0x00},{0x1f,0x3f,0x00},{0x10,0x3f,0x00},
00539   {0x00,0x3f,0x00},{0x00,0x3f,0x10},{0x00,0x3f,0x1f},{0x00,0x3f,0x2f},{0x00,0x3f,0x3f},{0x00,0x2f,0x3f},{0x00,0x1f,0x3f},{0x00,0x10,0x3f},
00540   {0x1f,0x1f,0x3f},{0x27,0x1f,0x3f},{0x2f,0x1f,0x3f},{0x37,0x1f,0x3f},{0x3f,0x1f,0x3f},{0x3f,0x1f,0x37},{0x3f,0x1f,0x2f},{0x3f,0x1f,0x27},
00541 
00542   {0x3f,0x1f,0x1f},{0x3f,0x27,0x1f},{0x3f,0x2f,0x1f},{0x3f,0x37,0x1f},{0x3f,0x3f,0x1f},{0x37,0x3f,0x1f},{0x2f,0x3f,0x1f},{0x27,0x3f,0x1f},
00543   {0x1f,0x3f,0x1f},{0x1f,0x3f,0x27},{0x1f,0x3f,0x2f},{0x1f,0x3f,0x37},{0x1f,0x3f,0x3f},{0x1f,0x37,0x3f},{0x1f,0x2f,0x3f},{0x1f,0x27,0x3f},
00544   {0x2d,0x2d,0x3f},{0x31,0x2d,0x3f},{0x36,0x2d,0x3f},{0x3a,0x2d,0x3f},{0x3f,0x2d,0x3f},{0x3f,0x2d,0x3a},{0x3f,0x2d,0x36},{0x3f,0x2d,0x31},
00545   {0x3f,0x2d,0x2d},{0x3f,0x31,0x2d},{0x3f,0x36,0x2d},{0x3f,0x3a,0x2d},{0x3f,0x3f,0x2d},{0x3a,0x3f,0x2d},{0x36,0x3f,0x2d},{0x31,0x3f,0x2d},
00546   {0x2d,0x3f,0x2d},{0x2d,0x3f,0x31},{0x2d,0x3f,0x36},{0x2d,0x3f,0x3a},{0x2d,0x3f,0x3f},{0x2d,0x3a,0x3f},{0x2d,0x36,0x3f},{0x2d,0x31,0x3f},
00547   {0x00,0x00,0x1c},{0x07,0x00,0x1c},{0x0e,0x00,0x1c},{0x15,0x00,0x1c},{0x1c,0x00,0x1c},{0x1c,0x00,0x15},{0x1c,0x00,0x0e},{0x1c,0x00,0x07},
00548   {0x1c,0x00,0x00},{0x1c,0x07,0x00},{0x1c,0x0e,0x00},{0x1c,0x15,0x00},{0x1c,0x1c,0x00},{0x15,0x1c,0x00},{0x0e,0x1c,0x00},{0x07,0x1c,0x00},
00549   {0x00,0x1c,0x00},{0x00,0x1c,0x07},{0x00,0x1c,0x0e},{0x00,0x1c,0x15},{0x00,0x1c,0x1c},{0x00,0x15,0x1c},{0x00,0x0e,0x1c},{0x00,0x07,0x1c},
00550 
00551   {0x0e,0x0e,0x1c},{0x11,0x0e,0x1c},{0x15,0x0e,0x1c},{0x18,0x0e,0x1c},{0x1c,0x0e,0x1c},{0x1c,0x0e,0x18},{0x1c,0x0e,0x15},{0x1c,0x0e,0x11},
00552   {0x1c,0x0e,0x0e},{0x1c,0x11,0x0e},{0x1c,0x15,0x0e},{0x1c,0x18,0x0e},{0x1c,0x1c,0x0e},{0x18,0x1c,0x0e},{0x15,0x1c,0x0e},{0x11,0x1c,0x0e},
00553   {0x0e,0x1c,0x0e},{0x0e,0x1c,0x11},{0x0e,0x1c,0x15},{0x0e,0x1c,0x18},{0x0e,0x1c,0x1c},{0x0e,0x18,0x1c},{0x0e,0x15,0x1c},{0x0e,0x11,0x1c},
00554   {0x14,0x14,0x1c},{0x16,0x14,0x1c},{0x18,0x14,0x1c},{0x1a,0x14,0x1c},{0x1c,0x14,0x1c},{0x1c,0x14,0x1a},{0x1c,0x14,0x18},{0x1c,0x14,0x16},
00555   {0x1c,0x14,0x14},{0x1c,0x16,0x14},{0x1c,0x18,0x14},{0x1c,0x1a,0x14},{0x1c,0x1c,0x14},{0x1a,0x1c,0x14},{0x18,0x1c,0x14},{0x16,0x1c,0x14},
00556   {0x14,0x1c,0x14},{0x14,0x1c,0x16},{0x14,0x1c,0x18},{0x14,0x1c,0x1a},{0x14,0x1c,0x1c},{0x14,0x1a,0x1c},{0x14,0x18,0x1c},{0x14,0x16,0x1c},
00557   {0x00,0x00,0x10},{0x04,0x00,0x10},{0x08,0x00,0x10},{0x0c,0x00,0x10},{0x10,0x00,0x10},{0x10,0x00,0x0c},{0x10,0x00,0x08},{0x10,0x00,0x04},
00558   {0x10,0x00,0x00},{0x10,0x04,0x00},{0x10,0x08,0x00},{0x10,0x0c,0x00},{0x10,0x10,0x00},{0x0c,0x10,0x00},{0x08,0x10,0x00},{0x04,0x10,0x00},
00559 
00560   {0x00,0x10,0x00},{0x00,0x10,0x04},{0x00,0x10,0x08},{0x00,0x10,0x0c},{0x00,0x10,0x10},{0x00,0x0c,0x10},{0x00,0x08,0x10},{0x00,0x04,0x10},
00561   {0x08,0x08,0x10},{0x0a,0x08,0x10},{0x0c,0x08,0x10},{0x0e,0x08,0x10},{0x10,0x08,0x10},{0x10,0x08,0x0e},{0x10,0x08,0x0c},{0x10,0x08,0x0a},
00562   {0x10,0x08,0x08},{0x10,0x0a,0x08},{0x10,0x0c,0x08},{0x10,0x0e,0x08},{0x10,0x10,0x08},{0x0e,0x10,0x08},{0x0c,0x10,0x08},{0x0a,0x10,0x08},
00563   {0x08,0x10,0x08},{0x08,0x10,0x0a},{0x08,0x10,0x0c},{0x08,0x10,0x0e},{0x08,0x10,0x10},{0x08,0x0e,0x10},{0x08,0x0c,0x10},{0x08,0x0a,0x10},
00564   {0x0b,0x0b,0x10},{0x0c,0x0b,0x10},{0x0d,0x0b,0x10},{0x0f,0x0b,0x10},{0x10,0x0b,0x10},{0x10,0x0b,0x0f},{0x10,0x0b,0x0d},{0x10,0x0b,0x0c},
00565   {0x10,0x0b,0x0b},{0x10,0x0c,0x0b},{0x10,0x0d,0x0b},{0x10,0x0f,0x0b},{0x10,0x10,0x0b},{0x0f,0x10,0x0b},{0x0d,0x10,0x0b},{0x0c,0x10,0x0b},
00566   {0x0b,0x10,0x0b},{0x0b,0x10,0x0c},{0x0b,0x10,0x0d},{0x0b,0x10,0x0f},{0x0b,0x10,0x10},{0x0b,0x0f,0x10},{0x0b,0x0d,0x10},{0x0b,0x0c,0x10}
00567 };
00568 VideoModeBlock * CurMode = NULL;
00569 
00570 static bool SetCurMode(VideoModeBlock modeblock[],Bit16u mode) {
00571         Bitu i=0;
00572         while (modeblock[i].mode!=0xffff) {
00573                 if (modeblock[i].mode!=mode)
00574                         i++;
00575                 /* Hack for VBE 1.2 modes and 24/32bpp ambiguity UNLESS the user changed the mode */
00576                 else if (modeblock[i].mode >= 0x100 && modeblock[i].mode <= 0x11F &&
00577             !(modeblock[i].special & _USER_MODIFIED) &&
00578                         ((modeblock[i].type == M_LIN32 && !vesa12_modes_32bpp) ||
00579                         (modeblock[i].type == M_LIN24 && vesa12_modes_32bpp))) {
00580                         /* ignore */
00581                         i++;
00582                 }
00583         /* ignore deleted modes */
00584         else if (modeblock[i].type == M_ERROR) {
00585             /* ignore */
00586             i++;
00587         }
00588             /* ignore disabled modes */
00589         else if (modeblock[i].special & _USER_DISABLED) {
00590             /* ignore */
00591             i++;
00592         }
00593                 else {
00594                         if ((!int10.vesa_oldvbe) || (ModeList_VGA[i].mode<0x120)) {
00595                                 CurMode=&modeblock[i];
00596                                 return true;
00597                         }
00598                         return false;
00599                 }
00600         }
00601         return false;
00602 }
00603 
00604 bool INT10_SetCurMode(void) {
00605         bool mode_changed=false;
00606         Bit16u bios_mode=(Bit16u)real_readb(BIOSMEM_SEG,BIOSMEM_CURRENT_MODE);
00607         if (CurMode == NULL || CurMode->mode != bios_mode) {
00608                 switch (machine) {
00609                 case MCH_CGA:
00610                         if (bios_mode<7) mode_changed=SetCurMode(ModeList_OTHER,bios_mode);
00611                         break;
00612                 case MCH_MCGA:
00613                         mode_changed=SetCurMode(ModeList_MCGA,bios_mode);
00614                         break;
00615                 case TANDY_ARCH_CASE:
00616                         if (bios_mode!=7 && bios_mode<=0xa) mode_changed=SetCurMode(ModeList_OTHER,bios_mode);
00617                         break;
00618                 case MCH_MDA:
00619                 case MCH_HERC:
00620                         break;
00621                 case MCH_EGA:
00622                         mode_changed=SetCurMode(ModeList_EGA,bios_mode);
00623                         break;
00624                 case VGA_ARCH_CASE:
00625                         switch (svgaCard) {
00626                         case SVGA_TsengET4K:
00627                         case SVGA_TsengET3K:
00628                                 mode_changed=SetCurMode(ModeList_VGA_Tseng,bios_mode);
00629                                 break;
00630                         case SVGA_ParadisePVGA1A:
00631                                 mode_changed=SetCurMode(ModeList_VGA_Paradise,bios_mode);
00632                                 break;
00633                         case SVGA_S3Trio:
00634                                 if (bios_mode>=0x68 && CurMode->mode==(bios_mode+0x98)) break;
00635                         default:
00636                                 mode_changed=SetCurMode(ModeList_VGA,bios_mode);
00637                                 break;
00638                         }
00639                         if (mode_changed && bios_mode<=3) {
00640                                 switch (real_readb(BIOSMEM_SEG,BIOSMEM_MODESET_CTL)&0x90) {
00641                                 case 0x00:
00642                                         CurMode=&ModeList_VGA_Text_350lines[bios_mode];
00643                                         break;
00644                                 case 0x80:
00645                                         CurMode=&ModeList_VGA_Text_200lines[bios_mode];
00646                                         break;
00647                                 }
00648                         }
00649                         break;
00650                 default:
00651                         break;
00652                 }
00653         }
00654         return mode_changed;
00655 }
00656 
00657 static void FinishSetMode(bool clearmem) {
00658         /* Clear video memory if needs be */
00659         if (clearmem) {
00660                 switch (CurMode->type) {
00661                 case M_CGA4:
00662                 case M_CGA2:
00663                 case M_TANDY16:
00664             if (machine == MCH_MCGA && CurMode->mode == 0x11) {
00665                 for (Bit16u ct=0;ct<32*1024;ct++) {
00666                     real_writew( 0xa000,ct*2,0x0000);
00667                 }
00668             }
00669             else {
00670                 for (Bit16u ct=0;ct<16*1024;ct++) {
00671                     real_writew( 0xb800,ct*2,0x0000);
00672                 }
00673             }
00674                         break;
00675                 case M_TEXT: {
00676                         Bit16u max = (CurMode->ptotal*CurMode->plength)>>1;
00677                         if (CurMode->mode == 7) {
00678                                 for (Bit16u ct=0;ct<max;ct++) real_writew(0xB000,ct*2,0x0720);
00679                         }
00680                         else {
00681                                 for (Bit16u ct=0;ct<max;ct++) real_writew(0xB800,ct*2,0x0720);
00682                         }
00683                         break;
00684                 }
00685                 case M_EGA:     
00686                 case M_VGA:
00687                 case M_LIN8:
00688                 case M_LIN4:
00689                 case M_LIN15:
00690                 case M_LIN16:
00691                 case M_LIN24:
00692                 case M_LIN32:
00693         case M_PACKED4:
00694                         /* Hack we just access the memory directly */
00695                         memset(vga.mem.linear,0,vga.mem.memsize);
00696                         break;
00697                 default:
00698                         break;
00699                 }
00700         }
00701         /* Setup the BIOS */
00702         if (CurMode->mode<128) real_writeb(BIOSMEM_SEG,BIOSMEM_CURRENT_MODE,(Bit8u)CurMode->mode);
00703         else real_writeb(BIOSMEM_SEG,BIOSMEM_CURRENT_MODE,(Bit8u)(CurMode->mode-0x98)); //Looks like the s3 bios
00704         real_writew(BIOSMEM_SEG,BIOSMEM_NB_COLS,(Bit16u)CurMode->twidth);
00705         real_writew(BIOSMEM_SEG,BIOSMEM_PAGE_SIZE,(Bit16u)CurMode->plength);
00706         real_writew(BIOSMEM_SEG,BIOSMEM_CRTC_ADDRESS,((CurMode->mode==7 )|| (CurMode->mode==0x0f)) ? 0x3b4 : 0x3d4);
00707         real_writeb(BIOSMEM_SEG,BIOSMEM_NB_ROWS,(Bit8u)(CurMode->theight-1));
00708         real_writew(BIOSMEM_SEG,BIOSMEM_CHAR_HEIGHT,(Bit16u)CurMode->cheight);
00709         real_writeb(BIOSMEM_SEG,BIOSMEM_VIDEO_CTL,(0x60|(clearmem?0:0x80)));
00710         real_writeb(BIOSMEM_SEG,BIOSMEM_SWITCHES,0x09);
00711 
00712         // this is an index into the dcc table:
00713         if (IS_VGA_ARCH) real_writeb(BIOSMEM_SEG,BIOSMEM_DCC_INDEX,0x0b);
00714         real_writed(BIOSMEM_SEG,BIOSMEM_VS_POINTER,int10.rom.video_save_pointers);
00715 
00716         // Set cursor shape
00717         if (CurMode->type==M_TEXT) {
00718                 INT10_SetCursorShape(CURSOR_SCAN_LINE_NORMAL, CURSOR_SCAN_LINE_END);
00719         }
00720         // Set cursor pos for page 0..7
00721         for (Bit8u ct=0;ct<8;ct++) INT10_SetCursorPos(0,0,ct);
00722         // Set active page 0
00723         INT10_SetActivePage(0);
00724         /* Set some interrupt vectors */
00725         if (CurMode->mode<=3 || CurMode->mode==7) {
00726                 RealSetVec(0x43,int10.rom.font_8_first);
00727         } else {
00728                 switch (CurMode->cheight) {
00729                 case 8:RealSetVec(0x43,int10.rom.font_8_first);break;
00730                 case 14:RealSetVec(0x43,int10.rom.font_14);break;
00731                 case 16:RealSetVec(0x43,int10.rom.font_16);break;
00732                 }
00733         }
00734         /* FIXME */
00735         VGA_DAC_UpdateColorPalette();
00736         /* Tell mouse resolution change */
00737         Mouse_NewVideoMode();
00738 }
00739 
00740 extern bool en_int33;
00741 
00742 bool INT10_SetVideoMode_OTHER(Bit16u mode,bool clearmem) {
00743         switch (machine) {
00744         case MCH_CGA:
00745         case MCH_AMSTRAD:
00746                 if (mode>6) return false;
00747         case TANDY_ARCH_CASE:
00748                 if (mode>0xa) return false;
00749                 if (mode==7) mode=0; // PCJR defaults to 0 on illegal mode 7
00750                 if (!SetCurMode(ModeList_OTHER,mode)) {
00751                         LOG(LOG_INT10,LOG_ERROR)("Trying to set illegal mode %X",mode);
00752                         return false;
00753                 }
00754                 break;
00755         case MCH_MCGA:
00756         if (!SetCurMode(ModeList_MCGA,mode)) {
00757             LOG(LOG_INT10,LOG_ERROR)("Trying to set illegal mode %X",mode);
00758             return false;
00759         }
00760         break;
00761     case MCH_MDA:
00762     case MCH_HERC:
00763                 // Only init the adapter if the equipment word is set to monochrome (Testdrive)
00764                 if ((real_readw(BIOSMEM_SEG,BIOSMEM_INITIAL_MODE)&0x30)!=0x30) return false;
00765                 CurMode=&Hercules_Mode;
00766                 mode=7; // in case the video parameter table is modified
00767                 break;
00768         default:
00769                 break;
00770         }
00771         LOG(LOG_INT10,LOG_NORMAL)("Set Video Mode %X",mode);
00772 
00773         /* Setup the CRTC */
00774         Bitu crtc_base=(machine==MCH_HERC || machine==MCH_MDA) ? 0x3b4 : 0x3d4;
00775         //Horizontal total
00776         IO_WriteW(crtc_base,0x00 | (CurMode->htotal) << 8);
00777         //Horizontal displayed
00778         IO_WriteW(crtc_base,0x01 | (CurMode->hdispend) << 8);
00779         //Horizontal sync position
00780         IO_WriteW(crtc_base,0x02 | (CurMode->hdispend+1) << 8);
00781         //Horizontal sync width, seems to be fixed to 0xa, for cga at least, hercules has 0xf
00782         // PCjr doubles sync width in high resolution modes, good for aspect correction
00783         // newer "compatible" CGA BIOS does the same
00784         // The IBM CGA card seems to limit retrace pulse widths
00785         Bitu syncwidth;
00786         if(machine==MCH_HERC || machine==MCH_MDA) syncwidth = 0xf;
00787         else if(CurMode->hdispend==80) syncwidth = 0xc;
00788         else syncwidth = 0x6;
00789         
00790         IO_WriteW(crtc_base,0x03 | (syncwidth) << 8);
00792         IO_WriteW(crtc_base,0x04 | (CurMode->vtotal) << 8);
00793         //Vertical total adjust, 6 for cga,hercules,tandy
00794         IO_WriteW(crtc_base,0x05 | (6) << 8);
00795         //Vertical displayed
00796         IO_WriteW(crtc_base,0x06 | (CurMode->vdispend) << 8);
00797         //Vertical sync position
00798         IO_WriteW(crtc_base,0x07 | (CurMode->vdispend + ((CurMode->vtotal - CurMode->vdispend)/2)-1) << 8);
00799         //Maximum scanline
00800         Bit8u scanline,crtpage;
00801         scanline=8;
00802         switch(CurMode->type) {
00803         case M_TEXT: // text mode character height
00804                 if (machine==MCH_HERC || machine==MCH_MDA) scanline=14;
00805                 else scanline=8;
00806                 break;
00807         case M_CGA2: // graphics mode: even/odd banks interleaved
00808         if (machine == MCH_MCGA && CurMode->mode >= 0x11)
00809                 scanline=1; // as seen on real hardware, modes 0x11 and 0x13 have max scanline register == 0x00
00810         else
00811                 scanline=2;
00812                 break;
00813         case M_VGA: // MCGA
00814         if (machine == MCH_MCGA)
00815                 scanline=1; // as seen on real hardware, modes 0x11 and 0x13 have max scanline register == 0x00
00816         else
00817                 scanline=2;
00818                 break;
00819         case M_CGA4:
00820                 if (CurMode->mode!=0xa) scanline=2;
00821                 else scanline=4;
00822                 break;
00823         case M_TANDY16:
00824                 if (CurMode->mode!=0x9) scanline=2;
00825                 else scanline=4;
00826                 break;
00827         default:
00828                 break;
00829         }
00830 
00831     if (machine == MCH_MCGA) {
00832         IO_Write(0x3c8,0);
00833         for (unsigned int i=0;i<248;i++) {
00834             IO_Write(0x3c9,vga_palette[i][0]);
00835             IO_Write(0x3c9,vga_palette[i][1]);
00836             IO_Write(0x3c9,vga_palette[i][2]);
00837         }
00838                 IO_Write(0x3c6,0xff); //Reset Pelmask
00839     }
00840 
00841         IO_WriteW(crtc_base,0x09 | (scanline-1u) << 8u);
00842         //Setup the CGA palette using VGA DAC palette
00843         for (Bit8u ct=0;ct<16;ct++) VGA_DAC_SetEntry(ct,cga_palette[ct][0],cga_palette[ct][1],cga_palette[ct][2]);
00844         //Setup the tandy palette
00845         for (Bit8u ct=0;ct<16;ct++) VGA_DAC_CombineColor(ct,ct);
00846         //Setup the special registers for each machine type
00847         Bit8u mode_control_list[0xa+1]={
00848                 0x2c,0x28,0x2d,0x29,    //0-3
00849                 0x2a,0x2e,0x1e,0x29,    //4-7
00850                 0x2a,0x2b,0x3b                  //8-a
00851         };
00852         Bit8u mode_control_list_pcjr[0xa+1]={
00853                 0x0c,0x08,0x0d,0x09,    //0-3
00854                 0x0a,0x0e,0x0e,0x09,    //4-7           
00855                 0x1a,0x1b,0x0b                  //8-a
00856         };
00857         Bit8u mode_control,color_select;
00858         switch (machine) {
00859         case MCH_MDA:
00860         case MCH_HERC:
00861                 IO_WriteB(0x3b8,0x28);  // TEXT mode and blinking characters
00862 
00863                 Herc_Palette();
00864                 VGA_DAC_CombineColor(0,0);
00865 
00866                 real_writeb(BIOSMEM_SEG,BIOSMEM_CURRENT_MSR,0x29); // attribute controls blinking
00867                 break;
00868         case MCH_AMSTRAD:
00869                 IO_WriteB( 0x3d9, 0x0f );
00870         case MCH_CGA:
00871         case MCH_MCGA:
00872         if (CurMode->mode == 0x13 && machine == MCH_MCGA)
00873             mode_control=0x0a;
00874         else if (CurMode->mode == 0x11 && machine == MCH_MCGA)
00875             mode_control=0x1e;
00876         else if (CurMode->mode < sizeof(mode_control_list))
00877             mode_control=mode_control_list[CurMode->mode];
00878         else
00879             mode_control=0x00;
00880 
00881                 if (CurMode->mode == 0x6) color_select=0x3f;
00882         else if (CurMode->mode == 0x11) color_select=0x3f;
00883                 else color_select=0x30;
00884                 IO_WriteB(0x3d8,mode_control);
00885                 IO_WriteB(0x3d9,color_select);
00886                 real_writeb(BIOSMEM_SEG,BIOSMEM_CURRENT_MSR,mode_control);
00887                 real_writeb(BIOSMEM_SEG,BIOSMEM_CURRENT_PAL,color_select);
00888                 if (mono_cga) Mono_CGA_Palette();
00889 
00890         if (machine == MCH_MCGA) {
00891             unsigned char mcga_mode = 0x10;
00892 
00893             if (CurMode->type == M_VGA)
00894                 mcga_mode |= 0x01;//320x200 256-color
00895             else if (CurMode->type == M_CGA2 && CurMode->sheight > 240)
00896                 mcga_mode |= 0x02;//640x480 2-color
00897 
00898             /* real hardware: BIOS sets the "hardware computes horizontal timings" bits for mode 0-3 */
00899             if (CurMode->mode <= 0x03)
00900                 mcga_mode |= 0x08;//hardware computes horizontal timing
00901 
00902             /* real hardware: unknown bit 2 is set for all modes except 640x480 2-color */
00903             if (CurMode->mode != 0x11)
00904                 mcga_mode |= 0x04;//unknown bit?
00905 
00906             /* real hardware: unknown bit 5 if set for all 640-wide modes */
00907             if (CurMode->swidth >= 500)
00908                 mcga_mode |= 0x20;//unknown bit?
00909 
00910             IO_WriteW(crtc_base,0x10 | (mcga_mode) << 8);
00911         }
00912                 break;
00913         case MCH_TANDY:
00914                 /* Init some registers */
00915                 IO_WriteB(0x3da,0x1);IO_WriteB(0x3de,0xf);              //Palette mask always 0xf
00916                 IO_WriteB(0x3da,0x2);IO_WriteB(0x3de,0x0);              //black border
00917                 IO_WriteB(0x3da,0x3);                                                   //Tandy color overrides?
00918                 switch (CurMode->mode) {
00919                 case 0x8:       
00920                         IO_WriteB(0x3de,0x14);break;
00921                 case 0x9:
00922                         IO_WriteB(0x3de,0x14);break;
00923                 case 0xa:
00924                         IO_WriteB(0x3de,0x0c);break;
00925                 default:
00926                         IO_WriteB(0x3de,0x0);break;
00927                 }
00928                 // write palette
00929                 for(Bitu i = 0; i < 16; i++) {
00930                         IO_WriteB(0x3da,i+0x10);
00931                         IO_WriteB(0x3de,i);
00932                 }
00933                 //Clear extended mapping
00934                 IO_WriteB(0x3da,0x5);
00935                 IO_WriteB(0x3de,0x0);
00936                 //Clear monitor mode
00937                 IO_WriteB(0x3da,0x8);
00938                 IO_WriteB(0x3de,0x0);
00939                 crtpage=(CurMode->mode>=0x9) ? 0xf6 : 0x3f;
00940                 IO_WriteB(0x3df,crtpage);
00941                 real_writeb(BIOSMEM_SEG,BIOSMEM_CRTCPU_PAGE,crtpage);
00942                 mode_control=mode_control_list[CurMode->mode];
00943                 if (CurMode->mode == 0x6 || CurMode->mode==0xa) color_select=0x3f;
00944                 else color_select=0x30;
00945                 IO_WriteB(0x3d8,mode_control);
00946                 IO_WriteB(0x3d9,color_select);
00947                 real_writeb(BIOSMEM_SEG,BIOSMEM_CURRENT_MSR,mode_control);
00948                 real_writeb(BIOSMEM_SEG,BIOSMEM_CURRENT_PAL,color_select);
00949                 break;
00950         case MCH_PCJR:
00951                 /* Init some registers */
00952                 IO_ReadB(0x3da);
00953                 IO_WriteB(0x3da,0x1);IO_WriteB(0x3da,0xf);              //Palette mask always 0xf
00954                 IO_WriteB(0x3da,0x2);IO_WriteB(0x3da,0x0);              //black border
00955                 IO_WriteB(0x3da,0x3);
00956                 if (CurMode->mode<=0x04) IO_WriteB(0x3da,0x02);
00957                 else if (CurMode->mode==0x06) IO_WriteB(0x3da,0x08);
00958                 else IO_WriteB(0x3da,0x00);
00959 
00960                 /* set CRT/Processor page register */
00961                 if (CurMode->mode<0x04) crtpage=0x3f;
00962                 else if (CurMode->mode>=0x09) crtpage=0xf6;
00963                 else crtpage=0x7f;
00964                 IO_WriteB(0x3df,crtpage);
00965                 real_writeb(BIOSMEM_SEG,BIOSMEM_CRTCPU_PAGE,crtpage);
00966 
00967                 mode_control=mode_control_list_pcjr[CurMode->mode];
00968                 IO_WriteB(0x3da,0x0);IO_WriteB(0x3da,mode_control);
00969                 real_writeb(BIOSMEM_SEG,BIOSMEM_CURRENT_MSR,mode_control);
00970 
00971                 if (CurMode->mode == 0x6 || CurMode->mode==0xa) color_select=0x3f;
00972                 else color_select=0x30;
00973                 real_writeb(BIOSMEM_SEG,BIOSMEM_CURRENT_PAL,color_select);
00974                 INT10_SetColorSelect(1);
00975                 INT10_SetBackgroundBorder(0);
00976                 break;
00977         default:
00978                 break;
00979         }
00980 
00981         // Check if the program wants us to use a custom mode table
00982         RealPt vparams = RealGetVec(0x1d);
00983         if (vparams != 0 && (vparams != BIOS_VIDEO_TABLE_LOCATION) && (mode < 8)) {
00984                 // load crtc parameters from video params table
00985                 Bit16u crtc_block_index = 0;
00986                 if (mode < 2) crtc_block_index = 0;
00987                 else if (mode < 4) crtc_block_index = 1;
00988                 else if (mode < 7) crtc_block_index = 2;
00989                 else if (mode == 7) crtc_block_index = 3; // MDA mono mode; invalid for others
00990                 else if (mode < 9) crtc_block_index = 2;
00991                 else crtc_block_index = 3; // Tandy/PCjr modes
00992 
00993                 // init CRTC registers
00994                 for (Bit16u i = 0; i < 16; i++)
00995                         IO_WriteW(crtc_base, (uint16_t)(i | (real_readb(RealSeg(vparams), 
00996                                 RealOff(vparams) + i + crtc_block_index*16) << 8)));
00997         }
00998         FinishSetMode(clearmem);
00999 
01000         if (en_int33) INT10_SetCurMode();
01001 
01002         return true;
01003 }
01004 
01005 bool unmask_irq0_on_int10_setmode = true;
01006 
01007 bool INT10_SetVideoMode(Bit16u mode) {
01008         //LOG_MSG("set mode %x",mode);
01009         bool clearmem=true;Bitu i;
01010         if (mode>=0x100) {
01011                 if ((mode & 0x4000) && int10.vesa_nolfb) return false;
01012                 if (mode & 0x8000) clearmem=false;
01013                 mode&=0xfff;
01014         }
01015         if ((mode<0x100) && (mode & 0x80)) {
01016                 clearmem=false;
01017                 mode-=0x80;
01018         }
01019 
01020     if (unmask_irq0_on_int10_setmode) {
01021         /* setting the video mode unmasks certain IRQs as a matter of course */
01022         PIC_SetIRQMask(0,false); /* Enable system timer */
01023     }
01024 
01025         int10.vesa_setmode=0xffff;
01026         LOG(LOG_INT10,LOG_NORMAL)("Set Video Mode %X",mode);
01027         if (!IS_EGAVGA_ARCH) return INT10_SetVideoMode_OTHER(mode,clearmem);
01028 
01029         /* First read mode setup settings from bios area */
01030 //      Bit8u video_ctl=real_readb(BIOSMEM_SEG,BIOSMEM_VIDEO_CTL);
01031 //      Bit8u vga_switches=real_readb(BIOSMEM_SEG,BIOSMEM_SWITCHES);
01032         Bit8u modeset_ctl=real_readb(BIOSMEM_SEG,BIOSMEM_MODESET_CTL);
01033 
01034         if (IS_VGA_ARCH) {
01035                 if (svga.accepts_mode) {
01036                         if (!svga.accepts_mode(mode)) return false;
01037                 }
01038 
01039                 switch(svgaCard) {
01040                 case SVGA_TsengET4K:
01041                 case SVGA_TsengET3K:
01042                         if (!SetCurMode(ModeList_VGA_Tseng,mode)){
01043                                 LOG(LOG_INT10,LOG_ERROR)("VGA:Trying to set illegal mode %X",mode);
01044                                 return false;
01045                         }
01046                         break;
01047                 case SVGA_ParadisePVGA1A:
01048                         if (!SetCurMode(ModeList_VGA_Paradise,mode)){
01049                                 LOG(LOG_INT10,LOG_ERROR)("VGA:Trying to set illegal mode %X",mode);
01050                                 return false;
01051                         }
01052                         break;
01053                 default:
01054                         if (!SetCurMode(ModeList_VGA,mode)){
01055                                 LOG(LOG_INT10,LOG_ERROR)("VGA:Trying to set illegal mode %X",mode);
01056                                 return false;
01057                         }
01058                 }
01059                 // check for scanline backwards compatibility (VESA text modes??)
01060                 if (CurMode->type==M_TEXT) {
01061                         if ((modeset_ctl&0x90)==0x80) { // 200 lines emulation
01062                                 if (CurMode->mode <= 3) {
01063                                         CurMode = &ModeList_VGA_Text_200lines[CurMode->mode];
01064                                 }
01065                         } else if ((modeset_ctl&0x90)==0x00) { // 350 lines emulation
01066                                 if (CurMode->mode <= 3) {
01067                                         CurMode = &ModeList_VGA_Text_350lines[CurMode->mode];
01068                                 }
01069                         }
01070                 }
01071         } else {
01072                 if (!SetCurMode(ModeList_EGA,mode)){
01073                         LOG(LOG_INT10,LOG_ERROR)("EGA:Trying to set illegal mode %X",mode);
01074                         return false;
01075                 }
01076         }
01077 
01078         /* Setup the VGA to the correct mode */
01079         // turn off video
01080         IO_Write(0x3c4,0); IO_Write(0x3c5,1); // reset
01081         IO_Write(0x3c4,1); IO_Write(0x3c5,0x20); // screen off
01082 
01083         Bit16u crtc_base;
01084         bool mono_mode=(mode == 7) || (mode==0xf);  
01085         if (mono_mode) crtc_base=0x3b4;
01086         else crtc_base=0x3d4;
01087 
01088         /* Setup MISC Output Register */
01089         Bit8u misc_output=0x2 | (mono_mode ? 0x0 : 0x1);
01090 
01091         if (machine==MCH_EGA) {
01092                 // 16MHz clock for 350-line EGA modes except mode F
01093                 if ((CurMode->vdispend==350) && (mode!=0xf)) misc_output|=0x4;
01094         } else {
01095                 // 28MHz clock for 9-pixel wide chars
01096                 if ((CurMode->type==M_TEXT) && (CurMode->cwidth==9)) misc_output|=0x4;
01097         }
01098 
01099         switch (CurMode->vdispend) {
01100         case 400: 
01101                 misc_output|=0x60;
01102                 break;
01103         case 480:
01104                 misc_output|=0xe0;
01105                 break;
01106         case 350:
01107                 misc_output|=0xa0;
01108                 break;
01109         case 200:
01110         default:
01111                 misc_output|=0x20;
01112         }
01113         IO_Write(0x3c2,misc_output);            //Setup for 3b4 or 3d4
01114         
01115         if (IS_VGA_ARCH && (svgaCard == SVGA_S3Trio)) {
01116         // unlock the S3 registers
01117                 IO_Write(crtc_base,0x38);IO_Write(crtc_base+1u,0x48);   //Register lock 1
01118                 IO_Write(crtc_base,0x39);IO_Write(crtc_base+1u,0xa5);   //Register lock 2
01119                 IO_Write(0x3c4,0x8);IO_Write(0x3c5,0x06);
01120                 // Disable MMIO here so we can read / write memory
01121                 IO_Write(crtc_base,0x53);IO_Write(crtc_base+1u,0x0);
01122         }
01123         
01124         /* Program Sequencer */
01125         Bit8u seq_data[SEQ_REGS];
01126         memset(seq_data,0,SEQ_REGS);
01127         
01128         seq_data[0] = 0x3;      // not reset
01129         seq_data[1] = 0x21;     // screen still disabled, will be enabled at end of setmode
01130         seq_data[4] = 0x04;     // odd/even disable
01131         
01132         if (CurMode->special & _EGA_HALF_CLOCK) seq_data[1]|=0x08; //Check for half clock
01133         if ((machine==MCH_EGA) && (CurMode->special & _EGA_HALF_CLOCK)) seq_data[1]|=0x02;
01134 
01135         if (IS_VGA_ARCH || (IS_EGA_ARCH && vga.mem.memsize >= 0x20000))
01136         seq_data[4]|=0x02;      //More than 64kb
01137     else if (IS_EGA_ARCH && CurMode->vdispend==350) {
01138         seq_data[4] &= ~0x04; // turn on odd/even
01139         seq_data[1] |= 0x04; // half clock
01140     }
01141 
01142         switch (CurMode->type) {
01143         case M_TEXT:
01144                 if (CurMode->cwidth==9) seq_data[1] &= ~1;
01145                 seq_data[2]|=0x3;                               //Enable plane 0 and 1
01146                 seq_data[4]|=0x01;                              //Alpanumeric
01147                 seq_data[4]&=~0x04;                             //odd/even enable
01148                 break;
01149         case M_CGA2:
01150                 if (IS_EGAVGA_ARCH) {
01151                         seq_data[2]|=0x1;                       //Enable plane 0. Most VGA cards treat it as a 640x200 variant of the MCGA 2-color mode, with bit 13 remapped for interlace
01152                 }
01153                 break;
01154         case M_CGA4:
01155                 if (IS_EGAVGA_ARCH) {
01156                         seq_data[2]|=0x3;                       //Enable plane 0 and 1
01157                         seq_data[4]&=~0x04;                     //odd/even enable
01158                 }
01159                 break;
01160         case M_LIN4:
01161         case M_EGA:
01162                 seq_data[2]|=0xf;                               //Enable all planes for writing
01163                 break;
01164         case M_LIN8:                                            //Seems to have the same reg layout from testing
01165         case M_LIN15:
01166         case M_LIN16:
01167         case M_LIN24:
01168         case M_LIN32:
01169     case M_PACKED4:
01170         case M_VGA:
01171                 seq_data[2]|=0xf;                               //Enable all planes for writing
01172                 seq_data[4]|=0x8;                               //Graphics - Chained
01173                 break;
01174         default:
01175                 break;
01176         }
01177         for (Bit8u ct=0;ct<SEQ_REGS;ct++) {
01178                 IO_Write(0x3c4,ct);
01179                 IO_Write(0x3c5,seq_data[ct]);
01180         }
01181 
01182         /* NTS: S3 INT 10 modesetting code below sets this bit anyway when writing CRTC register 0x31.
01183          *      It needs to be done as I/O port write so that Windows 95 can virtualize it properly when
01184          *      we're called to set INT10 mode 3 (from within virtual 8086 mode) when opening a DOS box.
01185          *
01186          *      If we just set it directly, then the generic S3 driver in Windows 95 cannot trap the I/O
01187          *      and prevent our own INT 10h handler from setting the VGA memory mapping into "compatible
01188          *      chain 4" mode, and then any non accelerated drawing from the Windows driver becomes a
01189          *      garbled mess spread out across the screen (due to the weird way that VGA planar memory
01190          *      is "chained" on SVGA chipsets).
01191          *
01192          *      The S3 linear framebuffer isn't affected by VGA chained mode, which is why only the
01193          *      generic S3 driver was affected by this bug, since the generic S3 driver is the one that
01194          *      uses only VGA access (0xA0000-0xAFFFF) and SVGA bank switching while the more specific
01195          *      "S3 Trio32 PCI" driver uses the linear framebuffer.
01196          *
01197          *      But to avoid breaking other SVGA emulation in DOSBox-X, we still set this manually for
01198          *      other VGA/SVGA emulation cases, just not S3 Trio emulation. */
01199         if (svgaCard != SVGA_S3Trio)
01200                 vga.config.compatible_chain4 = true; // this may be changed by SVGA chipset emulation
01201 
01202         if( machine==MCH_AMSTRAD )
01203         {
01204                 vga.amstrad.mask_plane = 0x07070707;
01205                 vga.amstrad.write_plane = 0x0F;
01206                 vga.amstrad.read_plane = 0x00;
01207                 vga.amstrad.border_color = 0x00;
01208         }
01209 
01210         /* Program CRTC */
01211         /* First disable write protection */
01212         IO_Write(crtc_base,0x11);
01213         IO_Write(crtc_base+1u,IO_Read(crtc_base+1u)&0x7f);
01214         /* Clear all the regs */
01215         for (Bit8u ct=0x0;ct<=0x18;ct++) {
01216                 IO_Write(crtc_base,ct);IO_Write(crtc_base+1u,0);
01217         }
01218         Bit8u overflow=0;Bit8u max_scanline=0;
01219         Bit8u ver_overflow=0;Bit8u hor_overflow=0;
01220         /* Horizontal Total */
01221         IO_Write(crtc_base,0x00);IO_Write(crtc_base+1u,(Bit8u)(CurMode->htotal-5));
01222         hor_overflow|=((CurMode->htotal-5) & 0x100) >> 8;
01223         /* Horizontal Display End */
01224         IO_Write(crtc_base,0x01);IO_Write(crtc_base+1u,(Bit8u)(CurMode->hdispend-1));
01225         hor_overflow|=((CurMode->hdispend-1) & 0x100) >> 7;
01226         /* Start horizontal Blanking */
01227         IO_Write(crtc_base,0x02);IO_Write(crtc_base+1u,(Bit8u)CurMode->hdispend);
01228         hor_overflow|=((CurMode->hdispend) & 0x100) >> 6;
01229         /* End horizontal Blanking */
01230         Bitu blank_end=(CurMode->htotal-2) & 0x7f;
01231         IO_Write(crtc_base,0x03);IO_Write(crtc_base+1u,0x80|(blank_end & 0x1f));
01232 
01233         /* Start Horizontal Retrace */
01234         Bitu ret_start;
01235         if ((CurMode->special & _EGA_HALF_CLOCK) && (CurMode->type!=M_CGA2)) ret_start = (CurMode->hdispend+3);
01236         else if (CurMode->type==M_TEXT) ret_start = (CurMode->hdispend+5);
01237         else ret_start = (CurMode->hdispend+4);
01238         IO_Write(crtc_base,0x04);IO_Write(crtc_base+1u,(Bit8u)ret_start);
01239         hor_overflow|=(ret_start & 0x100) >> 4;
01240 
01241         /* End Horizontal Retrace */
01242         Bitu ret_end;
01243         if (CurMode->special & _EGA_HALF_CLOCK) {
01244                 if (CurMode->type==M_CGA2) ret_end=0;   // mode 6
01245                 else if (CurMode->special & _DOUBLESCAN) ret_end = (CurMode->htotal-18) & 0x1f;
01246                 else ret_end = ((CurMode->htotal-18) & 0x1f) | 0x20; // mode 0&1 have 1 char sync delay
01247         } else if (CurMode->type==M_TEXT) ret_end = (CurMode->htotal-3) & 0x1f;
01248         else ret_end = (CurMode->htotal-4) & 0x1f;
01249         
01250         IO_Write(crtc_base,0x05);IO_Write(crtc_base+1u,(Bit8u)(ret_end | (blank_end & 0x20) << 2));
01251 
01252         /* Vertical Total */
01253         IO_Write(crtc_base,0x06);IO_Write(crtc_base+1u,(Bit8u)(CurMode->vtotal-2));
01254         overflow|=((CurMode->vtotal-2) & 0x100) >> 8;
01255         overflow|=((CurMode->vtotal-2) & 0x200) >> 4;
01256         ver_overflow|=((CurMode->vtotal-2) & 0x400) >> 10;
01257 
01258         Bitu vretrace;
01259         if (IS_VGA_ARCH) {
01260                 switch (CurMode->vdispend) {
01261                 case 400: vretrace=CurMode->vdispend+12;
01262                                 break;
01263                 case 480: vretrace=CurMode->vdispend+10;
01264                                 break;
01265                 case 350: vretrace=CurMode->vdispend+37;
01266                                 break;
01267                 default: vretrace=CurMode->vdispend+12;
01268                 }
01269         } else {
01270                 switch (CurMode->vdispend) {
01271                 case 350: vretrace=CurMode->vdispend;
01272                                 break;
01273                 default: vretrace=CurMode->vdispend+24;
01274                 }
01275         }
01276 
01277         /* Vertical Retrace Start */
01278         IO_Write(crtc_base,0x10);IO_Write(crtc_base+1u,(Bit8u)vretrace);
01279         overflow|=(vretrace & 0x100) >> 6;
01280         overflow|=(vretrace & 0x200) >> 2;
01281         ver_overflow|=(vretrace & 0x400) >> 6;
01282 
01283         /* Vertical Retrace End */
01284         IO_Write(crtc_base,0x11);IO_Write(crtc_base+1u,(vretrace+2) & 0xF);
01285 
01286         /* Vertical Display End */
01287         IO_Write(crtc_base,0x12);IO_Write(crtc_base+1u,(Bit8u)(CurMode->vdispend-1));
01288         overflow|=((CurMode->vdispend-1) & 0x100) >> 7;
01289         overflow|=((CurMode->vdispend-1) & 0x200) >> 3;
01290         ver_overflow|=((CurMode->vdispend-1) & 0x400) >> 9;
01291         
01292         Bitu vblank_trim;
01293         if (IS_VGA_ARCH) {
01294                 switch (CurMode->vdispend) {
01295                 case 400: vblank_trim=6;
01296                                 break;
01297                 case 480: vblank_trim=7;
01298                                 break;
01299                 case 350: vblank_trim=5;
01300                                 break;
01301                 default: vblank_trim=8;
01302                 }
01303         } else {
01304                 switch (CurMode->vdispend) {
01305                 case 350: vblank_trim=0;
01306                                 break;
01307                 default: vblank_trim=23;
01308                 }
01309         }
01310 
01311         /* Vertical Blank Start */
01312         IO_Write(crtc_base,0x15);IO_Write(crtc_base+1u,(Bit8u)(CurMode->vdispend+vblank_trim));
01313         overflow|=((CurMode->vdispend+vblank_trim) & 0x100) >> 5;
01314         max_scanline|=((CurMode->vdispend+vblank_trim) & 0x200) >> 4;
01315         ver_overflow|=((CurMode->vdispend+vblank_trim) & 0x400) >> 8;
01316 
01317         /* Vertical Blank End */
01318         IO_Write(crtc_base,0x16);IO_Write(crtc_base+1u,(Bit8u)(CurMode->vtotal-vblank_trim-2));
01319 
01320         /* Line Compare */
01321         Bitu line_compare=(CurMode->vtotal < 1024) ? 1023 : 2047;
01322         IO_Write(crtc_base,0x18);IO_Write(crtc_base+1u,line_compare&0xff);
01323         overflow|=(line_compare & 0x100) >> 4;
01324         max_scanline|=(line_compare & 0x200) >> 3;
01325         ver_overflow|=(line_compare & 0x400) >> 4;
01326         Bit8u underline=0;
01327         /* Maximum scanline / Underline Location */
01328         if (CurMode->special & _DOUBLESCAN) max_scanline|=0x80;
01329         if (CurMode->special & _REPEAT1) max_scanline|=0x01;
01330 
01331         switch (CurMode->type) {
01332         case M_TEXT:
01333                 if(IS_VGA_ARCH) {
01334                         switch(modeset_ctl & 0x90) {
01335                         case 0x0: // 350-lines mode: 8x14 font
01336                                 max_scanline |= (14-1);
01337                                 break;
01338                         default: // reserved
01339                         case 0x10: // 400 lines 8x16 font
01340                 max_scanline|=CurMode->cheight-1;
01341                                 break;
01342                         case 0x80: // 200 lines: 8x8 font and doublescan
01343                                 max_scanline |= (8-1);
01344                                 max_scanline |= 0x80;
01345                                 break;
01346                         }
01347                 } else max_scanline |= CurMode->cheight-1;
01348                 underline=mono_mode ? 0x0f : 0x1f; // mode 7 uses a diff underline position
01349                 break;
01350         case M_VGA:
01351                 underline=0x40;
01352                 break;
01353         case M_LIN8:
01354         case M_LIN15:
01355         case M_LIN16:
01356         case M_LIN24:
01357         case M_LIN32:
01358                 underline=0x60;                 //Seems to enable the every 4th clock on my s3
01359                 break;
01360         default:
01361                 break;
01362         }
01363 
01364     /* do NOT apply this to VESA BIOS modes */
01365         if (CurMode->mode < 0x100 && CurMode->vdispend==350) underline=0x0f;
01366 
01367         IO_Write(crtc_base,0x09);IO_Write(crtc_base+1u,max_scanline);
01368         IO_Write(crtc_base,0x14);IO_Write(crtc_base+1u,underline);
01369 
01370         /* OverFlow */
01371         IO_Write(crtc_base,0x07);IO_Write(crtc_base+1u,overflow);
01372 
01373         if (svgaCard == SVGA_S3Trio) {
01374                 /* Extended Horizontal Overflow */
01375                 IO_Write(crtc_base,0x5d);IO_Write(crtc_base+1u,hor_overflow);
01376                 /* Extended Vertical Overflow */
01377                 IO_Write(crtc_base,0x5e);IO_Write(crtc_base+1u,ver_overflow);
01378         }
01379 
01380         /* Offset Register */
01381         Bitu offset;
01382         switch (CurMode->type) {
01383         case M_LIN8:
01384                 offset = CurMode->swidth/8;
01385                 break;
01386         case M_LIN15:
01387         case M_LIN16:
01388                 offset = 2 * CurMode->swidth/8;
01389                 break;
01390         case M_LIN24:
01391                 offset = 3 * CurMode->swidth/8;
01392                 break;
01393         case M_LIN32:
01394                 offset = 4 * CurMode->swidth/8;
01395                 break;
01396     case M_EGA:
01397         if (IS_EGA_ARCH && vga.mem.memsize < 0x20000 && CurMode->vdispend==350)
01398             offset = CurMode->hdispend/4;
01399         else
01400             offset = CurMode->hdispend/2;
01401                 break;
01402         default:
01403         offset = CurMode->hdispend/2;
01404         break;
01405     }
01406         IO_Write(crtc_base,0x13);
01407         IO_Write(crtc_base + 1u,offset & 0xff);
01408 
01409         if (svgaCard == SVGA_S3Trio) {
01410                 /* Extended System Control 2 Register  */
01411                 /* This register actually has more bits but only use the extended offset ones */
01412                 IO_Write(crtc_base,0x51);
01413                 IO_Write(crtc_base + 1u,(Bit8u)((offset & 0x300) >> 4));
01414                 /* Clear remaining bits of the display start */
01415                 IO_Write(crtc_base,0x69);
01416                 IO_Write(crtc_base + 1u,0);
01417                 /* Extended Vertical Overflow */
01418                 IO_Write(crtc_base,0x5e);IO_Write(crtc_base+1u,ver_overflow);
01419         }
01420 
01421         /* Mode Control */
01422         Bit8u mode_control=0;
01423 
01424         switch (CurMode->type) {
01425         case M_CGA2:
01426                 mode_control=0xc2; // 0x06 sets address wrap.
01427                 break;
01428         case M_CGA4:
01429                 mode_control=0xa2;
01430                 break;
01431         case M_LIN4:
01432         case M_EGA:
01433         if (CurMode->mode==0x11) // 0x11 also sets address wrap.  thought maybe all 2 color modes did but 0x0f doesn't.
01434             mode_control=0xc3; // so.. 0x11 or 0x0f a one off?
01435         else
01436             mode_control=0xe3;
01437 
01438         if (IS_EGA_ARCH && vga.mem.memsize < 0x20000 && CurMode->vdispend==350)
01439             mode_control &= ~0x40; // word mode
01440                 break;
01441         case M_TEXT:
01442         case M_VGA:
01443         case M_LIN8:
01444         case M_LIN15:
01445         case M_LIN16:
01446         case M_LIN24:
01447         case M_LIN32:
01448     case M_PACKED4:
01449                 mode_control=0xa3;
01450                 if (CurMode->special & _VGA_PIXEL_DOUBLE)
01451                         mode_control |= 0x08;
01452                 break;
01453         default:
01454                 break;
01455         }
01456 
01457     if (IS_EGA_ARCH && vga.mem.memsize < 0x20000)
01458         mode_control &= ~0x20; // address wrap bit 13
01459 
01460         IO_Write(crtc_base,0x17);IO_Write(crtc_base+1u,mode_control);
01461         /* Renable write protection */
01462         IO_Write(crtc_base,0x11);
01463         IO_Write(crtc_base+1u,IO_Read(crtc_base+1u)|0x80);
01464 
01465         if (svgaCard == SVGA_S3Trio) {
01466                 /* Setup the correct clock */
01467                 if (CurMode->mode>=0x100) {
01468                         misc_output|=0xef;              //Select clock 3 
01469                         Bitu clock=CurMode->vtotal*8*CurMode->htotal*70;
01470                         if(CurMode->type==M_LIN15 || CurMode->type==M_LIN16) clock/=2;
01471                         VGA_SetClock(3,clock/1000);
01472                 }
01473                 Bit8u misc_control_2;
01474                 /* Setup Pixel format */
01475                 switch (CurMode->type) {
01476                 case M_LIN8:
01477                 default:
01478                         misc_control_2=0x00;
01479                         break;
01480                 case M_LIN15:
01481                         misc_control_2=0x30;
01482                         break;
01483                 case M_LIN16:
01484                         misc_control_2=0x50;
01485                         break;
01486                 case M_LIN24:
01487                         misc_control_2=0x70; /* FIXME: Is this right? I have no other reference than comments in vga_s3.cpp and s3freak's patch */
01488                         break;
01489                 case M_LIN32:
01490                         misc_control_2=0xd0;
01491                         break;
01492         case M_PACKED4://HACK
01493                         misc_control_2=0xf0;
01494                         break;
01495                 }
01496                 IO_WriteB(crtc_base,0x67);IO_WriteB(crtc_base+1u,misc_control_2);
01497         }
01498 
01499         /* Write Misc Output */
01500         IO_Write(0x3c2,misc_output);
01501         /* Program Graphics controller */
01502         Bit8u gfx_data[GFX_REGS];
01503         memset(gfx_data,0,GFX_REGS);
01504         gfx_data[0x7]=0xf;                              /* Color don't care */
01505         gfx_data[0x8]=0xff;                             /* BitMask */
01506         switch (CurMode->type) {
01507         case M_TEXT:
01508                 gfx_data[0x5]|=0x10;            //Odd-Even Mode
01509                 gfx_data[0x6]|=mono_mode ? 0x0a : 0x0e;         //Either b800 or b000, chain odd/even enable
01510                 break;
01511         case M_LIN8:
01512         case M_LIN15:
01513         case M_LIN16:
01514         case M_LIN24:
01515         case M_LIN32:
01516     case M_PACKED4:
01517                 gfx_data[0x5]|=0x40;            //256 color mode
01518         if (int10_vesa_map_as_128kb)
01519                 gfx_data[0x6]|=0x01;    //graphics mode at 0xa000-bffff
01520         else
01521                 gfx_data[0x6]|=0x05;    //graphics mode at 0xa000-affff
01522                 break;
01523         case M_VGA:
01524                 gfx_data[0x5]|=0x40;            //256 color mode
01525                 gfx_data[0x6]|=0x05;            //graphics mode at 0xa000-affff
01526                 break;
01527         case M_LIN4:
01528         case M_EGA:
01529         if (IS_EGA_ARCH && vga.mem.memsize < 0x20000 && CurMode->vdispend==350) {
01530             gfx_data[0x5]|=0x10;                //Odd-Even Mode
01531             gfx_data[0x6]|=0x02;                //Odd-Even Mode
01532                 gfx_data[0x7]=0x5;                      /* Color don't care */
01533         }
01534                 gfx_data[0x6]|=0x05;            //graphics mode at 0xa000-affff
01535                 break;
01536         case M_CGA4:
01537                 gfx_data[0x5]|=0x20;            //CGA mode
01538                 gfx_data[0x6]|=0x0f;            //graphics mode at at 0xb800=0xbfff
01539                 if (IS_EGAVGA_ARCH) gfx_data[0x5]|=0x10;
01540                 break;
01541         case M_CGA2:
01542                 gfx_data[0x6]|=0x0d;            //graphics mode at at 0xb800=0xbfff, chain odd/even disabled
01543                 break;
01544         default:
01545                 break;
01546         }
01547         for (Bit8u ct=0;ct<GFX_REGS;ct++) {
01548                 IO_Write(0x3ce,ct);
01549                 IO_Write(0x3cf,gfx_data[ct]);
01550         }
01551         Bit8u att_data[ATT_REGS];
01552         memset(att_data,0,ATT_REGS);
01553         att_data[0x12]=0xf;                             //Always have all color planes enabled
01554         /* Program Attribute Controller */
01555         switch (CurMode->type) {
01556         case M_EGA:
01557         case M_LIN4:
01558                 att_data[0x10]=0x01;            //Color Graphics
01559                 switch (CurMode->mode) {
01560                 case 0x0f:
01561                         att_data[0x12]=0x05;    // planes 0 and 2 enabled
01562                         att_data[0x10]|=0x0a;   // monochrome and blinking
01563         
01564                         att_data[0x01]=0x08; // low-intensity
01565                         att_data[0x04]=0x18; // blink-on case
01566                         att_data[0x05]=0x18; // high-intensity
01567                         att_data[0x09]=0x08; // low-intensity in blink-off case
01568                         att_data[0x0d]=0x18; // high-intensity in blink-off
01569                         break;
01570                 case 0x11:
01571                         for (i=1;i<16;i++) att_data[i]=0x3f;
01572                         break;
01573                 case 0x10:
01574                 case 0x12: 
01575                         goto att_text16;
01576                 default:
01577                         if ( CurMode->type == M_LIN4 )
01578                                 goto att_text16;
01579                         for (Bit8u ct=0;ct<8;ct++) {
01580                                 att_data[ct]=ct;
01581                                 att_data[ct+8]=ct+0x10;
01582                         }
01583                         break;
01584                 }
01585                 break;
01586         case M_TANDY16:
01587                 att_data[0x10]=0x01;            //Color Graphics
01588                 for (Bit8u ct=0;ct<16;ct++) att_data[ct]=ct;
01589                 break;
01590         case M_TEXT:
01591                 if (CurMode->cwidth==9) {
01592                         att_data[0x13]=0x08;    //Pel panning on 8, although we don't have 9 dot text mode
01593                         att_data[0x10]=0x0C;    //Color Text with blinking, 9 Bit characters
01594                 } else {
01595                         att_data[0x13]=0x00;
01596                         att_data[0x10]=0x08;    //Color Text with blinking, 8 Bit characters
01597                 }
01598                 real_writeb(BIOSMEM_SEG,BIOSMEM_CURRENT_PAL,0x30);
01599 att_text16:
01600                 if (CurMode->mode==7) {
01601                         att_data[0]=0x00;
01602                         att_data[8]=0x10;
01603                         for (i=1; i<8; i++) {
01604                                 att_data[i]=0x08;
01605                                 att_data[i+8]=0x18;
01606                         }
01607                 } else {
01608                         for (Bit8u ct=0;ct<8;ct++) {
01609                                 att_data[ct]=ct;
01610                                 att_data[ct+8]=ct+0x38;
01611                         }
01612                         if (IS_VGA_ARCH) att_data[0x06]=0x14;           //Odd Color 6 yellow/brown.
01613                 }
01614                 break;
01615         case M_CGA2:
01616                 att_data[0x10]=0x01;            //Color Graphics
01617                 att_data[0]=0x0;
01618                 for (i=1;i<0x10;i++) att_data[i]=0x17;
01619                 att_data[0x12]=0x1;                     //Only enable 1 plane
01620                 real_writeb(BIOSMEM_SEG,BIOSMEM_CURRENT_PAL,0x3f);
01621                 break;
01622         case M_CGA4:
01623                 att_data[0x10]=0x01;            //Color Graphics
01624                 att_data[0]=0x0;
01625                 att_data[1]=0x13;
01626                 att_data[2]=0x15;
01627                 att_data[3]=0x17;
01628                 att_data[4]=0x02;
01629                 att_data[5]=0x04;
01630                 att_data[6]=0x06;
01631                 att_data[7]=0x07;
01632                 for (Bit8u ct=0x8;ct<0x10;ct++) 
01633                         att_data[ct] = ct + 0x8;
01634                 real_writeb(BIOSMEM_SEG,BIOSMEM_CURRENT_PAL,0x30);
01635                 break;
01636         case M_VGA:
01637         case M_LIN8:
01638         case M_LIN15:
01639         case M_LIN16:
01640         case M_LIN24:
01641         case M_LIN32:
01642     case M_PACKED4:
01643                 for (Bit8u ct=0;ct<16;ct++) att_data[ct]=ct;
01644                 att_data[0x10]=0x41;            //Color Graphics 8-bit
01645                 break;
01646         default:
01647                 break;
01648         }
01649         IO_Read(mono_mode ? 0x3ba : 0x3da);
01650         if ((modeset_ctl & 8)==0) {
01651                 for (Bit8u ct=0;ct<ATT_REGS;ct++) {
01652                         IO_Write(0x3c0,ct);
01653                         IO_Write(0x3c0,att_data[ct]);
01654                 }
01655                 vga.config.pel_panning = 0;
01656                 IO_Write(0x3c0,0x20); IO_Write(0x3c0,0x00); //Disable palette access
01657                 IO_Write(0x3c6,0xff); //Reset Pelmask
01658                 /* Setup the DAC */
01659                 IO_Write(0x3c8,0);
01660                 switch (CurMode->type) {
01661                 case M_EGA:
01662                         if (CurMode->mode>0xf) {
01663                                 goto dac_text16;
01664                         } else if (CurMode->mode==0xf) {
01665                                 for (i=0;i<64;i++) {
01666                                         IO_Write(0x3c9,mtext_s3_palette[i][0]);
01667                                         IO_Write(0x3c9,mtext_s3_palette[i][1]);
01668                                         IO_Write(0x3c9,mtext_s3_palette[i][2]);
01669                                 }
01670                         } else {
01671                                 for (i=0;i<64;i++) {
01672                                         IO_Write(0x3c9,ega_palette[i][0]);
01673                                         IO_Write(0x3c9,ega_palette[i][1]);
01674                                         IO_Write(0x3c9,ega_palette[i][2]);
01675                                 }
01676                         }
01677                         break;
01678                 case M_CGA2:
01679                 case M_CGA4:
01680                 case M_TANDY16:
01681                         for (i=0;i<64;i++) {
01682                                 IO_Write(0x3c9,cga_palette_2[i][0]);
01683                                 IO_Write(0x3c9,cga_palette_2[i][1]);
01684                                 IO_Write(0x3c9,cga_palette_2[i][2]);
01685                         }
01686                         break;
01687                 case M_TEXT:
01688                         if (CurMode->mode==7) {
01689                                 if ((IS_VGA_ARCH) && (svgaCard == SVGA_S3Trio)) {
01690                                         for (i=0;i<64;i++) {
01691                                                 IO_Write(0x3c9,mtext_s3_palette[i][0]);
01692                                                 IO_Write(0x3c9,mtext_s3_palette[i][1]);
01693                                                 IO_Write(0x3c9,mtext_s3_palette[i][2]);
01694                                         }
01695                                 } else {
01696                                         for (i=0;i<64;i++) {
01697                                                 IO_Write(0x3c9,mtext_palette[i][0]);
01698                                                 IO_Write(0x3c9,mtext_palette[i][1]);
01699                                                 IO_Write(0x3c9,mtext_palette[i][2]);
01700                                         }
01701                                 }
01702                                 break;
01703                         } //FALLTHROUGH!!!!
01704                 case M_LIN4: //Added for CAD Software
01705 dac_text16:
01706                         for (i=0;i<64;i++) {
01707                                 IO_Write(0x3c9,text_palette[i][0]);
01708                                 IO_Write(0x3c9,text_palette[i][1]);
01709                                 IO_Write(0x3c9,text_palette[i][2]);
01710                         }
01711                         break;
01712                 case M_VGA:
01713                 case M_LIN8:
01714                 case M_LIN15:
01715                 case M_LIN16:
01716                 case M_LIN24:
01717                 case M_LIN32:
01718         case M_PACKED4:
01719                         // IBM and clones use 248 default colors in the palette for 256-color mode.
01720                         // The last 8 colors of the palette are only initialized to 0 at BIOS init.
01721                         // Palette index is left at 0xf8 as on most clones, IBM leaves it at 0x10.
01722                         for (i=0;i<248;i++) {
01723                                 IO_Write(0x3c9,vga_palette[i][0]);
01724                                 IO_Write(0x3c9,vga_palette[i][1]);
01725                                 IO_Write(0x3c9,vga_palette[i][2]);
01726                         }
01727                         break;
01728                 default:
01729                         break;
01730                 }
01731                 if (IS_VGA_ARCH) {
01732                         /* check if gray scale summing is enabled */
01733                         if (modeset_ctl & 2) INT10_PerformGrayScaleSumming(0,256);
01734                 }
01735         /* make sure the DAC index is reset on modeset */
01736                 IO_Write(0x3c7,0); /* according to src/hardware/vga_dac.cpp this sets read_index=0 and write_index=1 */
01737                 IO_Write(0x3c8,0); /* so set write_index=0 */
01738         } else {
01739                 for (Bit8u ct=0x10;ct<ATT_REGS;ct++) {
01740                         if (ct==0x11) continue; // skip overscan register
01741                         IO_Write(0x3c0,ct);
01742                         IO_Write(0x3c0,att_data[ct]);
01743                 }
01744                 vga.config.pel_panning = 0;
01745         }
01746         /* Setup some special stuff for different modes */
01747         Bit8u feature=real_readb(BIOSMEM_SEG,BIOSMEM_INITIAL_MODE);
01748         switch (CurMode->type) {
01749         case M_CGA2:
01750                 feature=(feature&~0x30)|0x20;
01751                 real_writeb(BIOSMEM_SEG,BIOSMEM_CURRENT_MSR,0x1e);
01752                 break;
01753         case M_CGA4:
01754                 feature=(feature&~0x30)|0x20;
01755                 if (CurMode->mode==4) real_writeb(BIOSMEM_SEG,BIOSMEM_CURRENT_MSR,0x2a);
01756                 else if (CurMode->mode==5) real_writeb(BIOSMEM_SEG,BIOSMEM_CURRENT_MSR,0x2e);
01757                 else real_writeb(BIOSMEM_SEG,BIOSMEM_CURRENT_MSR,0x2);
01758                 break;
01759         case M_TANDY16:
01760                 feature=(feature&~0x30)|0x20;
01761                 break;
01762         case M_TEXT:
01763                 feature=(feature&~0x30)|0x20;
01764                 switch (CurMode->mode) {
01765                 case 0:real_writeb(BIOSMEM_SEG,BIOSMEM_CURRENT_MSR,0x2c);break;
01766                 case 1:real_writeb(BIOSMEM_SEG,BIOSMEM_CURRENT_MSR,0x28);break;
01767                 case 2:real_writeb(BIOSMEM_SEG,BIOSMEM_CURRENT_MSR,0x2d);break;
01768                 case 3:
01769                 case 7:real_writeb(BIOSMEM_SEG,BIOSMEM_CURRENT_MSR,0x29);break;
01770                 }
01771                 break;
01772         case M_LIN4:
01773         case M_EGA:     
01774         case M_VGA:
01775                 feature=(feature&~0x30);
01776                 break;
01777         default:
01778                 break;
01779         }
01780         // disabled, has to be set in bios.cpp exclusively
01781 //      real_writeb(BIOSMEM_SEG,BIOSMEM_INITIAL_MODE,feature);
01782 
01783         if (svgaCard == SVGA_S3Trio) {
01784                 /* Setup the CPU Window */
01785                 IO_Write(crtc_base,0x6a);
01786                 IO_Write(crtc_base+1u,0);
01787                 /* Setup the linear frame buffer */
01788                 IO_Write(crtc_base,0x59);
01789                 IO_Write(crtc_base+1u,(Bit8u)((S3_LFB_BASE >> 24)&0xff));
01790                 IO_Write(crtc_base,0x5a);
01791                 IO_Write(crtc_base+1u,(Bit8u)((S3_LFB_BASE >> 16)&0xff));
01792                 IO_Write(crtc_base,0x6b); // BIOS scratchpad
01793                 IO_Write(crtc_base+1u,(Bit8u)((S3_LFB_BASE >> 24)&0xff));
01794                 
01795                 /* Setup some remaining S3 registers */
01796                 IO_Write(crtc_base,0x41); // BIOS scratchpad
01797                 IO_Write(crtc_base+1u,0x88);
01798                 IO_Write(crtc_base,0x52); // extended BIOS scratchpad
01799                 IO_Write(crtc_base+1u,0x80);
01800 
01801                 IO_Write(0x3c4,0x15);
01802                 IO_Write(0x3c5,0x03);
01803 
01804                 IO_Write(crtc_base,0x45);
01805                 IO_Write(crtc_base+1u,0x00);
01806 
01807                 // Accellerator setup 
01808                 Bitu reg_50=S3_XGA_8BPP;
01809                 switch (CurMode->type) {
01810                         case M_LIN15:
01811                         case M_LIN16: reg_50|=S3_XGA_16BPP; break;
01812                         case M_LIN32: reg_50|=S3_XGA_32BPP; break;
01813                         default: break;
01814                 }
01815                 switch(CurMode->swidth) {
01816                         case 640:  reg_50|=S3_XGA_640; break;
01817                         case 800:  reg_50|=S3_XGA_800; break;
01818                         case 1024: reg_50|=S3_XGA_1024; break;
01819                         case 1152: reg_50|=S3_XGA_1152; break;
01820                         case 1280: reg_50|=S3_XGA_1280; break;
01821                         case 1600: reg_50|=S3_XGA_1600; break;
01822                         default: break;
01823                 }
01824                 IO_WriteB(crtc_base,0x50); IO_WriteB(crtc_base+1u,reg_50);
01825 
01826                 Bit8u reg_31, reg_3a;
01827                 switch (CurMode->type) {
01828                         case M_LIN15:
01829                         case M_LIN16:
01830                         case M_LIN24:
01831                         case M_LIN32:
01832             case M_PACKED4:
01833                                 reg_3a=0x15;
01834                                 break;
01835                         case M_LIN8:
01836                                 // S3VBE20 does it this way. The other double pixel bit does not
01837                                 // seem to have an effect on the Trio64.
01838                                 if(CurMode->special&_S3_PIXEL_DOUBLE) reg_3a=0x5;
01839                                 else reg_3a=0x15;
01840                                 break;
01841                         default:
01842                                 reg_3a=5;
01843                                 break;
01844                 };
01845 
01846         unsigned char s3_mode = 0x00;
01847                 
01848                 switch (CurMode->type) {
01849                 case M_LIN4: // <- Theres a discrepance with real hardware on this
01850                 case M_LIN8:
01851                 case M_LIN15:
01852                 case M_LIN16:
01853                 case M_LIN24:
01854                 case M_LIN32:
01855         case M_PACKED4:
01856                         reg_31 = 9;
01857                         break;
01858                 default:
01859                         reg_31 = 5;
01860                         break;
01861                 }
01862 
01863         /* whether to enable the linear framebuffer */
01864         if (CurMode->mode >= 0x100 && !int10.vesa_nolfb)
01865             s3_mode |= 0x10; /* enable LFB */
01866 
01867                 IO_Write(crtc_base,0x3a);IO_Write(crtc_base+1u,reg_3a);
01868                 IO_Write(crtc_base,0x31);IO_Write(crtc_base+1u,reg_31); //Enable banked memory and 256k+ access
01869 
01870                 IO_Write(crtc_base,0x58);
01871                 if (vga.mem.memsize >= (4*1024*1024))
01872                         IO_Write(crtc_base+1u,0x3 | s3_mode);           // 4+ MB window
01873                 else if (vga.mem.memsize >= (2*1024*1024))
01874                         IO_Write(crtc_base+1u,0x2 | s3_mode);           // 2 MB window
01875                 else
01876                         IO_Write(crtc_base+1u,0x1 | s3_mode);           // 1 MB window
01877 
01878                 IO_Write(crtc_base,0x38);IO_Write(crtc_base+1u,0x48);   //Register lock 1
01879                 IO_Write(crtc_base,0x39);IO_Write(crtc_base+1u,0xa5);   //Register lock 2
01880         } else if (svga.set_video_mode) {
01881                 VGA_ModeExtraData modeData;
01882                 modeData.ver_overflow = ver_overflow;
01883                 modeData.hor_overflow = hor_overflow;
01884                 modeData.offset = offset;
01885                 modeData.modeNo = CurMode->mode;
01886                 modeData.htotal = CurMode->htotal;
01887                 modeData.vtotal = CurMode->vtotal;
01888                 svga.set_video_mode(crtc_base, &modeData);
01889         }
01890 
01891         FinishSetMode(clearmem);
01892 
01893         /* Set vga attrib register into defined state */
01894         IO_Read(mono_mode ? 0x3ba : 0x3da);
01895         IO_Write(0x3c0,0x20);
01896         IO_Read(mono_mode ? 0x3ba : 0x3da);
01897 
01898         /* Load text mode font */
01899         if (CurMode->type==M_TEXT) {
01900                 INT10_ReloadFont();
01901         }
01902         // Enable screen memory access
01903         IO_Write(0x3c4,1); IO_Write(0x3c5,seq_data[1] & ~0x20);
01904         //LOG_MSG("setmode end");
01905 
01906         if (en_int33) INT10_SetCurMode();
01907 
01908         return true;
01909 }
01910 
01911 Bitu VideoModeMemSize(Bitu mode) {
01912         if (!IS_VGA_ARCH)
01913                 return 0;
01914 
01915         VideoModeBlock* modelist = NULL;
01916 
01917         switch (svgaCard) {
01918         case SVGA_TsengET4K:
01919         case SVGA_TsengET3K:
01920                 modelist = ModeList_VGA_Tseng;
01921                 break;
01922         case SVGA_ParadisePVGA1A:
01923                 modelist = ModeList_VGA_Paradise;
01924                 break;
01925         default:
01926                 modelist = ModeList_VGA;
01927                 break;
01928         }
01929 
01930         VideoModeBlock* vmodeBlock = NULL;
01931         Bitu i=0;
01932         while (modelist[i].mode!=0xffff) {
01933                 if (modelist[i].mode==mode) {
01934                         /* Hack for VBE 1.2 modes and 24/32bpp ambiguity */
01935                         if (modelist[i].mode >= 0x100 && modelist[i].mode <= 0x11F &&
01936                 !(modelist[i].special & _USER_MODIFIED) &&
01937                                 ((modelist[i].type == M_LIN32 && !vesa12_modes_32bpp) ||
01938                                  (modelist[i].type == M_LIN24 && vesa12_modes_32bpp))) {
01939                                 /* ignore */
01940                         }
01941                         else {
01942                                 vmodeBlock = &modelist[i];
01943                                 break;
01944                         }
01945                 }
01946                 i++;
01947         }
01948 
01949         if (!vmodeBlock)
01950                 return ~0ul;
01951 
01952         switch(vmodeBlock->type) {
01953     case M_PACKED4:
01954                 if (mode >= 0x100 && !allow_vesa_4bpp_packed) return ~0ul;
01955                 return vmodeBlock->swidth*vmodeBlock->sheight/2;
01956         case M_LIN4:
01957                 if (mode >= 0x100 && !allow_vesa_4bpp) return ~0ul;
01958                 return vmodeBlock->swidth*vmodeBlock->sheight/2;
01959         case M_LIN8:
01960                 if (mode >= 0x100 && !allow_vesa_8bpp) return ~0ul;
01961                 return vmodeBlock->swidth*vmodeBlock->sheight;
01962         case M_LIN15:
01963                 if (mode >= 0x100 && !allow_vesa_15bpp) return ~0ul;
01964                 return vmodeBlock->swidth*vmodeBlock->sheight*2;
01965         case M_LIN16:
01966                 if (mode >= 0x100 && !allow_vesa_16bpp) return ~0ul;
01967                 return vmodeBlock->swidth*vmodeBlock->sheight*2;
01968         case M_LIN24:
01969                 if (mode >= 0x100 && !allow_vesa_24bpp) return ~0ul;
01970                 return vmodeBlock->swidth*vmodeBlock->sheight*3;
01971         case M_LIN32:
01972                 if (mode >= 0x100 && !allow_vesa_32bpp) return ~0ul;
01973                 return vmodeBlock->swidth*vmodeBlock->sheight*4;
01974         case M_TEXT:
01975                 if (mode >= 0x100 && !allow_vesa_tty) return ~0ul;
01976                 return vmodeBlock->twidth*vmodeBlock->theight*2;
01977         default:
01978                 break;
01979         }
01980         // Return 0 for all other types, those always fit in memory
01981         return 0;
01982 }
01983 
01984 Bitu INT10_WriteVESAModeList(Bitu max_modes);
01985 
01986 /* ====================== VESAMOED.COM ====================== */
01987 class VESAMOED : public Program {
01988 public:
01989         void Run(void) {
01990         size_t array_i = 0;
01991         std::string arg,tmp;
01992                 bool got_opt=false;
01993         int mode = -1;
01994         int fmt = -1;
01995         int w = -1,h = -1;
01996         int ch = -1;
01997         int newmode = -1;
01998         signed char enable = -1;
01999         bool doDelete = false;
02000         bool modefind = false;
02001                 
02002         cmd->BeginOpt();
02003         while (cmd->GetOpt(/*&*/arg)) {
02004                         got_opt=true;
02005             if (arg == "?" || arg == "help") {
02006                 doHelp();
02007                 break;
02008             }
02009             else if (arg == "mode") {
02010                 cmd->NextOptArgv(/*&*/tmp);
02011 
02012                 if (tmp == "find") {
02013                     modefind = true;
02014                 }
02015                 else if (isdigit(tmp[0])) {
02016                     mode = strtoul(tmp.c_str(),NULL,0);
02017                 }
02018                 else {
02019                     WriteOut("Unknown mode '%s'\n",tmp.c_str());
02020                     return;
02021                 }
02022             }
02023             else if (arg == "fmt") {
02024                 cmd->NextOptArgv(/*&*/tmp);
02025 
02026                      if (tmp == "LIN4")
02027                     fmt = M_LIN4;
02028                 else if (tmp == "LIN8")
02029                     fmt = M_LIN8;
02030                 else if (tmp == "LIN15")
02031                     fmt = M_LIN15;
02032                 else if (tmp == "LIN16")
02033                     fmt = M_LIN16;
02034                 else if (tmp == "LIN24")
02035                     fmt = M_LIN24;
02036                 else if (tmp == "LIN32")
02037                     fmt = M_LIN32;
02038                 else if (tmp == "TEXT")
02039                     fmt = M_TEXT;
02040                 else {
02041                     WriteOut("Unknown format '%s'\n",tmp.c_str());
02042                     return;
02043                 }
02044             }
02045             else if (arg == "w") {
02046                 cmd->NextOptArgv(/*&*/tmp);
02047                 w = strtoul(tmp.c_str(),NULL,0);
02048             }
02049             else if (arg == "h") {
02050                 cmd->NextOptArgv(/*&*/tmp);
02051                 h = strtoul(tmp.c_str(),NULL,0);
02052             }
02053             else if (arg == "ch") {
02054                 cmd->NextOptArgv(/*&*/tmp);
02055                 ch = strtoul(tmp.c_str(),NULL,0);
02056             }
02057             else if (arg == "newmode") {
02058                 cmd->NextOptArgv(/*&*/tmp);
02059 
02060                 if (isdigit(tmp[0])) {
02061                     newmode = strtoul(tmp.c_str(),NULL,0);
02062                 }
02063                 else {
02064                     WriteOut("Unknown newmode '%s'\n",tmp.c_str());
02065                     return;
02066                 }
02067             }
02068             else if (arg == "delete") {
02069                 doDelete = true;
02070             }
02071             // NTS: If you're wondering why we support disabled modes (modes listed but cannot be set),
02072             //      there are plenty of scenarios on actual hardware where this occurs. Laptops, for
02073             //      example, have SVGA chipsets that can go up to 1600x1200, but the BIOS will disable
02074             //      anything above the native resolution of the laptop's LCD display unless an
02075             //      external monitor is attached at boot-up.
02076             else if (arg == "disable") {
02077                 enable = 0;
02078             }
02079             else if (arg == "enable") {
02080                 enable = 1;
02081             }
02082             else {
02083                 WriteOut("Unknown switch %s",arg.c_str());
02084                 return;
02085             }
02086         }
02087         cmd->EndOpt();
02088                 if(!got_opt) {
02089             doHelp();
02090             return;
02091         }
02092 
02093         if (modefind) {
02094             if (w < 0 && h < 0 && fmt < 0)
02095                 return;
02096 
02097             while (ModeList_VGA[array_i].mode != 0xFFFF) {
02098                 bool match = true;
02099 
02100                      if (w > 0 && (Bitu)w != ModeList_VGA[array_i].swidth)
02101                     match = false;
02102                 else if (h > 0 && (Bitu)h != ModeList_VGA[array_i].sheight)
02103                     match = false;
02104                 else if (fmt >= 0 && (Bitu)fmt != ModeList_VGA[array_i].type)
02105                     match = false;
02106                 else if (ModeList_VGA[array_i].type == M_ERROR)
02107                     match = false;
02108                 else if (ModeList_VGA[array_i].mode <= 0x13)
02109                     match = false;
02110 
02111                 if (!match)
02112                     array_i++;
02113                 else
02114                     break;
02115             }
02116         }
02117         else {
02118             while (ModeList_VGA[array_i].mode != 0xFFFF) {
02119                 if (ModeList_VGA[array_i].mode == (Bitu)mode)
02120                     break;
02121 
02122                 array_i++;
02123             }
02124         }
02125 
02126         if (ModeList_VGA[array_i].mode == 0xFFFF) {
02127             WriteOut("Mode not found\n");
02128             return;
02129         }
02130         else if (ModeList_VGA[array_i].mode <= 0x13) {
02131             WriteOut("Editing base VGA modes is not allowed\n");
02132             return;
02133         }
02134         else if (modefind) {
02135             WriteOut("Found mode 0x%x\n",(unsigned int)ModeList_VGA[array_i].mode);
02136         }
02137 
02138         if (enable == 0)
02139             ModeList_VGA[array_i].special |= _USER_DISABLED;
02140         else if (enable == 1)
02141             ModeList_VGA[array_i].special &= ~_USER_DISABLED;
02142 
02143         if (doDelete) {
02144             if (ModeList_VGA[array_i].type != M_ERROR)
02145                 WriteOut("Mode 0x%x deleted\n",ModeList_VGA[array_i].mode);
02146             else
02147                 WriteOut("Mode 0x%x already deleted\n",ModeList_VGA[array_i].mode);
02148 
02149             ModeList_VGA[array_i].type = M_ERROR;
02150             INT10_WriteVESAModeList(int10.rom.vesa_alloc_modes);
02151             return;
02152         }
02153 
02154         if (fmt < 0 && ModeList_VGA[array_i].type == M_ERROR) {
02155             WriteOut("Mode 0x%x is still deleted. Set a format with -fmt to un-delete\n",ModeList_VGA[array_i].mode);
02156             return;
02157         }
02158 
02159         if (!modefind && (w > 0 || h > 0 || fmt >= 0 || ch > 0)) {
02160             WriteOut("Changing mode 0x%x parameters\n",(unsigned int)ModeList_VGA[array_i].mode);
02161 
02162             ModeList_VGA[array_i].special |= _USER_MODIFIED;
02163 
02164             if (fmt >= 0) {
02165                 ModeList_VGA[array_i].type = (VGAModes)fmt;
02166                 /* will require reprogramming width in some cases! */
02167                 if (w < 0) w = ModeList_VGA[array_i].swidth;
02168             }
02169             if (w > 0) {
02170                 /* enforce alignment to avoid problems with modesetting code */
02171                 {
02172                     unsigned int aln = 8;
02173 
02174                     if (ModeList_VGA[array_i].type == M_LIN4)
02175                         aln = 16;
02176 
02177                     w += aln / 2;
02178                     w -= w % aln;
02179                     if (w == 0) w = aln;
02180                 }
02181 
02182                 ModeList_VGA[array_i].swidth = (Bitu)w;
02183                 if (ModeList_VGA[array_i].type == M_LIN15 || ModeList_VGA[array_i].type == M_LIN16) {
02184                     ModeList_VGA[array_i].hdispend = (Bitu)w / 4;
02185                     ModeList_VGA[array_i].htotal = ModeList_VGA[array_i].hdispend + 40;
02186                 }
02187                 else {
02188                     ModeList_VGA[array_i].hdispend = (Bitu)w / 8;
02189                     ModeList_VGA[array_i].htotal = ModeList_VGA[array_i].hdispend + 20;
02190                 }
02191             }
02192             if (h > 0) {
02193                 ModeList_VGA[array_i].sheight = (Bitu)h;
02194 
02195                 if (h >= 340)
02196                     ModeList_VGA[array_i].special &= ~_REPEAT1;
02197                 else
02198                     ModeList_VGA[array_i].special |= _REPEAT1;
02199 
02200                 if (ModeList_VGA[array_i].special & _REPEAT1)
02201                     ModeList_VGA[array_i].vdispend = (Bitu)h * 2;
02202                 else
02203                     ModeList_VGA[array_i].vdispend = (Bitu)h;
02204 
02205                 ModeList_VGA[array_i].vtotal = ModeList_VGA[array_i].vdispend + 49;
02206             }
02207             if (ch == 8 || ch == 14 || ch == 16)
02208                 ModeList_VGA[array_i].cheight = (Bitu)ch;
02209 
02210             ModeList_VGA[array_i].twidth = ModeList_VGA[array_i].swidth / ModeList_VGA[array_i].cwidth;
02211             ModeList_VGA[array_i].theight = ModeList_VGA[array_i].sheight / ModeList_VGA[array_i].cheight;
02212             INT10_WriteVESAModeList(int10.rom.vesa_alloc_modes);
02213         }
02214 
02215         if (newmode >= 0x40) {
02216             WriteOut("Mode 0x%x moved to mode 0x%x\n",(unsigned int)ModeList_VGA[array_i].mode,(unsigned int)newmode);
02217             ModeList_VGA[array_i].mode = (Bitu)newmode;
02218             INT10_WriteVESAModeList(int10.rom.vesa_alloc_modes);
02219         }
02220 
02221         /* if the new mode cannot fit in available memory, then mark as disabled */
02222         {
02223             unsigned int pitch = 0;
02224 
02225             switch (ModeList_VGA[array_i].type) {
02226                 case M_LIN4:
02227                 case M_PACKED4:
02228                     pitch = (ModeList_VGA[array_i].swidth / 8) * 4; /* not totally accurate but close enough */
02229                     break;
02230                 case M_LIN8:
02231                     pitch = ModeList_VGA[array_i].swidth;
02232                     break;
02233                 case M_LIN15:
02234                 case M_LIN16:
02235                     pitch = ModeList_VGA[array_i].swidth * 2;
02236                     break;
02237                 case M_LIN24:
02238                     pitch = ModeList_VGA[array_i].swidth * 3;
02239                     break;
02240                 case M_LIN32:
02241                     pitch = ModeList_VGA[array_i].swidth * 4;
02242                     break;
02243                 default:
02244                     break;
02245             }
02246 
02247             if ((pitch * ModeList_VGA[array_i].sheight) > vga.mem.memsize) {
02248                 /* NTS: Actually we don't mark as disabled, the VESA mode query function will
02249                  *      report as disabled automatically for the same check we do. This just
02250                  *      lets the user know. */
02251                 WriteOut("WARNING: Mode %u x %u as specified exceeds video memory, will be disabled\n",
02252                         ModeList_VGA[array_i].swidth,
02253                         ModeList_VGA[array_i].sheight);
02254             }
02255         }
02256     }
02257     void doHelp(void) {
02258         WriteOut("VESAMOED VESA BIOS mode editor utility\n");
02259         WriteOut("\n");
02260         WriteOut("NOTE: Due to architectual limitations of VBE emulation,\n");
02261         WriteOut("      Adding new modes is not allowed.\n");
02262         WriteOut("\n");
02263         WriteOut("  -mode <x>               VBE video mode to edit.\n");
02264         WriteOut("                            Specify video mode in decimal or hexadecimal,\n");
02265         WriteOut("                            or specify 'find' to match by fmt, width, height.\n");
02266         WriteOut("  -fmt <x>                Change pixel format, or mode to find.\n");
02267         WriteOut("                            LIN4, LIN8, LIN15, LIN16,\n");
02268         WriteOut("                            LIN24, LIN32, TEXT\n");
02269         WriteOut("  -w <x>                  Change width (in pixels), or mode to find.\n");
02270         WriteOut("  -h <x>                  Change height (in pixels), or mode to find.\n");
02271         WriteOut("  -ch <x>                 Change char height (in pixels), or mode to find.\n");
02272         WriteOut("  -newmode <x>            Change video mode number\n");
02273         WriteOut("  -delete                 Delete video mode\n");
02274         WriteOut("  -disable                Disable video mode (list but do not allow setting)\n");
02275         WriteOut("  -enable                 Enable video mode\n");
02276     }
02277 };
02278 
02279 void VESAMOED_ProgramStart(Program * * make) {
02280         *make=new VESAMOED;
02281 }
02282