DOSBox-X
 All Classes Namespaces Files Functions Variables Typedefs Enumerations Enumerator Defines
include/paging.h
00001 /*
00002  *  Copyright (C) 2002-2015  The DOSBox Team
00003  *
00004  *  This program is free software; you can redistribute it and/or modify
00005  *  it under the terms of the GNU General Public License as published by
00006  *  the Free Software Foundation; either version 2 of the License, or
00007  *  (at your option) any later version.
00008  *
00009  *  This program is distributed in the hope that it will be useful,
00010  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
00011  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
00012  *  GNU General Public License for more details.
00013  *
00014  *  You should have received a copy of the GNU General Public License
00015  *  along with this program; if not, write to the Free Software
00016  *  Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
00017  */
00018 
00019 
00020 #ifndef DOSBOX_PAGING_H
00021 #define DOSBOX_PAGING_H
00022 
00023 #ifndef DOSBOX_DOSBOX_H
00024 #include <iostream>
00025 #include "dosbox.h"
00026 #endif
00027 #ifndef DOSBOX_MEM_H
00028 #include "mem.h"
00029 #endif
00030 
00031 // disable this to reduce the size of the TLB
00032 // NOTE: does not work with the dynamic core (dynrec is fine)
00033 #define USE_FULL_TLB
00034 
00035 class PageHandler;
00036 class MEM_CalloutObject;
00037 
00038 class PageDirectory;
00039 
00040 typedef PageHandler* (MEM_CalloutHandler)(MEM_CalloutObject &co,Bitu phys_page);
00041 
00042 void MEM_RegisterHandler(Bitu phys_page,PageHandler *handler,Bitu phys_range=1);
00043 
00044 void MEM_FreeHandler(Bitu phys_page,Bitu phys_range=1);
00045 
00046 void MEM_InvalidateCachedHandler(Bitu phys_page,Bitu phys_range=1);
00047 
00048 static const Bitu MEMMASK_ISA_20BIT = 0x000000FFU; /* ISA 20-bit decode (20 - 12 = 8) */
00049 static const Bitu MEMMASK_ISA_24BIT = 0x00000FFFU; /* ISA 24-bit decode (24 - 12 = 12) */
00050 static const Bitu MEMMASK_FULL      = 0x000FFFFFU; /* full 32-bit decode (32 - 12 = 20) */
00051 
00052 /* WARNING: Will only produce a correct result if 'x' is a nonzero power of two.
00053  * For use with MEMMASK_Combine. 'x' is in units of PAGES not BYTES.
00054  */
00055 static inline Bitu MEMMASK_Range(const Bitu x) {
00056     return ~(x - 1);
00057 }
00058 
00059 /* combine range mask with MEMMASK value.
00060  */
00061 static inline Bitu MEMMASK_Combine(const Bitu a,const Bitu b) {
00062     return a & b;
00063 }
00064 
00065 #define MEM_PAGE_SIZE   (4096)
00066 #define XMS_START               (0x110)
00067 
00068 #if defined(USE_FULL_TLB)
00069 #define TLB_SIZE                (1024*1024)
00070 #else
00071 #define TLB_SIZE                65536   // This must a power of 2 and greater then LINK_START
00072 #define BANK_SHIFT              28
00073 #define BANK_MASK               0xffff // always the same as TLB_SIZE-1?
00074 #define TLB_BANKS               ((1024*1024/TLB_SIZE)-1)
00075 #endif
00076 
00077 #define PFLAG_READABLE          0x1
00078 #define PFLAG_WRITEABLE         0x2
00079 #define PFLAG_HASROM            0x4
00080 #define PFLAG_HASCODE           0x8                             //Page contains dynamic code
00081 #define PFLAG_NOCODE            0x10                    //No dynamic code can be generated here
00082 #define PFLAG_INIT                      0x20                    //No dynamic code can be generated here
00083 
00084 #define LINK_START      ((1024+64)/4)                   //Start right after the HMA
00085 
00086 //Allow 128 mb of memory to be linked
00087 #define PAGING_LINKS (128*1024/4)
00088 
00089 class PageHandler {
00090 public:
00091         PageHandler(Bitu flg) : flags(flg) {}
00092         virtual ~PageHandler(void) { }
00093         virtual Bitu readb(PhysPt addr);
00094         virtual Bitu readw(PhysPt addr);
00095         virtual Bitu readd(PhysPt addr);
00096         virtual void writeb(PhysPt addr,Bitu val);
00097         virtual void writew(PhysPt addr,Bitu val);
00098         virtual void writed(PhysPt addr,Bitu val);
00099         virtual HostPt GetHostReadPt(Bitu phys_page);
00100         virtual HostPt GetHostWritePt(Bitu phys_page);
00101         virtual bool readb_checked(PhysPt addr,Bit8u * val);
00102         virtual bool readw_checked(PhysPt addr,Bit16u * val);
00103         virtual bool readd_checked(PhysPt addr,Bit32u * val);
00104         virtual bool writeb_checked(PhysPt addr,Bitu val);
00105         virtual bool writew_checked(PhysPt addr,Bitu val);
00106         virtual bool writed_checked(PhysPt addr,Bitu val);
00107    PageHandler (void) { }
00108         Bitu flags; 
00109         Bitu getFlags() const {
00110                 return flags;
00111         }
00112         void setFlags(const Bitu flagsNew) {
00113                 flags = flagsNew;
00114         }
00115 
00116 private:
00117         PageHandler(const PageHandler&);
00118         PageHandler& operator=(const PageHandler&);
00119 
00120 };
00121 
00122 /* NTS: To explain the Install() method, the caller not only provides the IOMASK_.. value, but ANDs
00123  *      the least significant bits to define the range of I/O ports to respond to. An ISA Sound Blaster
00124  *      for example would set portmask = (IOMASK_ISA_10BIT & (~0xF)) in order to respond to 220h-22Fh,
00125  *      240h-24Fh, etc. At I/O callout time, the callout object is tested
00126  *      if (cpu_ioport & io_mask) == (m_port & io_mask)
00127  *
00128  *      This does not prevent emulation of devices that start on non-aligned ports or strange port ranges,
00129  *      because the callout handler is free to decline the I/O request, leading the callout process to
00130  *      move on to the next device or mark the I/O port as empty. */
00131 class MEM_CalloutObject {
00132 public:
00133     MEM_CalloutObject() : installed(false), mem_mask(0xFFFFFFFFU), range_mask(0U), alias_mask(0xFFFFFFFFU), getcounter(0), m_handler(NULL), m_base(0), alloc(false) {};
00134     void InvalidateCachedHandlers(void);
00135         void Install(Bitu page,Bitu pagemask/*MEMMASK_ISA_24BIT, etc.*/,MEM_CalloutHandler *handler);
00136         void Uninstall();
00137 public:
00138         bool installed;
00139     Bitu mem_mask;
00140     Bitu range_mask;
00141     Bitu alias_mask;
00142     unsigned int getcounter;
00143     MEM_CalloutHandler *m_handler;
00144         Bitu m_base;
00145     bool alloc;
00146 public:
00147     inline bool MatchPage(const Bitu p) {
00148         /* (p & io_mask) == (m_port & io_mask) but this also works.
00149          * apparently modern x86 processors are faster at addition/subtraction than bitmasking.
00150          * for this to work, m_port must be a multiple of the I/O range. For example, if the I/O
00151          * range is 16 ports, then m_port must be a multiple of 16. */
00152         return ((p - m_base) & mem_mask) == 0;
00153     }
00154     inline bool isInstalled(void) {
00155         return installed;
00156     }
00157 };
00158 
00159 enum MEM_Type_t {
00160     MEM_TYPE_NONE=0,
00161     MEM_TYPE_MIN=1,
00162     MEM_TYPE_ISA=1,
00163     MEM_TYPE_PCI,
00164     MEM_TYPE_MB,
00165 
00166     MEM_TYPE_MAX
00167 };
00168 
00169 void MEM_InitCallouts(void);
00170 
00171 typedef uint32_t MEM_Callout_t;
00172 
00173 static inline uint32_t MEM_Callout_t_comb(const enum MEM_Type_t t,const uint32_t idx) {
00174     return ((uint32_t)t << (uint32_t)28) + idx;
00175 }
00176 
00177 static inline enum MEM_Type_t MEM_Callout_t_type(const MEM_Callout_t t) {
00178     return (enum MEM_Type_t)(t >> 28);
00179 }
00180 
00181 static inline uint32_t MEM_Callout_t_index(const MEM_Callout_t t) {
00182     return t & (((uint32_t)1 << (uint32_t)28) - (uint32_t)1);
00183 }
00184 
00185 static const MEM_Callout_t MEM_Callout_t_none = (MEM_Callout_t)0;
00186 
00187 MEM_Callout_t MEM_AllocateCallout(MEM_Type_t t);
00188 void MEM_FreeCallout(MEM_Callout_t c);
00189 MEM_CalloutObject *MEM_GetCallout(MEM_Callout_t c);
00190 void MEM_PutCallout(MEM_CalloutObject *obj);
00191 
00192 /* Some other functions */
00193 void PAGING_Enable(bool enabled);
00194 bool PAGING_Enabled(void);
00195 void PAGING_SetWP(bool wp);
00196 void PAGING_SwitchCPL(bool isUser);
00197 
00198 Bitu PAGING_GetDirBase(void);
00199 void PAGING_SetDirBase(Bitu cr3);
00200 void PAGING_InitTLB(void);
00201 void PAGING_ClearTLB(void);
00202 
00203 void PAGING_LinkPage(Bitu lin_page,Bitu phys_page);
00204 void PAGING_LinkPage_ReadOnly(Bitu lin_page,Bitu phys_page);
00205 void PAGING_UnlinkPages(Bitu lin_page,Bitu pages);
00206 /* This maps the page directly, only use when paging is disabled */
00207 void PAGING_MapPage(Bitu lin_page,Bitu phys_page);
00208 bool PAGING_MakePhysPage(Bitu & page);
00209 bool PAGING_ForcePageInit(Bitu lin_addr);
00210 
00211 void MEM_SetLFB(Bitu page, Bitu pages, PageHandler *handler, PageHandler *mmiohandler);
00212 void MEM_SetPageHandler(Bitu phys_page, Bitu pages, PageHandler * handler);
00213 void MEM_ResetPageHandler(Bitu phys_page, Bitu pages);
00214 
00215 
00216 #ifdef _MSC_VER
00217 #pragma pack (1)
00218 #endif
00219 struct X86_PageEntryBlock{
00220 #ifdef WORDS_BIGENDIAN
00221         Bit32u          base:20;
00222         Bit32u          avl:3;
00223         Bit32u          g:1;
00224         Bit32u          pat:1;
00225         Bit32u          d:1;
00226         Bit32u          a:1;
00227         Bit32u          pcd:1;
00228         Bit32u          pwt:1;
00229         Bit32u          us:1;
00230         Bit32u          wr:1;
00231         Bit32u          p:1;
00232 #else
00233         Bit32u          p:1;
00234         Bit32u          wr:1;
00235         Bit32u          us:1;
00236         Bit32u          pwt:1;
00237         Bit32u          pcd:1;
00238         Bit32u          a:1;
00239         Bit32u          d:1;
00240         Bit32u          pat:1;
00241         Bit32u          g:1;
00242         Bit32u          avl:3;
00243         Bit32u          base:20;
00244 #endif
00245 } GCC_ATTRIBUTE(packed);
00246 #ifdef _MSC_VER
00247 #pragma pack ()
00248 #endif
00249 
00250 
00251 union X86PageEntry {
00252         Bit32u load;
00253         X86_PageEntryBlock block;
00254 };
00255 
00256 #if !defined(USE_FULL_TLB)
00257 typedef struct {
00258         HostPt read;
00259         HostPt write;
00260         PageHandler * readhandler;
00261         PageHandler * writehandler;
00262         Bit32u phys_page;
00263 } tlb_entry;
00264 #endif
00265 
00266 struct PagingBlock {
00267         Bitu                    cr3;
00268         Bitu                    cr2;
00269         bool wp;
00270         struct {
00271                 Bitu page;
00272                 PhysPt addr;
00273         } base;
00274 #if defined(USE_FULL_TLB)
00275         struct {
00276                 HostPt read[TLB_SIZE];
00277                 HostPt write[TLB_SIZE];
00278                 PageHandler * readhandler[TLB_SIZE];
00279                 PageHandler * writehandler[TLB_SIZE];
00280                 Bit32u  phys_page[TLB_SIZE];
00281         } tlb;
00282 #else
00283         tlb_entry tlbh[TLB_SIZE];
00284         tlb_entry *tlbh_banks[TLB_BANKS];
00285 #endif
00286         struct {
00287                 Bitu used;
00288                 Bit32u entries[PAGING_LINKS];
00289         } links;
00290         struct {
00291                 Bitu used;
00292                 Bit32u entries[PAGING_LINKS];
00293         } ur_links;
00294         struct {
00295                 Bitu used;
00296                 Bit32u entries[PAGING_LINKS];
00297         } krw_links;
00298         struct {
00299                 Bitu used;
00300                 Bit32u entries[PAGING_LINKS];
00301         } kr_links; // WP-only
00302         Bit32u          firstmb[LINK_START];
00303         bool            enabled;
00304 };
00305 
00306 extern PagingBlock paging; 
00307 
00308 /* Some support functions */
00309 
00310 PageHandler * MEM_GetPageHandler(const Bitu phys_page);
00311 
00312 
00313 /* Unaligned address handlers */
00314 Bit16u mem_unalignedreadw(const PhysPt address);
00315 Bit32u mem_unalignedreadd(const PhysPt address);
00316 void mem_unalignedwritew(const PhysPt address,const Bit16u val);
00317 void mem_unalignedwrited(const PhysPt address,const Bit32u val);
00318 
00319 bool mem_unalignedreadw_checked(const PhysPt address,Bit16u * const val);
00320 bool mem_unalignedreadd_checked(const PhysPt address,Bit32u * const val);
00321 bool mem_unalignedwritew_checked(const PhysPt address,Bit16u const val);
00322 bool mem_unalignedwrited_checked(const PhysPt address,Bit32u const val);
00323 
00324 #if defined(USE_FULL_TLB)
00325 
00326 static INLINE HostPt get_tlb_read(const PhysPt address) {
00327         return paging.tlb.read[address>>12];
00328 }
00329 static INLINE HostPt get_tlb_write(const PhysPt address) {
00330         return paging.tlb.write[address>>12];
00331 }
00332 static INLINE PageHandler* get_tlb_readhandler(const PhysPt address) {
00333         return paging.tlb.readhandler[address>>12];
00334 }
00335 static INLINE PageHandler* get_tlb_writehandler(const PhysPt address) {
00336         return paging.tlb.writehandler[address>>12];
00337 }
00338 
00339 /* Use these helper functions to access linear addresses in readX/writeX functions */
00340 static INLINE PhysPt PAGING_GetPhysicalPage(const PhysPt linePage) {
00341         return (paging.tlb.phys_page[linePage>>12]<<12);
00342 }
00343 
00344 static INLINE PhysPt PAGING_GetPhysicalAddress(const PhysPt linAddr) {
00345         return (paging.tlb.phys_page[linAddr>>12]<<12)|(linAddr&0xfff);
00346 }
00347 
00348 #else
00349 
00350 void PAGING_InitTLBBank(tlb_entry **bank);
00351 
00352 static INLINE tlb_entry *get_tlb_entry(const PhysPt address) {
00353         const Bitu index=(address >> 12U);
00354         if (TLB_BANKS && (index > TLB_SIZE)) {
00355                 const Bitu bank=(address >> BANK_SHIFT) - 1U;
00356                 if (!paging.tlbh_banks[bank])
00357                         PAGING_InitTLBBank(&paging.tlbh_banks[bank]);
00358                 return &paging.tlbh_banks[bank][index & BANK_MASK];
00359         }
00360         return &paging.tlbh[index];
00361 }
00362 
00363 static INLINE HostPt get_tlb_read(const PhysPt address) {
00364         return get_tlb_entry(address)->read;
00365 }
00366 static INLINE HostPt get_tlb_write(const PhysPt address) {
00367         return get_tlb_entry(address)->write;
00368 }
00369 static INLINE PageHandler* get_tlb_readhandler(const PhysPt address) {
00370         return get_tlb_entry(address)->readhandler;
00371 }
00372 static INLINE PageHandler* get_tlb_writehandler(const PhysPt address) {
00373         return get_tlb_entry(address)->writehandler;
00374 }
00375 
00376 /* Use these helper functions to access linear addresses in readX/writeX functions */
00377 static INLINE PhysPt PAGING_GetPhysicalPage(const PhysPt linePage) {
00378         tlb_entry *entry = get_tlb_entry(linePage);
00379         return (entry->phys_page<<12);
00380 }
00381 
00382 static INLINE PhysPt PAGING_GetPhysicalAddress(const PhysPt linAddr) {
00383         tlb_entry *entry = get_tlb_entry(linAddr);
00384         return (entry->phys_page<<12)|(linAddr&0xfff);
00385 }
00386 #endif
00387 
00388 /* Special inlined memory reading/writing */
00389 
00390 static INLINE Bit8u mem_readb_inline(const PhysPt address) {
00391         const HostPt tlb_addr=get_tlb_read(address);
00392         if (tlb_addr) return host_readb(tlb_addr+address);
00393         else return (Bit8u)(get_tlb_readhandler(address))->readb(address);
00394 }
00395 
00396 static INLINE Bit16u mem_readw_inline(const PhysPt address) {
00397         if ((address & 0xfff)<0xfff) {
00398                 const HostPt tlb_addr=get_tlb_read(address);
00399                 if (tlb_addr) return host_readw(tlb_addr+address);
00400                 else return (Bit16u)(get_tlb_readhandler(address))->readw(address);
00401         } else return mem_unalignedreadw(address);
00402 }
00403 
00404 static INLINE Bit32u mem_readd_inline(const PhysPt address) {
00405         if ((address & 0xfff)<0xffd) {
00406                 const HostPt tlb_addr=get_tlb_read(address);
00407                 if (tlb_addr) return host_readd(tlb_addr+address);
00408                 else return (get_tlb_readhandler(address))->readd(address);
00409         } else return mem_unalignedreadd(address);
00410 }
00411 
00412 static INLINE void mem_writeb_inline(const PhysPt address,const Bit8u val) {
00413         const HostPt tlb_addr=get_tlb_write(address);
00414         if (tlb_addr) host_writeb(tlb_addr+address,val);
00415         else (get_tlb_writehandler(address))->writeb(address,val);
00416 }
00417 
00418 static INLINE void mem_writew_inline(const PhysPt address,const Bit16u val) {
00419         if ((address & 0xfffu)<0xfffu) {
00420                 const HostPt tlb_addr=get_tlb_write(address);
00421                 if (tlb_addr) host_writew(tlb_addr+address,val);
00422                 else (get_tlb_writehandler(address))->writew(address,val);
00423         } else mem_unalignedwritew(address,val);
00424 }
00425 
00426 static INLINE void mem_writed_inline(const PhysPt address,const Bit32u val) {
00427         if ((address & 0xfffu)<0xffdu) {
00428                 const HostPt tlb_addr=get_tlb_write(address);
00429                 if (tlb_addr) host_writed(tlb_addr+address,val);
00430                 else (get_tlb_writehandler(address))->writed(address,val);
00431         } else mem_unalignedwrited(address,val);
00432 }
00433 
00434 
00435 static INLINE bool mem_readb_checked(const PhysPt address, Bit8u * const val) {
00436         const HostPt tlb_addr=get_tlb_read(address);
00437         if (tlb_addr) {
00438                 *val=host_readb(tlb_addr+address);
00439                 return false;
00440         } else return (get_tlb_readhandler(address))->readb_checked(address, val);
00441 }
00442 
00443 static INLINE bool mem_readw_checked(const PhysPt address, Bit16u * const val) {
00444         if ((address & 0xfffu)<0xfffu) {
00445                 const HostPt tlb_addr=get_tlb_read(address);
00446                 if (tlb_addr) {
00447                         *val=host_readw(tlb_addr+address);
00448                         return false;
00449                 } else return (get_tlb_readhandler(address))->readw_checked(address, val);
00450         } else return mem_unalignedreadw_checked(address, val);
00451 }
00452 
00453 static INLINE bool mem_readd_checked(const PhysPt address, Bit32u * const val) {
00454         if ((address & 0xfffu)<0xffdu) {
00455                 const HostPt tlb_addr=get_tlb_read(address);
00456                 if (tlb_addr) {
00457                         *val=host_readd(tlb_addr+address);
00458                         return false;
00459                 } else return (get_tlb_readhandler(address))->readd_checked(address, val);
00460         } else return mem_unalignedreadd_checked(address, val);
00461 }
00462 
00463 static INLINE bool mem_writeb_checked(const PhysPt address,const Bit8u val) {
00464         const HostPt tlb_addr=get_tlb_write(address);
00465         if (tlb_addr) {
00466                 host_writeb(tlb_addr+address,val);
00467                 return false;
00468         } else return (get_tlb_writehandler(address))->writeb_checked(address,val);
00469 }
00470 
00471 static INLINE bool mem_writew_checked(const PhysPt address,const Bit16u val) {
00472         if ((address & 0xfffu)<0xfffu) {
00473                 const HostPt tlb_addr=get_tlb_write(address);
00474                 if (tlb_addr) {
00475                         host_writew(tlb_addr+address,val);
00476                         return false;
00477                 } else return (get_tlb_writehandler(address))->writew_checked(address,val);
00478         } else return mem_unalignedwritew_checked(address,val);
00479 }
00480 
00481 static INLINE bool mem_writed_checked(const PhysPt address,const Bit32u val) {
00482         if ((address & 0xfffu)<0xffdu) {
00483                 const HostPt tlb_addr=get_tlb_write(address);
00484                 if (tlb_addr) {
00485                         host_writed(tlb_addr+address,val);
00486                         return false;
00487                 } else return (get_tlb_writehandler(address))->writed_checked(address,val);
00488         } else return mem_unalignedwrited_checked(address,val);
00489 }
00490 
00491 extern bool dosbox_allow_nonrecursive_page_fault;       /* when set, do nonrecursive mode (when executing instruction) */
00492 
00493 #include <exception>
00494 
00495 class GuestPageFaultException : public std::exception {
00496 public:
00497         virtual const char *what() const throw() {
00498                 return "Guest page fault exception";
00499         }
00500         GuestPageFaultException(PhysPt n_lin_addr, Bitu n_page_addr, Bitu n_faultcode) {
00501                 lin_addr = n_lin_addr;
00502                 page_addr = n_page_addr;
00503                 faultcode = n_faultcode;
00504         }
00505 public:
00506         PhysPt lin_addr;
00507         Bitu page_addr;
00508         Bitu faultcode;
00509 };
00510 
00511 #endif