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src/hardware/vga_other.cpp
00001 /*
00002  *  Copyright (C) 2002-2015  The DOSBox Team
00003  *
00004  *  This program is free software; you can redistribute it and/or modify
00005  *  it under the terms of the GNU General Public License as published by
00006  *  the Free Software Foundation; either version 2 of the License, or
00007  *  (at your option) any later version.
00008  *
00009  *  This program is distributed in the hope that it will be useful,
00010  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
00011  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
00012  *  GNU General Public License for more details.
00013  *
00014  *  You should have received a copy of the GNU General Public License
00015  *  along with this program; if not, write to the Free Software
00016  *  Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
00017  */
00018 
00019 
00020 #include <string.h>
00021 #include <math.h>
00022 #include "dosbox.h"
00023 #include "inout.h"
00024 #include "vga.h"
00025 #include "mem.h"
00026 #include "pic.h"
00027 #include "render.h"
00028 #include "mapper.h"
00029 
00030 #define crtc(blah) vga.crtc.blah
00031 
00032 static Bitu read_cga(Bitu /*port*/,Bitu /*iolen*/);
00033 static void write_cga(Bitu port,Bitu val,Bitu /*iolen*/);
00034 
00035 static void write_crtc_index_other(Bitu /*port*/,Bitu val,Bitu /*iolen*/) {
00036         vga.other.index=(Bit8u)(val & 0x1f);
00037 }
00038 
00039 static Bitu read_crtc_index_other(Bitu /*port*/,Bitu /*iolen*/) {
00040         return vga.other.index;
00041 }
00042 
00043 static void write_crtc_data_other(Bitu /*port*/,Bitu val,Bitu /*iolen*/) {
00044         switch (vga.other.index) {
00045         case 0x00:              //Horizontal total
00046                 if (vga.other.htotal ^ val) VGA_StartResize();
00047                 vga.other.htotal=(Bit8u)val;
00048                 break;
00049         case 0x01:              //Horizontal displayed chars
00050                 if (vga.other.hdend ^ val) VGA_StartResize();
00051                 vga.other.hdend=(Bit8u)val;
00052                 break;
00053         case 0x02:              //Horizontal sync position
00054                 vga.other.hsyncp=(Bit8u)val;
00055                 break;
00056         case 0x03:              //Horizontal sync width
00057                 if (machine==MCH_TANDY) vga.other.vsyncw=(Bit8u)(val >> 4);
00058                 else vga.other.vsyncw = 16; // The MC6845 has a fixed v-sync width of 16 lines
00059                 vga.other.hsyncw=(Bit8u)(val & 0xf);
00060                 break;
00061         case 0x04:              //Vertical total
00062                 if (vga.other.vtotal ^ val) VGA_StartResize();
00063                 vga.other.vtotal=(Bit8u)(val&0x7f);
00064                 break;
00065         case 0x05:              //Vertical display adjust
00066                 if (vga.other.vadjust ^ val) VGA_StartResize();
00067                 vga.other.vadjust=(Bit8u)val;
00068                 break;
00069         case 0x06:              //Vertical rows
00070                 if (vga.other.vdend ^ val) VGA_StartResize();
00071                 vga.other.vdend=(Bit8u)(val&0x7f);
00072                 break;
00073         case 0x07:              //Vertical sync position
00074                 vga.other.vsyncp=(Bit8u)val;
00075                 break;
00076         case 0x09:              //Max scanline
00077                 val &= 0x1f; // VGADOC says bit 0-3 but the MC6845 datasheet says bit 0-4
00078                 if (vga.other.max_scanline ^ val) VGA_StartResize();
00079                 vga.other.max_scanline=(Bit8u)val;
00080                 break;
00081         case 0x0A:      /* Cursor Start Register */
00082                 vga.other.cursor_start = (Bit8u)(val & 0x3f);
00083                 vga.draw.cursor.sline = (Bit8u)(val&0x1f);
00084                 vga.draw.cursor.enabled = ((val & 0x60) != 0x20);
00085                 break;
00086         case 0x0B:      /* Cursor End Register */
00087                 vga.other.cursor_end = (Bit8u)(val&0x1f);
00088                 vga.draw.cursor.eline = (Bit8u)(val&0x1f);
00089                 break;
00090         case 0x0C:      /* Start Address High Register */
00091                 // Bit 12 (depending on video mode) and 13 are actually masked too,
00092                 // but so far no need to implement it.
00093         if (machine == MCH_MCGA)
00094             vga.config.display_start=(vga.config.display_start & 0x00FF) | ((val&0xFF) << 8);
00095         else
00096             vga.config.display_start=(vga.config.display_start & 0x00FF) | ((val&0x3F) << 8);
00097                 break;
00098         case 0x0D:      /* Start Address Low Register */
00099                 vga.config.display_start=(vga.config.display_start & 0xFF00) | val;
00100                 break;
00101         case 0x0E:      /*Cursor Location High Register */
00102                 vga.config.cursor_start&=0x00ffu;
00103                 vga.config.cursor_start|=(unsigned int)(((Bit8u)val) << 8u);
00104                 break;
00105         case 0x0F:      /* Cursor Location Low Register */
00106                 vga.config.cursor_start&=0xff00u;
00107                 vga.config.cursor_start|=(Bit8u)val;
00108                 break;
00109         case 0x10:      /* Light Pen High */
00110                 // MC6845 datasheet says the light pen registers are only readable
00111                 vga.other.lightpen &= 0xff;
00112                 vga.other.lightpen |= (val & 0x3f)<<8;          // only 6 bits
00113                 break;
00114         case 0x11:      /* Light Pen Low */
00115                 vga.other.lightpen &= 0xff00;
00116                 vga.other.lightpen |= (Bit8u)val;
00117                 break;
00118         default:
00119                 LOG(LOG_VGAMISC,LOG_NORMAL)("MC6845:Write %X to illegal index %x",(int)val,(int)vga.other.index);
00120         }
00121 }
00122 static Bitu read_crtc_data_other(Bitu /*port*/,Bitu /*iolen*/) {
00123         switch (vga.other.index) {
00124         case 0x00:              //Horizontal total
00125                 return vga.other.htotal;
00126         case 0x01:              //Horizontal displayed chars
00127                 return vga.other.hdend;
00128         case 0x02:              //Horizontal sync position
00129                 return vga.other.hsyncp;
00130         case 0x03:              //Horizontal and vertical sync width
00131                 if (machine==MCH_TANDY)
00132                         return (unsigned int)vga.other.hsyncw | (unsigned int)(vga.other.vsyncw << 4u);
00133                 else return vga.other.hsyncw;
00134         case 0x04:              //Vertical total
00135                 return vga.other.vtotal;
00136         case 0x05:              //Vertical display adjust
00137                 return vga.other.vadjust;
00138         case 0x06:              //Vertical rows
00139                 return vga.other.vdend;
00140         case 0x07:              //Vertical sync position
00141                 return vga.other.vsyncp;
00142         case 0x09:              //Max scanline
00143                 return vga.other.max_scanline;
00144         case 0x0A:      /* Cursor Start Register */
00145                 return vga.other.cursor_start;
00146         case 0x0B:      /* Cursor End Register */
00147                 return vga.other.cursor_end;
00148         case 0x0C:      /* Start Address High Register */
00149                 return (Bit8u)(vga.config.display_start >> 8u);
00150         case 0x0D:      /* Start Address Low Register */
00151                 return (Bit8u)(vga.config.display_start & 0xffu);
00152         case 0x0E:      /*Cursor Location High Register */
00153                 return (Bit8u)(vga.config.cursor_start >> 8u);
00154         case 0x0F:      /* Cursor Location Low Register */
00155                 return (Bit8u)(vga.config.cursor_start & 0xffu);
00156         case 0x10:      /* Light Pen High */
00157                 return (Bit8u)(vga.other.lightpen >> 8u);
00158         case 0x11:      /* Light Pen Low */
00159                 return (Bit8u)(vga.other.lightpen & 0xffu);
00160         default:
00161                 LOG(LOG_VGAMISC,LOG_NORMAL)("MC6845:Read from illegal index %x",vga.other.index);
00162         }
00163         return (Bitu)(~0);
00164 }
00165 
00166 static void write_crtc_data_mcga(Bitu port,Bitu val,Bitu iolen) {
00167     if (vga.other.index < 0x10) {
00168         /* MCGA has a write protect, just like VGA */
00169                 if (vga.other.index <= 0x07 && crtc(read_only)) return;
00170 
00171         /* 0x00 through 0x0F are the same as CGA */
00172         write_crtc_data_other(port,val,iolen);
00173     }
00174     else {
00175         switch (vga.other.index) {
00176             case 0x10: /* MCGA Mode Control */
00177                 {
00178                     const Bit8u changed = (vga.other.mcga_mode_control ^ val);
00179 
00180                     /* bit 0: 1=select 320x200 256-color mode    0=all else
00181                      * bit 1: 1=select 640x480 2-color mode      0=all else
00182                      * bit 2: reserved
00183                      * bit 3: 1=horizontal timing parameters computed in hardware for video mode   0=...from timing in registers 0-3
00184                      * bit 4: 1=enable dot clock
00185                      * bit 5: reserved
00186                      * bit 6: inverse of bit 8 of vertical displayed register 0x06
00187                      * bit 7: 1=write protect registers 0-7 */
00188                     vga.other.mcga_mode_control = val;
00189                     if (val & 0x80)
00190                         crtc(read_only) = true;
00191                     else
00192                         crtc(read_only) = false;
00193 
00194                     if (vga.other.mcga_mode_control & 3) {
00195                         for (unsigned int i=0;i < 16;i++)
00196                             VGA_DAC_CombineColor(i,i);
00197 
00198                         VGA_DAC_UpdateColorPalette();
00199                     }
00200 
00201                     if (vga.other.mcga_mode_control & 1) { // MCGA 256-color mode
00202                                             VGA_SetMode(M_VGA);
00203                     }
00204                     else {
00205                         if (vga.other.mcga_mode_control & 2) { // MCGA 640x480 2-color
00206                                                 VGA_SetMode(M_TANDY2);
00207                                 vga.tandy.addr_mask = 0xFFFF;
00208                         }
00209                         else {
00210                             write_cga(0x3D8,vga.tandy.mode_control,1); // restore CGA
00211                                 vga.tandy.addr_mask = 8*1024 - 1;
00212                         }
00213 
00214                         write_cga(0x3D9,vga.tandy.color_select,1); // restore CGA
00215                     }
00216 
00217                     if (changed & 0x0B)
00218                         VGA_StartResize();
00219                 }
00220                 break;
00221             default:
00222                 LOG(LOG_VGAMISC,LOG_NORMAL)("MC6845:MCGA Write %X to illegal index %x",(int)val,(int)vga.other.index);
00223                 break;
00224         }
00225     }
00226 }
00227 static Bitu read_crtc_data_mcga(Bitu port,Bitu iolen) {
00228     if (vga.other.index < 0x10) {
00229         /* 0x00 through 0x0F are the same as CGA */
00230         return read_crtc_data_other(port,iolen);
00231     }
00232     else {
00233         switch (vga.other.index) {
00234             case 0x10: /* MCGA Mode Control */
00235                 return vga.other.mcga_mode_control;
00236             default:
00237                         LOG(LOG_VGAMISC,LOG_NORMAL)("MC6845:MCGA Read from illegal index %x",vga.other.index);
00238                 break;
00239         }
00240     }
00241 
00242         return (Bitu)(~0);
00243 }
00244 
00245 static void write_lightpen(Bitu port,Bitu val,Bitu) {
00246     (void)val;//UNUSED
00247         switch (port) {
00248         case 0x3db:     // Clear lightpen latch
00249                 vga.other.lightpen_triggered = false;
00250                 break;
00251         case 0x3dc:     // Preset lightpen latch
00252                 if (!vga.other.lightpen_triggered) {
00253                         vga.other.lightpen_triggered = true; // TODO: this shows at port 3ba/3da bit 1
00254                         
00255                         double timeInFrame = PIC_FullIndex()-vga.draw.delay.framestart;
00256                         double timeInLine = fmod(timeInFrame,vga.draw.delay.htotal);
00257                         Bitu current_scanline = (Bitu)(timeInFrame / vga.draw.delay.htotal);
00258                         
00259                         vga.other.lightpen = (Bit16u)((vga.draw.address_add/2) * (current_scanline/2));
00260                         vga.other.lightpen += (Bit16u)((timeInLine / vga.draw.delay.hdend) *
00261                                 ((float)(vga.draw.address_add/2)));
00262                 }
00263                 break;
00264         }
00265 }
00266 
00267 Bit8u cga_comp = 0;
00268 bool new_cga = 0;
00269 
00270 static double hue_offset = 0.0;
00271 
00272 static Bit8u cga16_val = 0;
00273 static void update_cga16_color(void);
00274 static Bit8u herc_pal = 0;
00275 static Bit8u mono_cga_pal = 0;
00276 static Bit8u mono_cga_bright = 0;
00277 static Bit8u const mono_cga_palettes[8][16][3] =
00278 {
00279         { // 0 - green, 4-color-optimized contrast
00280                 {0x00,0x00,0x00},{0x00,0x0d,0x03},{0x01,0x17,0x05},{0x01,0x1a,0x06},{0x02,0x28,0x09},{0x02,0x2c,0x0a},{0x03,0x39,0x0d},{0x03,0x3c,0x0e},
00281                 {0x00,0x07,0x01},{0x01,0x13,0x04},{0x01,0x1f,0x07},{0x01,0x23,0x08},{0x02,0x31,0x0b},{0x02,0x35,0x0c},{0x05,0x3f,0x11},{0x0d,0x3f,0x17},
00282         },
00283         { // 1 - green, 16-color-optimized contrast
00284                 {0x00,0x00,0x00},{0x00,0x0d,0x03},{0x01,0x15,0x05},{0x01,0x17,0x05},{0x01,0x21,0x08},{0x01,0x24,0x08},{0x02,0x2e,0x0b},{0x02,0x31,0x0b},
00285                 {0x01,0x22,0x08},{0x02,0x28,0x09},{0x02,0x30,0x0b},{0x02,0x32,0x0c},{0x03,0x39,0x0d},{0x03,0x3b,0x0e},{0x09,0x3f,0x14},{0x0d,0x3f,0x17},
00286         },
00287         { // 2 - amber, 4-color-optimized contrast
00288                 {0x00,0x00,0x00},{0x15,0x05,0x00},{0x20,0x0b,0x00},{0x24,0x0d,0x00},{0x33,0x18,0x00},{0x37,0x1b,0x00},{0x3f,0x26,0x01},{0x3f,0x2b,0x06},
00289                 {0x0b,0x02,0x00},{0x1b,0x08,0x00},{0x29,0x11,0x00},{0x2e,0x14,0x00},{0x3b,0x1e,0x00},{0x3e,0x21,0x00},{0x3f,0x32,0x0a},{0x3f,0x38,0x0d},
00290         },
00291         { // 3 - amber, 16-color-optimized contrast
00292                 {0x00,0x00,0x00},{0x15,0x05,0x00},{0x1e,0x09,0x00},{0x21,0x0b,0x00},{0x2b,0x12,0x00},{0x2f,0x15,0x00},{0x38,0x1c,0x00},{0x3b,0x1e,0x00},
00293                 {0x2c,0x13,0x00},{0x32,0x17,0x00},{0x3a,0x1e,0x00},{0x3c,0x1f,0x00},{0x3f,0x27,0x01},{0x3f,0x2a,0x04},{0x3f,0x36,0x0c},{0x3f,0x38,0x0d},
00294         },
00295         { // 4 - grey, 4-color-optimized contrast
00296                 {0x00,0x00,0x00},{0x0d,0x0d,0x0d},{0x15,0x15,0x15},{0x18,0x18,0x18},{0x24,0x24,0x24},{0x27,0x27,0x27},{0x33,0x33,0x33},{0x37,0x37,0x37},
00297                 {0x08,0x08,0x08},{0x10,0x10,0x10},{0x1c,0x1c,0x1c},{0x20,0x20,0x20},{0x2c,0x2c,0x2c},{0x2f,0x2f,0x2f},{0x3b,0x3b,0x3b},{0x3f,0x3f,0x3f},
00298         },
00299         { // 5 - grey, 16-color-optimized contrast
00300                 {0x00,0x00,0x00},{0x0d,0x0d,0x0d},{0x12,0x12,0x12},{0x15,0x15,0x15},{0x1e,0x1e,0x1e},{0x20,0x20,0x20},{0x29,0x29,0x29},{0x2c,0x2c,0x2c},
00301                 {0x1f,0x1f,0x1f},{0x23,0x23,0x23},{0x2b,0x2b,0x2b},{0x2d,0x2d,0x2d},{0x34,0x34,0x34},{0x36,0x36,0x36},{0x3d,0x3d,0x3d},{0x3f,0x3f,0x3f},
00302         },
00303         { // 6 - paper-white, 4-color-optimized contrast
00304                 {0x00,0x00,0x00},{0x0e,0x0f,0x10},{0x15,0x17,0x18},{0x18,0x1a,0x1b},{0x24,0x25,0x25},{0x27,0x28,0x28},{0x33,0x34,0x32},{0x37,0x38,0x35},
00305                 {0x09,0x0a,0x0b},{0x11,0x12,0x13},{0x1c,0x1e,0x1e},{0x20,0x22,0x22},{0x2c,0x2d,0x2c},{0x2f,0x30,0x2f},{0x3c,0x3c,0x38},{0x3f,0x3f,0x3b},
00306         },
00307         { // 7 - paper-white, 16-color-optimized contrast
00308                 {0x00,0x00,0x00},{0x0e,0x0f,0x10},{0x13,0x14,0x15},{0x15,0x17,0x18},{0x1e,0x20,0x20},{0x20,0x22,0x22},{0x29,0x2a,0x2a},{0x2c,0x2d,0x2c},
00309                 {0x1f,0x21,0x21},{0x23,0x25,0x25},{0x2b,0x2c,0x2b},{0x2d,0x2e,0x2d},{0x34,0x35,0x33},{0x37,0x37,0x34},{0x3e,0x3e,0x3a},{0x3f,0x3f,0x3b},
00310         },
00311 };
00312 
00313 static void cga16_color_select(Bit8u val) {
00314         cga16_val = val;
00315         update_cga16_color();
00316 }
00317 
00318 static void update_cga16_color(void) {
00319 // New algorithm based on code by reenigne
00320 // Works in all CGA graphics modes/color settings and can simulate older and newer CGA revisions
00321         static const double tau = 6.28318531; // == 2*pi
00322         static const double ns = 567.0/440;  // degrees of hue shift per nanosecond
00323 
00324         double tv_brightness = 0.0; // hardcoded for simpler implementation
00325         double tv_saturation = (new_cga ? 0.7 : 0.6);
00326 
00327         bool bw = (vga.tandy.mode_control&4) != 0;
00328         bool color_sel = (cga16_val&0x20) != 0;
00329         bool background_i = (cga16_val&0x10) != 0;      // Really foreground intensity, but this is what the CGA schematic calls it.
00330         bool bpp1 = (vga.tandy.mode_control&0x10) != 0;
00331         Bit8u overscan = cga16_val&0x0f;  // aka foreground colour in 1bpp mode
00332 
00333         double chroma_coefficient = new_cga ? 0.29 : 0.72;
00334         double b_coefficient = new_cga ? 0.07 : 0;
00335         double g_coefficient = new_cga ? 0.22 : 0;
00336         double r_coefficient = new_cga ? 0.1 : 0;
00337         double i_coefficient = new_cga ? 0.32 : 0.28;
00338         double rgbi_coefficients[0x10];
00339         for (int c = 0; c < 0x10; c++) {
00340                 double v = 0;
00341                 if ((c & 1) != 0)
00342                         v += b_coefficient;
00343                 if ((c & 2) != 0)
00344                         v += g_coefficient;
00345                 if ((c & 4) != 0)
00346                         v += r_coefficient;
00347                 if ((c & 8) != 0)
00348                         v += i_coefficient;
00349                 rgbi_coefficients[c] = v;
00350         }
00351 
00352         // The pixel clock delay calculation is not accurate for 2bpp, but the difference is small and a more accurate calculation would be too slow.
00353         static const double rgbi_pixel_delay = 15.5*ns;
00354         static const double chroma_pixel_delays[8] = {
00355                 0,        // Black:   no chroma
00356                 35*ns,    // Blue:    no XORs
00357                 44.5*ns,  // Green:   XOR on rising and falling edges
00358                 39.5*ns,  // Cyan:    XOR on falling but not rising edge
00359                 44.5*ns,  // Red:     XOR on rising and falling edges
00360                 39.5*ns,  // Magenta: XOR on falling but not rising edge
00361                 44.5*ns,  // Yellow:  XOR on rising and falling edges
00362                 39.5*ns}; // White:   XOR on falling but not rising edge
00363         double pixel_clock_delay;
00364         int o = overscan == 0 ? 15 : overscan;
00365         if (overscan == 8)
00366                 pixel_clock_delay = rgbi_pixel_delay;
00367         else {
00368                 double d = rgbi_coefficients[o];
00369                 pixel_clock_delay = (chroma_pixel_delays[o & 7]*chroma_coefficient + rgbi_pixel_delay*d)/(chroma_coefficient + d);
00370         }
00371         pixel_clock_delay -= 21.5*ns;  // correct for delay of color burst
00372 
00373         double hue_adjust = (-(90-33)-hue_offset+pixel_clock_delay)*tau/360.0;
00374         double chroma_signals[8][4];
00375         for (Bit8u i=0; i<4; i++) {
00376                 chroma_signals[0][i] = 0;
00377                 chroma_signals[7][i] = 1;
00378                 for (Bit8u j=0; j<6; j++) {
00379                         static const double phases[6] = {
00380                                 270 - 21.5*ns,  // blue
00381                                 135 - 29.5*ns,  // green
00382                                 180 - 21.5*ns,  // cyan
00383                                   0 - 21.5*ns,  // red
00384                                 315 - 29.5*ns,  // magenta
00385                                  90 - 21.5*ns}; // yellow/burst
00386                         // All the duty cycle fractions are the same, just under 0.5 as the rising edge is delayed 2ns more than the falling edge.
00387                         static const double duty = 0.5 - 2*ns/360.0;
00388 
00389                         // We have a rectangle wave with period 1 (in units of the reciprocal of the color burst frequency) and duty
00390                         // cycle fraction "duty" and phase "phase". We band-limit this wave to frequency 2 and sample it at intervals of 1/4.
00391                         // We model our band-limited wave with 4 frequency components:
00392                         //   f(x) = a + b*sin(x*tau) + c*cos(x*tau) + d*sin(x*2*tau)
00393                         // Then:
00394                         //   a =   integral(0, 1, f(x)*dx) = duty
00395                         //   b = 2*integral(0, 1, f(x)*sin(x*tau)*dx) = 2*integral(0, duty, sin(x*tau)*dx) = 2*(1-cos(x*tau))/tau
00396                         //   c = 2*integral(0, 1, f(x)*cos(x*tau)*dx) = 2*integral(0, duty, cos(x*tau)*dx) = 2*sin(duty*tau)/tau
00397                         //   d = 2*integral(0, 1, f(x)*sin(x*2*tau)*dx) = 2*integral(0, duty, sin(x*4*pi)*dx) = 2*(1-cos(2*tau*duty))/(2*tau)
00398                         double a = duty;
00399                         double b = 2.0*(1.0-cos(duty*tau))/tau;
00400                         double c = 2.0*sin(duty*tau)/tau;
00401                         double d = 2.0*(1.0-cos(duty*2*tau))/(2*tau);
00402 
00403                         double x = (phases[j] + 21.5*ns + pixel_clock_delay)/360.0 + i/4.0;
00404 
00405                         chroma_signals[j+1][i] = a + b*sin(x*tau) + c*cos(x*tau) + d*sin(x*2*tau);
00406                 }
00407         }
00408         Bitu CGApal[4] = {
00409                 overscan,
00410                 (Bitu)(2 + (color_sel||bw ? 1 : 0) + (background_i ? 8 : 0)),
00411                 (Bitu)(4 + (color_sel&&!bw? 1 : 0) + (background_i ? 8 : 0)),
00412                 (Bitu)(6 + (color_sel||bw ? 1 : 0) + (background_i ? 8 : 0))
00413         };
00414         for (Bit8u x=0; x<4; x++) {      // Position of pixel in question
00415                 bool even = (x & 1) == 0;
00416                 for (Bit8u bits=0; bits<(even ? 0x10 : 0x40); ++bits) {
00417                         double Y=0, I=0, Q=0;
00418                         for (Bit8u p=0; p<4; p++) {  // Position within color carrier cycle
00419                                 // generate pixel pattern.
00420                                 Bit8u rgbi;
00421                                 if (bpp1)
00422                                         rgbi = ((bits >> (3-p)) & (even ? 1 : 2)) != 0 ? overscan : 0;
00423                                 else
00424                                         if (even)
00425                                                 rgbi = CGApal[(bits >> (2-(p&2)))&3];
00426                                         else
00427                                                 rgbi = CGApal[(bits >> (4-((p+1)&6)))&3];
00428                                 Bit8u c = rgbi & 7;
00429                                 if (bw && c != 0)
00430                                         c = 7;
00431 
00432                                 // calculate composite output
00433                                 double chroma = chroma_signals[c][(p+x)&3]*chroma_coefficient;
00434                                 double composite = chroma + rgbi_coefficients[rgbi];
00435 
00436                                 Y+=composite;
00437                                 if (!bw) { // burst on
00438                                         I+=composite*2*cos(hue_adjust + (p+x)*tau/4.0);
00439                                         Q+=composite*2*sin(hue_adjust + (p+x)*tau/4.0);
00440                                 }
00441                         }
00442 
00443                         double contrast = 1 - tv_brightness;
00444 
00445                         Y = (contrast*Y/4.0) + tv_brightness; if (Y>1.0) Y=1.0; if (Y<0.0) Y=0.0;
00446                         I = (contrast*I/4.0) * tv_saturation; if (I>0.5957) I=0.5957; if (I<-0.5957) I=-0.5957;
00447                         Q = (contrast*Q/4.0) * tv_saturation; if (Q>0.5226) Q=0.5226; if (Q<-0.5226) Q=-0.5226;
00448 
00449                         static const double gamma = 2.2;
00450 
00451                         double R = Y + 0.9563*I + 0.6210*Q;     R = (R - 0.075) / (1-0.075); if (R<0) R=0; if (R>1) R=1;
00452                         double G = Y - 0.2721*I - 0.6474*Q;     G = (G - 0.075) / (1-0.075); if (G<0) G=0; if (G>1) G=1;
00453                         double B = Y - 1.1069*I + 1.7046*Q;     B = (B - 0.075) / (1-0.075); if (B<0) B=0; if (B>1) B=1;
00454                         R = pow(R, gamma);
00455                         G = pow(G, gamma);
00456                         B = pow(B, gamma);
00457 
00458                         int r = static_cast<int>(255*pow( 1.5073*R -0.3725*G -0.0832*B, 1/gamma)); if (r<0) r=0; if (r>255) r=255;
00459                         int g = static_cast<int>(255*pow(-0.0275*R +0.9350*G +0.0670*B, 1/gamma)); if (g<0) g=0; if (g>255) g=255;
00460                         int b = static_cast<int>(255*pow(-0.0272*R -0.0401*G +1.1677*B, 1/gamma)); if (b<0) b=0; if (b>255) b=255;
00461 
00462                         Bit8u index = bits | ((x & 1) == 0 ? 0x30 : 0x80) | ((x & 2) == 0 ? 0x40 : 0);
00463                         RENDER_SetPal(index,r,g,b);
00464                 }
00465         }
00466 }
00467 
00468 static void IncreaseHue(bool pressed) {
00469         if (!pressed)
00470                 return;
00471         hue_offset += 5.0;
00472         update_cga16_color();
00473         LOG_MSG("Hue at %f",hue_offset); 
00474 }
00475 
00476 static void DecreaseHue(bool pressed) {
00477         if (!pressed)
00478                 return;
00479         hue_offset -= 5.0;
00480         update_cga16_color();
00481         LOG_MSG("Hue at %f",hue_offset); 
00482 }
00483 
00484 static void write_cga_color_select(Bitu val) {
00485         vga.tandy.color_select=val;
00486 
00487     if (vga.other.mcga_mode_control & 1) /* ignore COMPLETELY in 256-color MCGA mode */
00488         return;
00489 
00490         switch(vga.mode) {
00491         case  M_TANDY4: {
00492                 Bit8u base = (val & 0x10) ? 0x08 : 0;
00493                 Bit8u bg = val & 0xf;
00494                 if (vga.tandy.mode_control & 0x4)       // cyan red white
00495                         VGA_SetCGA4Table(bg, 3+base, 4+base, 7+base);
00496                 else if (val & 0x20)                            // cyan magenta white
00497                         VGA_SetCGA4Table(bg, 3+base, 5+base, 7+base);
00498                 else                                                            // green red brown
00499                         VGA_SetCGA4Table(bg, 2+base, 4+base, 6+base);
00500                 vga.tandy.border_color = bg;
00501                 vga.attr.overscan_color = bg;
00502                 break;
00503         }
00504         case M_TANDY2:
00505                 VGA_SetCGA2Table(0,val & 0xf);
00506                 vga.attr.overscan_color = 0;
00507                 break;
00508         case M_CGA16:
00509                 cga16_color_select(val);
00510                 break;
00511         case M_TEXT:
00512                 vga.tandy.border_color = val & 0xf;
00513                 vga.attr.overscan_color = 0;
00514                 break;
00515         case M_AMSTRAD: // Amstrad "palette". 0x3D9
00516                 break;
00517         default:
00518                 break;
00519         }
00520 }
00521 
00522 static Bitu read_cga(Bitu port,Bitu /*iolen*/) {
00523     if (machine == MCH_MCGA) { // On MCGA, ports 3D8h and 3D9h are also readable
00524         switch (port) {
00525             case 0x3d8:
00526                 return vga.tandy.mode_control;
00527             case 0x3d9: // color select
00528                 return vga.tandy.color_select;
00529         }
00530     }
00531 
00532     return ~0UL;
00533 }
00534 
00535 static void write_cga(Bitu port,Bitu val,Bitu /*iolen*/) {
00536     Bitu changed;
00537 
00538         switch (port) {
00539         case 0x3d8:
00540         changed = vga.tandy.mode_control ^ val;
00541 
00542                 vga.tandy.mode_control=(Bit8u)val;
00543                 vga.attr.disabled = (val&0x8)? 0: 1; 
00544         if (vga.other.mcga_mode_control & 3) { // MCGA 256-color mode or 2-color 640x480
00545             // do nothing
00546         }
00547         else if (vga.tandy.mode_control & 0x2) {                // graphics mode
00548                         if (vga.tandy.mode_control & 0x10) {// highres mode
00549                                 if (machine == MCH_AMSTRAD) {
00550                                         VGA_SetMode(M_AMSTRAD);                 //Amstrad 640x200x16 video mode.
00551                                 } else if (machine != MCH_MCGA && (cga_comp==1 || (cga_comp==0 && !(val&0x4))) && !mono_cga) {  // composite display
00552                                         VGA_SetMode(M_CGA16);           // composite ntsc 640x200 16 color mode
00553                                 } else {
00554                                         VGA_SetMode(M_TANDY2);
00555                                 }
00556                         } else {                                                        // lowres mode
00557                                 if (machine != MCH_MCGA && cga_comp==1) {                               // composite display
00558                                         VGA_SetMode(M_CGA16);           // composite ntsc 640x200 16 color mode
00559                                 } else {
00560                                         VGA_SetMode(M_TANDY4);
00561                                 }
00562                         }
00563 
00564                         write_cga_color_select(vga.tandy.color_select);
00565                 } else {
00566                         VGA_SetMode(M_TANDY_TEXT);
00567                 }
00568                 VGA_SetBlinking(val & 0x20);
00569 
00570         /* MCGA: Changes to this bit are important to track, because
00571          *       horizontal timings do not change between 40x25 and 80x25 */
00572         if (changed & 1) /* 80x25 enable bit changed */
00573             VGA_StartResize();
00574 
00575                 break;
00576         case 0x3d9: // color select
00577                 write_cga_color_select(val);
00578                 if( machine==MCH_AMSTRAD ) {
00579                         vga.amstrad.mask_plane = ( val | ( val << 8 ) | ( val << 16 ) | ( val << 24 ) ) & 0x0F0F0F0F;
00580                 }
00581                 break;
00582         case 0x3dd:
00583                 vga.amstrad.write_plane = val & 0x0F;
00584                 break;
00585         case 0x3de:
00586                 vga.amstrad.read_plane = val & 0x03;
00587                 break;
00588         case 0x3df:
00589                 vga.amstrad.border_color = val & 0x0F;
00590                 break;
00591         }
00592 }
00593 
00594 static void CGAModel(bool pressed) {
00595         if (!pressed) return;
00596         new_cga = !new_cga;
00597         update_cga16_color();
00598         LOG_MSG("%s model CGA selected", new_cga ? "Late" : "Early");
00599 }
00600  
00601 static void Composite(bool pressed) {
00602         if (!pressed) return;
00603         if (++cga_comp>2) cga_comp=0;
00604         LOG_MSG("Composite output: %s",(cga_comp==0)?"auto":((cga_comp==1)?"on":"off"));
00605         // switch RGB and Composite if in graphics mode
00606         if (vga.tandy.mode_control & 0x2)
00607                 write_cga(0x3d8,vga.tandy.mode_control,1);
00608 }
00609 
00610 static void tandy_update_palette() {
00611         // TODO mask off bits if needed
00612         if (machine == MCH_TANDY) {
00613                 switch (vga.mode) {
00614                 case M_TANDY2:
00615                         VGA_SetCGA2Table(vga.attr.palette[0],
00616                                 vga.attr.palette[vga.tandy.color_select&0xf]);
00617                         break;
00618                 case M_TANDY4:
00619                         if (vga.tandy.gfx_control & 0x8) {
00620                                 // 4-color high resolution - might be an idea to introduce M_TANDY4H
00621                                 VGA_SetCGA4Table( // function sets both medium and highres 4color tables
00622                                         vga.attr.palette[0], vga.attr.palette[1],
00623                                         vga.attr.palette[2], vga.attr.palette[3]);
00624                         } else {
00625                                 Bit8u color_set = 0;
00626                                 Bit8u r_mask = 0xf;
00627                                 if (vga.tandy.color_select & 0x10) color_set |= 8; // intensity
00628                                 if (vga.tandy.color_select & 0x20) color_set |= 1; // Cyan Mag. White
00629                                 if (vga.tandy.mode_control & 0x04) {                    // Cyan Red White
00630                                         color_set |= 1; 
00631                                         r_mask &= ~1;
00632                                 }
00633                                 VGA_SetCGA4Table(
00634                                         vga.attr.palette[vga.tandy.color_select&0xf],
00635                                         vga.attr.palette[(2|color_set)& vga.tandy.palette_mask],
00636                                         vga.attr.palette[(4|(color_set& r_mask))& vga.tandy.palette_mask],
00637                                         vga.attr.palette[(6|color_set)& vga.tandy.palette_mask]);
00638                         }
00639                         break;
00640                 default:
00641                         break;
00642                 }
00643         } else {
00644                 // PCJr
00645                 switch (vga.mode) {
00646                 case M_TANDY2:
00647                         VGA_SetCGA2Table(vga.attr.palette[0],vga.attr.palette[1]);
00648                         break;
00649                 case M_TANDY4:
00650                         VGA_SetCGA4Table(
00651                                 vga.attr.palette[0], vga.attr.palette[1],
00652                                 vga.attr.palette[2], vga.attr.palette[3]);
00653                         break;
00654                 default:
00655                         break;
00656                 }
00657         }
00658 }
00659 
00660 void VGA_SetModeNow(VGAModes mode);
00661 
00662 static void TANDY_FindMode(void) {
00663         if (vga.tandy.mode_control & 0x2) {
00664                 if (vga.tandy.gfx_control & 0x10) {
00665                         if (vga.mode==M_TANDY4) {
00666                                 VGA_SetModeNow(M_TANDY16);
00667                         } else VGA_SetMode(M_TANDY16);
00668                 }
00669                 else if (vga.tandy.gfx_control & 0x08) {
00670                         VGA_SetMode(M_TANDY4);
00671                 }
00672                 else if (vga.tandy.mode_control & 0x10)
00673                         VGA_SetMode(M_TANDY2);
00674                 else {
00675                         if (vga.mode==M_TANDY16) {
00676                                 VGA_SetModeNow(M_TANDY4);
00677                         } else VGA_SetMode(M_TANDY4);
00678                 }
00679                 tandy_update_palette();
00680         } else {
00681                 VGA_SetMode(M_TANDY_TEXT);
00682         }
00683 }
00684 
00685 static void PCJr_FindMode(void) {
00686         if (vga.tandy.mode_control & 0x2) {
00687                 if (vga.tandy.mode_control & 0x10) {
00688                         /* bit4 of mode control 1 signals 16 colour graphics mode */
00689                         if (vga.mode==M_TANDY4) VGA_SetModeNow(M_TANDY16); // TODO lowres mode only
00690                         else VGA_SetMode(M_TANDY16);
00691                 } else if (vga.tandy.gfx_control & 0x08) {
00692                         /* bit3 of mode control 2 signals 2 colour graphics mode */
00693                         VGA_SetMode(M_TANDY2);
00694                 } else {
00695                         /* otherwise some 4-colour graphics mode */
00696                         if (vga.mode==M_TANDY16) VGA_SetModeNow(M_TANDY4);
00697                         else VGA_SetMode(M_TANDY4);
00698                 }
00699                 tandy_update_palette();
00700         } else {
00701                 VGA_SetMode(M_TANDY_TEXT);
00702         }
00703 }
00704 
00705 static void TandyCheckLineMask(void ) {
00706         if ( vga.tandy.extended_ram & 1 ) {
00707                 vga.tandy.line_mask = 0;
00708         } else if ( vga.tandy.mode_control & 0x2) {
00709                 vga.tandy.line_mask |= 1;
00710         }
00711         if ( vga.tandy.line_mask ) {
00712                 vga.tandy.line_shift = 13;
00713                 vga.tandy.addr_mask = (1 << 13) - 1;
00714         } else {
00715                 vga.tandy.addr_mask = (Bitu)(~0);
00716                 vga.tandy.line_shift = 0;
00717         }
00718 }
00719 
00720 static void write_tandy_reg(Bit8u val) {
00721         switch (vga.tandy.reg_index) {
00722         case 0x0:
00723                 if (machine==MCH_PCJR) {
00724                         vga.tandy.mode_control=val;
00725                         VGA_SetBlinking(val & 0x20);
00726                         PCJr_FindMode();
00727                         if (val&0x8) vga.attr.disabled &= ~1;
00728                         else vga.attr.disabled |= 1;
00729                 } else {
00730                         LOG(LOG_VGAMISC,LOG_NORMAL)("Unhandled Write %2X to tandy reg %X",val,vga.tandy.reg_index);
00731                 }
00732                 break;
00733         case 0x1:       /* Palette mask */
00734                 vga.tandy.palette_mask = val;
00735                 tandy_update_palette();
00736                 break;
00737         case 0x2:       /* Border color */
00738                 vga.tandy.border_color=val;
00739                 break;
00740         case 0x3:       /* More control */
00741                 vga.tandy.gfx_control=val;
00742                 if (machine==MCH_TANDY) TANDY_FindMode();
00743                 else PCJr_FindMode();
00744                 break;
00745         case 0x5:       /* Extended ram page register */
00746                 // Bit 0 enables extended ram
00747                 // Bit 7 Switches clock, 0 -> cga 28.6 , 1 -> mono 32.5
00748                 vga.tandy.extended_ram = val;
00749                 //This is a bit of a hack to enable mapping video memory differently for highres mode
00750                 TandyCheckLineMask();
00751                 VGA_SetupHandlers();
00752                 break;
00753         default:
00754                 if ((vga.tandy.reg_index & 0xf0) == 0x10) { // color palette
00755                         vga.attr.palette[vga.tandy.reg_index-0x10] = val&0xf;
00756                         tandy_update_palette();
00757                 } else
00758                         LOG(LOG_VGAMISC,LOG_NORMAL)("Unhandled Write %2X to tandy reg %X",val,vga.tandy.reg_index);
00759         }
00760 }
00761 
00762 static void write_tandy(Bitu port,Bitu val,Bitu /*iolen*/) {
00763         switch (port) {
00764         case 0x3d8:
00765                 val &= 0x3f; // only bits 0-6 are used
00766                 if (vga.tandy.mode_control ^ val) {
00767                         vga.tandy.mode_control=(Bit8u)val;
00768                         if (val&0x8) vga.attr.disabled &= ~1;
00769                         else vga.attr.disabled |= 1;
00770                         TandyCheckLineMask();
00771                         VGA_SetBlinking(val & 0x20);
00772                         TANDY_FindMode();
00773                         VGA_StartResize();
00774                 }
00775                 break;
00776         case 0x3d9:
00777                 vga.tandy.color_select=val;
00778                 tandy_update_palette();
00779                 break;
00780         case 0x3da:
00781                 vga.tandy.reg_index=(Bit8u)val;
00782                 //if (val&0x10) vga.attr.disabled |= 2;
00783                 //else vga.attr.disabled &= ~2;
00784                 break;
00785 //      case 0x3dd:     //Extended ram page address register:
00786 //              break;
00787         case 0x3de:
00788                 write_tandy_reg((Bit8u)val);
00789                 break;
00790         case 0x3df:
00791                 // CRT/processor page register
00792                 // See the comments on the PCJr version of this register.
00793                 // A difference to it is:
00794                 // Bit 3-5: Processor page CPU_PG
00795                 // The remapped range is 32kB instead of 16. Therefore CPU_PG bit 0
00796                 // appears to be ORed with CPU A14 (to preserve some sort of
00797                 // backwards compatibility?), resulting in odd pages being mapped
00798                 // as 2x16kB. Implemeted in vga_memory.cpp Tandy handler.
00799 
00800                 vga.tandy.line_mask = (Bit8u)(val >> 6);
00801                 vga.tandy.draw_bank = val & ((vga.tandy.line_mask&2) ? 0x6 : 0x7);
00802                 vga.tandy.mem_bank = (val >> 3) & 7;
00803                 TandyCheckLineMask();
00804                 VGA_SetupHandlers();
00805                 break;
00806         }
00807 }
00808 
00809 static void write_pcjr(Bitu port,Bitu val,Bitu /*iolen*/) {
00810         switch (port) {
00811         case 0x3da:
00812                 if (vga.tandy.pcjr_flipflop) write_tandy_reg((Bit8u)val);
00813                 else {
00814                         vga.tandy.reg_index=(Bit8u)val;
00815                         if (vga.tandy.reg_index & 0x10)
00816                                 vga.attr.disabled |= 2;
00817                         else vga.attr.disabled &= ~2;
00818                 }
00819                 vga.tandy.pcjr_flipflop=!vga.tandy.pcjr_flipflop;
00820                 break;
00821         case 0x3df:
00822                 // CRT/processor page register
00823                 
00824                 // Bit 0-2: CRT page PG0-2
00825                 // In one- and two bank modes, bit 0-2 select the 16kB memory
00826                 // area of system RAM that is displayed on the screen.
00827                 // In 4-banked modes, bit 1-2 select the 32kB memory area.
00828                 // Bit 2 only has effect when the PCJR upgrade to 128k is installed.
00829                 
00830                 // Bit 3-5: Processor page CPU_PG
00831                 // Selects the 16kB area of system RAM that is mapped to
00832                 // the B8000h IBM PC video memory window. Since A14-A16 of the 
00833                 // processor are unconditionally replaced with these bits when
00834                 // B8000h is accessed, the 16kB area is mapped to the 32kB
00835                 // range twice in a row. (Scuba Venture writes across the boundary)
00836                 
00837                 // Bit 6-7: Video Address mode
00838                 // 0: CRTC addresses A0-12 directly, accessing 8k characters
00839                 //    (+8k attributes). Used in text modes (one bank).
00840                 //    PG0-2 in effect. 16k range.
00841                 // 1: CRTC A12 is replaced with CRTC RA0 (see max_scanline).
00842                 //    This results in the even/odd scanline two bank system.
00843                 //    PG0-2 in effect. 16k range.
00844                 // 2: Documented as unused. CRTC addresses A0-12, PG0 is replaced
00845                 //    with RA1. Looks like nonsense.
00846                 //    PG1-2 in effect. 32k range which cannot be used completely.
00847                 // 3: CRTC A12 is replaced with CRTC RA0, PG0 is replaced with
00848                 //    CRTC RA1. This results in the 4-bank mode.
00849                 //    PG1-2 in effect. 32k range.
00850 
00851                 vga.tandy.line_mask = (Bit8u)(val >> 6);
00852                 vga.tandy.draw_bank = val & ((vga.tandy.line_mask&2) ? 0x6 : 0x7);
00853                 vga.tandy.mem_bank = (val >> 3) & 7;
00854                 vga.tandy.draw_base = &MemBase[vga.tandy.draw_bank * 16 * 1024];
00855                 vga.tandy.mem_base = &MemBase[vga.tandy.mem_bank * 16 * 1024];
00856                 TandyCheckLineMask();
00857                 VGA_SetupHandlers();
00858                 break;
00859         }
00860 }
00861 
00862 static void CycleHercPal(bool pressed) {
00863         if (!pressed) return;
00864         if (++herc_pal>3) herc_pal=0;
00865         Herc_Palette();
00866 }
00867 
00868 static void CycleMonoCGAPal(bool pressed) {
00869         if (!pressed) return;
00870         if (++mono_cga_pal>3) mono_cga_pal=0;
00871         Mono_CGA_Palette();
00872 }
00873 
00874 static void CycleMonoCGABright(bool pressed) {
00875         if (!pressed) return;
00876         if (++mono_cga_bright>1) mono_cga_bright=0;
00877         Mono_CGA_Palette();
00878 }
00879         
00880 void Herc_Palette(void) {       
00881         switch (herc_pal) {
00882         case 0: // White
00883                 VGA_DAC_SetEntry(0x7,0x2a,0x2a,0x2a);
00884                 VGA_DAC_SetEntry(0xf,0x3f,0x3f,0x3f);
00885                 break;
00886         case 1: // Amber
00887                 VGA_DAC_SetEntry(0x7,0x34,0x20,0x00);
00888                 VGA_DAC_SetEntry(0xf,0x3f,0x34,0x00);
00889                 break;
00890         case 2: // Paper-white
00891                 VGA_DAC_SetEntry(0x7,0x2c,0x2d,0x2c);
00892                 VGA_DAC_SetEntry(0xf,0x3f,0x3f,0x3b);
00893                 break;
00894         case 3: // Green
00895                 VGA_DAC_SetEntry(0x7,0x00,0x26,0x00);
00896                 VGA_DAC_SetEntry(0xf,0x00,0x3f,0x00);
00897                 break;
00898         }
00899         VGA_DAC_CombineColor(1,0x7);
00900         VGA_DAC_CombineColor(2,0xf);
00901 }
00902 
00903 static void HercBlend(bool pressed) {
00904         if (!pressed) return;
00905         vga.herc.blend = !vga.herc.blend;
00906         VGA_SetupDrawing(0);
00907 }
00908 
00909 void Mono_CGA_Palette(void) {   
00910         for (Bit8u ct=0;ct<16;ct++) {
00911                 VGA_DAC_SetEntry(ct,
00912                                                  mono_cga_palettes[2*mono_cga_pal+mono_cga_bright][ct][0],
00913                                                  mono_cga_palettes[2*mono_cga_pal+mono_cga_bright][ct][1],
00914                                                  mono_cga_palettes[2*mono_cga_pal+mono_cga_bright][ct][2]
00915                 );
00916                 VGA_DAC_CombineColor(ct,ct);
00917         }
00918 }
00919 
00920 static void write_hercules(Bitu port,Bitu val,Bitu /*iolen*/) {
00921         switch (port) {
00922         case 0x3b8: {
00923                 // the protected bits can always be cleared but only be set if the 
00924                 // protection bits are set
00925                 if (vga.herc.mode_control&0x2) {
00926                         // already set
00927                         if (!(val&0x2)) {
00928                                 vga.herc.mode_control &= ~0x2;
00929                                 VGA_SetMode(M_HERC_TEXT);
00930                         }
00931                 } else {
00932                         // not set, can only set if protection bit is set
00933                         if ((val & 0x2) && (vga.herc.enable_bits & 0x1)) {
00934                                 vga.herc.mode_control |= 0x2;
00935                                 VGA_SetMode(M_HERC_GFX);
00936                         }
00937                 }
00938                 if (vga.herc.mode_control&0x80) {
00939                         if (!(val&0x80)) {
00940                                 vga.herc.mode_control &= ~0x80;
00941                                 vga.tandy.draw_base = &vga.mem.linear[0];
00942                         }
00943                 } else {
00944                         if ((val & 0x80) && (vga.herc.enable_bits & 0x2)) {
00945                                 vga.herc.mode_control |= 0x80;
00946                                 vga.tandy.draw_base = &vga.mem.linear[32*1024];
00947                         }
00948                 }
00949                 vga.draw.blinking = (val&0x20)!=0;
00950                 vga.herc.mode_control &= 0x82;
00951                 vga.herc.mode_control |= val & ~0x82u;
00952                 break;
00953                 }
00954         case 0x3bf:
00955                 if ( vga.herc.enable_bits ^ val) {
00956                         vga.herc.enable_bits=val;
00957                         // Bit 1 enables the upper 32k of video memory,
00958                         // so update the handlers
00959                         VGA_SetupHandlers();
00960                 }
00961                 break;
00962         }
00963 }
00964 
00965 /* static Bitu read_hercules(Bitu port,Bitu iolen) {
00966         LOG_MSG("read from Herc port %x",port);
00967         return 0;
00968 } */
00969 
00970 Bitu read_herc_status(Bitu /*port*/,Bitu /*iolen*/) {
00971         // 3BAh (R):  Status Register
00972         // bit   0  Horizontal sync
00973         //       1  Light pen status (only some cards)
00974         //       3  Video signal
00975         //     4-6      000: Hercules
00976         //                      001: Hercules Plus
00977         //                      101: Hercules InColor
00978         //                      111: Unknown clone
00979         //       7  Vertical sync inverted
00980 
00981         double timeInFrame = PIC_FullIndex()-vga.draw.delay.framestart;
00982         Bit8u retval=0x72; // Hercules ident; from a working card (Winbond W86855AF)
00983                                         // Another known working card has 0x76 ("KeysoGood", full-length)
00984 
00985     if (machine == MCH_HERC) {
00986         /* NTS: Vertical retrace bit is hercules-specific, as documented.
00987          *      DOSLIB uses this to detect MDA vs Hercules.
00988          *
00989          *      This (and DOSLIB) will be revised when I get around to
00990          *      plugging in my old MDA in one machine and Hercules card
00991          *      in another machine to double-check ---J.C. */
00992         if (timeInFrame < vga.draw.delay.vrstart ||
00993                 timeInFrame > vga.draw.delay.vrend) retval |= 0x80;
00994     }
00995     else {
00996         retval |= 0x80; // bit 7 always set on MDA (right??)
00997     }
00998 
00999         double timeInLine=fmod(timeInFrame,vga.draw.delay.htotal);
01000         if (timeInLine >= vga.draw.delay.hrstart &&
01001                 timeInLine <= vga.draw.delay.hrend) retval |= 0x1;
01002 
01003     if (machine == MCH_HERC) {
01004         // 688 Attack sub checks bit 3 - as a workaround have the bit enabled
01005         // if no sync active (corresponds to a completely white screen)
01006         if ((retval&0x81)==0x80) retval |= 0x8;
01007     }
01008 
01009         return retval;
01010 }
01011 
01012 
01013 void VGA_SetupOther(void) {
01014         Bitu i;
01015         memset( &vga.tandy, 0, sizeof( vga.tandy ));
01016         vga.attr.disabled = 0;
01017         vga.config.bytes_skip=0;
01018 
01019         //Initialize values common for most machines, can be overwritten
01020         vga.tandy.draw_base = vga.mem.linear;
01021         vga.tandy.mem_base = vga.mem.linear;
01022         vga.tandy.addr_mask = 8*1024 - 1;
01023         vga.tandy.line_mask = 3;
01024         vga.tandy.line_shift = 13;
01025 
01026         if (machine==MCH_CGA || machine==MCH_AMSTRAD || IS_TANDY_ARCH) {
01027                 extern Bit8u int10_font_08[256 * 8];
01028                 for (i=0;i<256;i++)     memcpy(&vga.draw.font[i*32],&int10_font_08[i*8],8);
01029                 vga.draw.font_tables[0]=vga.draw.font_tables[1]=vga.draw.font;
01030         }
01031     if (machine==MCH_MCGA) { // MCGA uses a 8x16 font, through double-scanning as if 8x8 CGA text mode
01032         extern Bit8u int10_font_16[256 * 16];
01033         for (i=0;i<256;i++)     memcpy(&vga.draw.font[i*32],&int10_font_16[i*16],16);
01034         vga.draw.font_tables[0]=vga.draw.font_tables[1]=vga.draw.font;
01035     }
01036         if (machine==MCH_CGA || IS_TANDY_ARCH || machine==MCH_HERC || machine==MCH_MDA) {
01037                 IO_RegisterWriteHandler(0x3db,write_lightpen,IO_MB);
01038                 IO_RegisterWriteHandler(0x3dc,write_lightpen,IO_MB);
01039         }
01040         if (machine==MCH_HERC || machine==MCH_MDA) {
01041                 extern Bit8u int10_font_14[256 * 14];
01042                 for (i=0;i<256;i++)     memcpy(&vga.draw.font[i*32],&int10_font_14[i*14],14);
01043                 vga.draw.font_tables[0]=vga.draw.font_tables[1]=vga.draw.font;
01044                 MAPPER_AddHandler(HercBlend,MK_nothing,0,"hercblend","Herc Blend");
01045                 MAPPER_AddHandler(CycleHercPal,MK_nothing,0,"hercpal","Herc Pal");
01046         }
01047         if (machine==MCH_CGA || machine==MCH_MCGA || machine==MCH_AMSTRAD) {
01048                 vga.amstrad.mask_plane = 0x07070707;
01049                 vga.amstrad.write_plane = 0x0F;
01050                 vga.amstrad.read_plane = 0x00;
01051                 vga.amstrad.border_color = 0x00;
01052 
01053                 IO_RegisterWriteHandler(0x3d8,write_cga,IO_MB);
01054                 IO_RegisterWriteHandler(0x3d9,write_cga,IO_MB);
01055 
01056         if (machine == MCH_MCGA) { /* ports 3D8h-3D9h are readable on MCGA */
01057             IO_RegisterReadHandler(0x3d8,read_cga,IO_MB);
01058             IO_RegisterReadHandler(0x3d9,read_cga,IO_MB);
01059         }
01060 
01061                 if (machine == MCH_AMSTRAD) {
01062                         IO_RegisterWriteHandler(0x3dd,write_cga,IO_MB);
01063                         IO_RegisterWriteHandler(0x3de,write_cga,IO_MB);
01064                         IO_RegisterWriteHandler(0x3df,write_cga,IO_MB);
01065                 }
01066 
01067                 if(!mono_cga) {
01068             MAPPER_AddHandler(IncreaseHue,MK_nothing,0,"inchue","Inc Hue");
01069             MAPPER_AddHandler(DecreaseHue,MK_nothing,0,"dechue","Dec Hue");
01070             MAPPER_AddHandler(CGAModel,MK_nothing,0,"cgamodel","CGA Model");
01071             MAPPER_AddHandler(Composite,MK_nothing,0,"cgacomp","CGA Comp");
01072         } else {
01073             MAPPER_AddHandler(CycleMonoCGAPal,MK_nothing,0,"monocgapal","Mono CGA Pal"); 
01074             MAPPER_AddHandler(CycleMonoCGABright,MK_nothing,0,"monocgabright","Mono CGA Bright"); 
01075         }
01076         }
01077         if (machine==MCH_TANDY) {
01078                 write_tandy( 0x3df, 0x0, 0 );
01079                 IO_RegisterWriteHandler(0x3d8,write_tandy,IO_MB);
01080                 IO_RegisterWriteHandler(0x3d9,write_tandy,IO_MB);
01081                 IO_RegisterWriteHandler(0x3da,write_tandy,IO_MB);
01082                 IO_RegisterWriteHandler(0x3de,write_tandy,IO_MB);
01083                 IO_RegisterWriteHandler(0x3df,write_tandy,IO_MB);
01084         }
01085         if (machine==MCH_PCJR) {
01086                 //write_pcjr will setup base address
01087                 write_pcjr( 0x3df, 0x7 | (0x7 << 3), 0 );
01088                 IO_RegisterWriteHandler(0x3da,write_pcjr,IO_MB);
01089                 IO_RegisterWriteHandler(0x3df,write_pcjr,IO_MB);
01090                 // additional CRTC access documented
01091                 IO_RegisterWriteHandler(0x3d0,write_crtc_index_other,IO_MB);
01092                 IO_RegisterWriteHandler(0x3d1,write_crtc_data_other,IO_MB);
01093         }
01094         if (machine==MCH_HERC || machine==MCH_MDA) {
01095                 Bitu base=0x3b0;
01096                 for (Bitu i = 0; i < 4; i++) {
01097                         // The registers are repeated as the address is not decoded properly;
01098                         // The official ports are 3b4, 3b5
01099                         IO_RegisterWriteHandler(base+i*2,write_crtc_index_other,IO_MB);
01100                         IO_RegisterWriteHandler(base+i*2+1,write_crtc_data_other,IO_MB);
01101                         IO_RegisterReadHandler(base+i*2,read_crtc_index_other,IO_MB);
01102                         IO_RegisterReadHandler(base+i*2+1,read_crtc_data_other,IO_MB);
01103                 }
01104                 vga.herc.blend=false;
01105                 vga.herc.enable_bits=0;
01106                 vga.herc.mode_control=0xa; // first mode written will be text mode
01107                 vga.crtc.underline_location = 13;
01108                 IO_RegisterReadHandler(0x3ba,read_herc_status,IO_MB);
01109     }
01110         if (machine==MCH_HERC) {
01111         IO_RegisterWriteHandler(0x3b8,write_hercules,IO_MB);
01112                 IO_RegisterWriteHandler(0x3bf,write_hercules,IO_MB);
01113         }
01114         if (machine==MCH_MDA) {
01115         VGA_SetMode(M_HERC_TEXT); // HACK
01116     }
01117         if (machine==MCH_CGA) {
01118                 Bitu base=0x3d0;
01119                 for (Bitu port_ct=0; port_ct<4; port_ct++) {
01120                         IO_RegisterWriteHandler(base+port_ct*2,write_crtc_index_other,IO_MB);
01121                         IO_RegisterWriteHandler(base+port_ct*2+1,write_crtc_data_other,IO_MB);
01122                         IO_RegisterReadHandler(base+port_ct*2,read_crtc_index_other,IO_MB);
01123                         IO_RegisterReadHandler(base+port_ct*2+1,read_crtc_data_other,IO_MB);
01124                 }
01125         }
01126         if (machine==MCH_MCGA) {
01127                 Bitu base=0x3d0;
01128                 for (Bitu port_ct=0; port_ct<4; port_ct++) {
01129                         IO_RegisterWriteHandler(base+port_ct*2,write_crtc_index_other,IO_MB);
01130                         IO_RegisterWriteHandler(base+port_ct*2+1,write_crtc_data_mcga,IO_MB);
01131                         IO_RegisterReadHandler(base+port_ct*2,read_crtc_index_other,IO_MB);
01132                         IO_RegisterReadHandler(base+port_ct*2+1,read_crtc_data_mcga,IO_MB);
01133                 }
01134         }
01135         if (IS_TANDY_ARCH) {
01136                 Bitu base=0x3d4;
01137                 IO_RegisterWriteHandler(base,write_crtc_index_other,IO_MB);
01138                 IO_RegisterWriteHandler(base+1,write_crtc_data_other,IO_MB);
01139                 IO_RegisterReadHandler(base,read_crtc_index_other,IO_MB);
01140                 IO_RegisterReadHandler(base+1,read_crtc_data_other,IO_MB);
01141         }
01142         if (machine==MCH_AMSTRAD) {
01143                 Bitu base=(machine==MCH_HERC || machine==MCH_MDA) ? 0x3b4 : 0x3d4;
01144                 IO_RegisterWriteHandler(base,write_crtc_index_other,IO_MB);
01145                 IO_RegisterWriteHandler(base+1,write_crtc_data_other,IO_MB);
01146                 IO_RegisterReadHandler(base,read_crtc_index_other,IO_MB);
01147                 IO_RegisterReadHandler(base+1,read_crtc_data_other,IO_MB);
01148 
01149                 // Check for CGA CRTC port mirroring (Prohibition).
01150                 if( base==0x3d4 ) {
01151                         base=0x3d0;
01152                         IO_RegisterWriteHandler(base,write_crtc_index_other,IO_MB);
01153                         IO_RegisterWriteHandler(base+1,write_crtc_data_other,IO_MB);
01154                         IO_RegisterReadHandler(base,read_crtc_index_other,IO_MB);
01155                         IO_RegisterReadHandler(base+1,read_crtc_data_other,IO_MB);
01156                 }
01157         }
01158         // AMSTRAD
01159 }
01160