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00001 // license:GPL-2.0+ 00002 // copyright-holders:Jarek Burczynski 00003 /* 00004 ** 00005 ** File: ymf262.c - software implementation of YMF262 00006 ** FM sound generator type OPL3 00007 ** 00008 ** Copyright Jarek Burczynski 00009 ** 00010 ** Version 0.2 00011 ** 00012 00013 Revision History: 00014 00015 03-03-2003: initial release 00016 - thanks to Olivier Galibert and Chris Hardy for YMF262 and YAC512 chips 00017 - thanks to Stiletto for the datasheets 00018 00019 Features as listed in 4MF262A6 data sheet: 00020 1. Registers are compatible with YM3812 (OPL2) FM sound source. 00021 2. Up to six sounds can be used as four-operator melody sounds for variety. 00022 3. 18 simultaneous melody sounds, or 15 melody sounds with 5 rhythm sounds (with two operators). 00023 4. 6 four-operator melody sounds and 6 two-operator melody sounds, or 6 four-operator melody 00024 sounds, 3 two-operator melody sounds and 5 rhythm sounds (with four operators). 00025 5. 8 selectable waveforms. 00026 6. 4-channel sound output. 00027 7. YMF262 compabile DAC (YAC512) is available. 00028 8. LFO for vibrato and tremolo effedts. 00029 9. 2 programable timers. 00030 10. Shorter register access time compared with YM3812. 00031 11. 5V single supply silicon gate CMOS process. 00032 12. 24 Pin SOP Package (YMF262-M), 48 Pin SQFP Package (YMF262-S). 00033 00034 00035 differences between OPL2 and OPL3 not documented in Yamaha datahasheets: 00036 - sinus table is a little different: the negative part is off by one... 00037 00038 - in order to enable selection of four different waveforms on OPL2 00039 one must set bit 5 in register 0x01(test). 00040 on OPL3 this bit is ignored and 4-waveform select works *always*. 00041 (Don't confuse this with OPL3's 8-waveform select.) 00042 00043 - Envelope Generator: all 15 x rates take zero time on OPL3 00044 (on OPL2 15 0 and 15 1 rates take some time while 15 2 and 15 3 rates 00045 take zero time) 00046 00047 - channel calculations: output of operator 1 is in perfect sync with 00048 output of operator 2 on OPL3; on OPL and OPL2 output of operator 1 00049 is always delayed by one sample compared to output of operator 2 00050 00051 00052 differences between OPL2 and OPL3 shown in datasheets: 00053 - YMF262 does not support CSM mode 00054 00055 00056 */ 00057 00058 #include "emu.h" 00059 #include "ymf262.h" 00060 00061 00062 /* output final shift */ 00063 #if (OPL3_SAMPLE_BITS==16) 00064 #define FINAL_SH (0) 00065 #define MAXOUT (+32767) 00066 #define MINOUT (-32768) 00067 #else 00068 #define FINAL_SH (8) 00069 #define MAXOUT (+127) 00070 #define MINOUT (-128) 00071 #endif 00072 00073 00074 #define FREQ_SH 16 /* 16.16 fixed point (frequency calculations) */ 00075 #define EG_SH 16 /* 16.16 fixed point (EG timing) */ 00076 #define LFO_SH 24 /* 8.24 fixed point (LFO calculations) */ 00077 #define TIMER_SH 16 /* 16.16 fixed point (timers calculations) */ 00078 00079 #define FREQ_MASK ((1<<FREQ_SH)-1) 00080 00081 /* envelope output entries */ 00082 #define ENV_BITS 10 00083 #define ENV_LEN (1<<ENV_BITS) 00084 #define ENV_STEP (128.0/ENV_LEN) 00085 00086 #define MAX_ATT_INDEX ((1<<(ENV_BITS-1))-1) /*511*/ 00087 #define MIN_ATT_INDEX (0) 00088 00089 /* sinwave entries */ 00090 #define SIN_BITS 10 00091 #define SIN_LEN (1<<SIN_BITS) 00092 #define SIN_MASK (SIN_LEN-1) 00093 00094 #define TL_RES_LEN (256) /* 8 bits addressing (real chip) */ 00095 00096 00097 00098 /* register number to channel number , slot offset */ 00099 #define SLOT1 0 00100 #define SLOT2 1 00101 00102 /* Envelope Generator phases */ 00103 00104 #define EG_ATT 4 00105 #define EG_DEC 3 00106 #define EG_SUS 2 00107 #define EG_REL 1 00108 #define EG_OFF 0 00109 00110 /* Routing connections between slots */ 00111 #define CONN_NULL 0 00112 #define CONN_CHAN0 1 00113 #define CONN_PHASEMOD 19 00114 #define CONN_PHASEMOD2 20 00115 00116 namespace { 00117 00118 /* save output as raw 16-bit sample */ 00119 00120 /*#define SAVE_SAMPLE*/ 00121 00122 #ifdef SAVE_SAMPLE 00123 static FILE *sample[1]; 00124 #if 1 /*save to MONO file */ 00125 #define SAVE_ALL_CHANNELS \ 00126 { signed int pom = a; \ 00127 fputc((unsigned short)pom&0xff,sample[0]); \ 00128 fputc(((unsigned short)pom>>8)&0xff,sample[0]); \ 00129 } 00130 #else /*save to STEREO file */ 00131 #define SAVE_ALL_CHANNELS \ 00132 { signed int pom = a; \ 00133 fputc((unsigned short)pom&0xff,sample[0]); \ 00134 fputc(((unsigned short)pom>>8)&0xff,sample[0]); \ 00135 pom = b; \ 00136 fputc((unsigned short)pom&0xff,sample[0]); \ 00137 fputc(((unsigned short)pom>>8)&0xff,sample[0]); \ 00138 } 00139 #endif 00140 #endif 00141 00142 00143 #define OPL3_TYPE_YMF262 (0) /* 36 operators, 8 waveforms */ 00144 00145 00146 struct OPL3_SLOT 00147 { 00148 uint32_t ar; /* attack rate: AR<<2 */ 00149 uint32_t dr; /* decay rate: DR<<2 */ 00150 uint32_t rr; /* release rate:RR<<2 */ 00151 uint8_t KSR; /* key scale rate */ 00152 uint8_t ksl; /* keyscale level */ 00153 uint8_t ksr; /* key scale rate: kcode>>KSR */ 00154 uint8_t mul; /* multiple: mul_tab[ML] */ 00155 00156 /* Phase Generator */ 00157 uint32_t Cnt; /* frequency counter */ 00158 uint32_t Incr; /* frequency counter step */ 00159 uint8_t FB; /* feedback shift value */ 00160 uint8_t conn_enum; /* slot output route */ 00161 int32_t *connect; /* slot output pointer */ 00162 int32_t op1_out[2]; /* slot1 output for feedback */ 00163 uint8_t CON; /* connection (algorithm) type */ 00164 00165 /* Envelope Generator */ 00166 uint8_t eg_type; /* percussive/non-percussive mode */ 00167 uint8_t state; /* phase type */ 00168 uint32_t TL; /* total level: TL << 2 */ 00169 int32_t TLL; /* adjusted now TL */ 00170 int32_t volume; /* envelope counter */ 00171 uint32_t sl; /* sustain level: sl_tab[SL] */ 00172 00173 uint32_t eg_m_ar; /* (attack state) */ 00174 uint8_t eg_sh_ar; /* (attack state) */ 00175 uint8_t eg_sel_ar; /* (attack state) */ 00176 uint32_t eg_m_dr; /* (decay state) */ 00177 uint8_t eg_sh_dr; /* (decay state) */ 00178 uint8_t eg_sel_dr; /* (decay state) */ 00179 uint32_t eg_m_rr; /* (release state) */ 00180 uint8_t eg_sh_rr; /* (release state) */ 00181 uint8_t eg_sel_rr; /* (release state) */ 00182 00183 uint32_t key; /* 0 = KEY OFF, >0 = KEY ON */ 00184 00185 /* LFO */ 00186 uint32_t AMmask; /* LFO Amplitude Modulation enable mask */ 00187 uint8_t vib; /* LFO Phase Modulation enable flag (active high)*/ 00188 00189 /* waveform select */ 00190 uint8_t waveform_number; 00191 unsigned int wavetable; 00192 00193 //unsigned char reserved[128-84];//speedup: pump up the struct size to power of 2 00194 unsigned char reserved[128-100];//speedup: pump up the struct size to power of 2 00195 00196 }; 00197 00198 struct OPL3_CH 00199 { 00200 OPL3_SLOT SLOT[2]; 00201 00202 uint32_t block_fnum; /* block+fnum */ 00203 uint32_t fc; /* Freq. Increment base */ 00204 uint32_t ksl_base; /* KeyScaleLevel Base step */ 00205 uint8_t kcode; /* key code (for key scaling) */ 00206 00207 /* 00208 there are 12 2-operator channels which can be combined in pairs 00209 to form six 4-operator channel, they are: 00210 0 and 3, 00211 1 and 4, 00212 2 and 5, 00213 9 and 12, 00214 10 and 13, 00215 11 and 14 00216 */ 00217 uint8_t extended; /* set to 1 if this channel forms up a 4op channel with another channel(only used by first of pair of channels, ie 0,1,2 and 9,10,11) */ 00218 00219 unsigned char reserved[512-272];//speedup:pump up the struct size to power of 2 00220 00221 }; 00222 00223 /* OPL3 state */ 00224 struct OPL3 00225 { 00226 OPL3_CH P_CH[18]; /* OPL3 chips have 18 channels */ 00227 00228 uint32_t pan[18*4]; /* channels output masks (0xffffffff = enable); 4 masks per one channel */ 00229 uint32_t pan_ctrl_value[18]; /* output control values 1 per one channel (1 value contains 4 masks) */ 00230 00231 signed int chanout[18]; 00232 signed int phase_modulation; /* phase modulation input (SLOT 2) */ 00233 signed int phase_modulation2; /* phase modulation input (SLOT 3 in 4 operator channels) */ 00234 00235 uint32_t eg_cnt; /* global envelope generator counter */ 00236 uint32_t eg_timer; /* global envelope generator counter works at frequency = chipclock/288 (288=8*36) */ 00237 uint32_t eg_timer_add; /* step of eg_timer */ 00238 uint32_t eg_timer_overflow; /* envelope generator timer overflows every 1 sample (on real chip) */ 00239 00240 uint32_t fn_tab[1024]; /* fnumber->increment counter */ 00241 00242 /* LFO */ 00243 uint32_t LFO_AM; 00244 int32_t LFO_PM; 00245 00246 uint8_t lfo_am_depth; 00247 uint8_t lfo_pm_depth_range; 00248 uint32_t lfo_am_cnt; 00249 uint32_t lfo_am_inc; 00250 uint32_t lfo_pm_cnt; 00251 uint32_t lfo_pm_inc; 00252 00253 uint32_t noise_rng; /* 23 bit noise shift register */ 00254 uint32_t noise_p; /* current noise 'phase' */ 00255 uint32_t noise_f; /* current noise period */ 00256 00257 uint8_t OPL3_mode; /* OPL3 extension enable flag */ 00258 00259 uint8_t rhythm; /* Rhythm mode */ 00260 00261 int T[2]; /* timer counters */ 00262 uint8_t st[2]; /* timer enable */ 00263 00264 uint32_t address; /* address register */ 00265 uint8_t status; /* status flag */ 00266 uint8_t statusmask; /* status mask */ 00267 00268 uint8_t nts; /* NTS (note select) */ 00269 00270 /* external event callback handlers */ 00271 OPL3_TIMERHANDLER timer_handler; 00272 device_t *TimerParam; 00273 OPL3_IRQHANDLER IRQHandler; 00274 device_t *IRQParam; 00275 OPL3_UPDATEHANDLER UpdateHandler; 00276 device_t *UpdateParam; 00277 00278 uint8_t type; /* chip type */ 00279 int clock; /* master clock (Hz) */ 00280 int rate; /* sampling rate (Hz) */ 00281 double freqbase; /* frequency base */ 00282 //attotime TimerBase; /* Timer base time (==sampling time)*/ 00283 device_t *device; 00284 00285 /* Optional handlers */ 00286 void SetTimerHandler(OPL3_TIMERHANDLER handler, device_t *device) 00287 { 00288 timer_handler = handler; 00289 TimerParam = device; 00290 } 00291 void SetIRQHandler(OPL3_IRQHANDLER handler, device_t *device) 00292 { 00293 IRQHandler = handler; 00294 IRQParam = device; 00295 } 00296 void SetUpdateHandler(OPL3_UPDATEHANDLER handler, device_t *device) 00297 { 00298 UpdateHandler = handler; 00299 UpdateParam = device; 00300 } 00301 }; 00302 00303 } // anonymous namespace 00304 00305 00306 00307 /* mapping of register number (offset) to slot number used by the emulator */ 00308 static const int slot_array[32]= 00309 { 00310 0, 2, 4, 1, 3, 5,-1,-1, 00311 6, 8,10, 7, 9,11,-1,-1, 00312 12,14,16,13,15,17,-1,-1, 00313 -1,-1,-1,-1,-1,-1,-1,-1 00314 }; 00315 00316 /* key scale level */ 00317 /* table is 3dB/octave , DV converts this into 6dB/octave */ 00318 /* 0.1875 is bit 0 weight of the envelope counter (volume) expressed in the 'decibel' scale */ 00319 #define DV (0.1875/2.0) 00320 static const double ksl_tab[8*16]= 00321 { 00322 /* OCT 0 */ 00323 0.000/DV, 0.000/DV, 0.000/DV, 0.000/DV, 00324 0.000/DV, 0.000/DV, 0.000/DV, 0.000/DV, 00325 0.000/DV, 0.000/DV, 0.000/DV, 0.000/DV, 00326 0.000/DV, 0.000/DV, 0.000/DV, 0.000/DV, 00327 /* OCT 1 */ 00328 0.000/DV, 0.000/DV, 0.000/DV, 0.000/DV, 00329 0.000/DV, 0.000/DV, 0.000/DV, 0.000/DV, 00330 0.000/DV, 0.750/DV, 1.125/DV, 1.500/DV, 00331 1.875/DV, 2.250/DV, 2.625/DV, 3.000/DV, 00332 /* OCT 2 */ 00333 0.000/DV, 0.000/DV, 0.000/DV, 0.000/DV, 00334 0.000/DV, 1.125/DV, 1.875/DV, 2.625/DV, 00335 3.000/DV, 3.750/DV, 4.125/DV, 4.500/DV, 00336 4.875/DV, 5.250/DV, 5.625/DV, 6.000/DV, 00337 /* OCT 3 */ 00338 0.000/DV, 0.000/DV, 0.000/DV, 1.875/DV, 00339 3.000/DV, 4.125/DV, 4.875/DV, 5.625/DV, 00340 6.000/DV, 6.750/DV, 7.125/DV, 7.500/DV, 00341 7.875/DV, 8.250/DV, 8.625/DV, 9.000/DV, 00342 /* OCT 4 */ 00343 0.000/DV, 0.000/DV, 3.000/DV, 4.875/DV, 00344 6.000/DV, 7.125/DV, 7.875/DV, 8.625/DV, 00345 9.000/DV, 9.750/DV,10.125/DV,10.500/DV, 00346 10.875/DV,11.250/DV,11.625/DV,12.000/DV, 00347 /* OCT 5 */ 00348 0.000/DV, 3.000/DV, 6.000/DV, 7.875/DV, 00349 9.000/DV,10.125/DV,10.875/DV,11.625/DV, 00350 12.000/DV,12.750/DV,13.125/DV,13.500/DV, 00351 13.875/DV,14.250/DV,14.625/DV,15.000/DV, 00352 /* OCT 6 */ 00353 0.000/DV, 6.000/DV, 9.000/DV,10.875/DV, 00354 12.000/DV,13.125/DV,13.875/DV,14.625/DV, 00355 15.000/DV,15.750/DV,16.125/DV,16.500/DV, 00356 16.875/DV,17.250/DV,17.625/DV,18.000/DV, 00357 /* OCT 7 */ 00358 0.000/DV, 9.000/DV,12.000/DV,13.875/DV, 00359 15.000/DV,16.125/DV,16.875/DV,17.625/DV, 00360 18.000/DV,18.750/DV,19.125/DV,19.500/DV, 00361 19.875/DV,20.250/DV,20.625/DV,21.000/DV 00362 }; 00363 #undef DV 00364 00365 /* 0 / 3.0 / 1.5 / 6.0 dB/OCT */ 00366 static const uint32_t ksl_shift[4] = { 31, 1, 2, 0 }; 00367 00368 00369 /* sustain level table (3dB per step) */ 00370 /* 0 - 15: 0, 3, 6, 9,12,15,18,21,24,27,30,33,36,39,42,93 (dB)*/ 00371 #define SC(db) (uint32_t) ( db * (2.0/ENV_STEP) ) 00372 static const uint32_t sl_tab[16]={ 00373 SC( 0),SC( 1),SC( 2),SC(3 ),SC(4 ),SC(5 ),SC(6 ),SC( 7), 00374 SC( 8),SC( 9),SC(10),SC(11),SC(12),SC(13),SC(14),SC(31) 00375 }; 00376 #undef SC 00377 00378 00379 #define RATE_STEPS (8) 00380 static const unsigned char eg_inc[15*RATE_STEPS]={ 00381 /*cycle:0 1 2 3 4 5 6 7*/ 00382 00383 /* 0 */ 0,1, 0,1, 0,1, 0,1, /* rates 00..12 0 (increment by 0 or 1) */ 00384 /* 1 */ 0,1, 0,1, 1,1, 0,1, /* rates 00..12 1 */ 00385 /* 2 */ 0,1, 1,1, 0,1, 1,1, /* rates 00..12 2 */ 00386 /* 3 */ 0,1, 1,1, 1,1, 1,1, /* rates 00..12 3 */ 00387 00388 /* 4 */ 1,1, 1,1, 1,1, 1,1, /* rate 13 0 (increment by 1) */ 00389 /* 5 */ 1,1, 1,2, 1,1, 1,2, /* rate 13 1 */ 00390 /* 6 */ 1,2, 1,2, 1,2, 1,2, /* rate 13 2 */ 00391 /* 7 */ 1,2, 2,2, 1,2, 2,2, /* rate 13 3 */ 00392 00393 /* 8 */ 2,2, 2,2, 2,2, 2,2, /* rate 14 0 (increment by 2) */ 00394 /* 9 */ 2,2, 2,4, 2,2, 2,4, /* rate 14 1 */ 00395 /*10 */ 2,4, 2,4, 2,4, 2,4, /* rate 14 2 */ 00396 /*11 */ 2,4, 4,4, 2,4, 4,4, /* rate 14 3 */ 00397 00398 /*12 */ 4,4, 4,4, 4,4, 4,4, /* rates 15 0, 15 1, 15 2, 15 3 for decay */ 00399 /*13 */ 8,8, 8,8, 8,8, 8,8, /* rates 15 0, 15 1, 15 2, 15 3 for attack (zero time) */ 00400 /*14 */ 0,0, 0,0, 0,0, 0,0, /* infinity rates for attack and decay(s) */ 00401 }; 00402 00403 00404 #define O(a) (a*RATE_STEPS) 00405 00406 /* note that there is no O(13) in this table - it's directly in the code */ 00407 static const unsigned char eg_rate_select[16+64+16]={ /* Envelope Generator rates (16 + 64 rates + 16 RKS) */ 00408 /* 16 infinite time rates */ 00409 O(14),O(14),O(14),O(14),O(14),O(14),O(14),O(14), 00410 O(14),O(14),O(14),O(14),O(14),O(14),O(14),O(14), 00411 00412 /* rates 00-12 */ 00413 O( 0),O( 1),O( 2),O( 3), 00414 O( 0),O( 1),O( 2),O( 3), 00415 O( 0),O( 1),O( 2),O( 3), 00416 O( 0),O( 1),O( 2),O( 3), 00417 O( 0),O( 1),O( 2),O( 3), 00418 O( 0),O( 1),O( 2),O( 3), 00419 O( 0),O( 1),O( 2),O( 3), 00420 O( 0),O( 1),O( 2),O( 3), 00421 O( 0),O( 1),O( 2),O( 3), 00422 O( 0),O( 1),O( 2),O( 3), 00423 O( 0),O( 1),O( 2),O( 3), 00424 O( 0),O( 1),O( 2),O( 3), 00425 O( 0),O( 1),O( 2),O( 3), 00426 00427 /* rate 13 */ 00428 O( 4),O( 5),O( 6),O( 7), 00429 00430 /* rate 14 */ 00431 O( 8),O( 9),O(10),O(11), 00432 00433 /* rate 15 */ 00434 O(12),O(12),O(12),O(12), 00435 00436 /* 16 dummy rates (same as 15 3) */ 00437 O(12),O(12),O(12),O(12),O(12),O(12),O(12),O(12), 00438 O(12),O(12),O(12),O(12),O(12),O(12),O(12),O(12), 00439 00440 }; 00441 #undef O 00442 00443 /*rate 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 */ 00444 /*shift 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0, 0, 0, 0 */ 00445 /*mask 4095, 2047, 1023, 511, 255, 127, 63, 31, 15, 7, 3, 1, 0, 0, 0, 0 */ 00446 00447 #define O(a) (a*1) 00448 static const unsigned char eg_rate_shift[16+64+16]={ /* Envelope Generator counter shifts (16 + 64 rates + 16 RKS) */ 00449 /* 16 infinite time rates */ 00450 O(0),O(0),O(0),O(0),O(0),O(0),O(0),O(0), 00451 O(0),O(0),O(0),O(0),O(0),O(0),O(0),O(0), 00452 00453 /* rates 00-12 */ 00454 O(12),O(12),O(12),O(12), 00455 O(11),O(11),O(11),O(11), 00456 O(10),O(10),O(10),O(10), 00457 O( 9),O( 9),O( 9),O( 9), 00458 O( 8),O( 8),O( 8),O( 8), 00459 O( 7),O( 7),O( 7),O( 7), 00460 O( 6),O( 6),O( 6),O( 6), 00461 O( 5),O( 5),O( 5),O( 5), 00462 O( 4),O( 4),O( 4),O( 4), 00463 O( 3),O( 3),O( 3),O( 3), 00464 O( 2),O( 2),O( 2),O( 2), 00465 O( 1),O( 1),O( 1),O( 1), 00466 O( 0),O( 0),O( 0),O( 0), 00467 00468 /* rate 13 */ 00469 O( 0),O( 0),O( 0),O( 0), 00470 00471 /* rate 14 */ 00472 O( 0),O( 0),O( 0),O( 0), 00473 00474 /* rate 15 */ 00475 O( 0),O( 0),O( 0),O( 0), 00476 00477 /* 16 dummy rates (same as 15 3) */ 00478 O( 0),O( 0),O( 0),O( 0),O( 0),O( 0),O( 0),O( 0), 00479 O( 0),O( 0),O( 0),O( 0),O( 0),O( 0),O( 0),O( 0), 00480 00481 }; 00482 #undef O 00483 00484 00485 /* multiple table */ 00486 #define ML 2 00487 static const uint8_t mul_tab[16]= { 00488 /* 1/2, 1, 2, 3, 4, 5, 6, 7, 8, 9,10,10,12,12,15,15 */ 00489 ML/2, 1*ML, 2*ML, 3*ML, 4*ML, 5*ML, 6*ML, 7*ML, 00490 8*ML, 9*ML,10*ML,10*ML,12*ML,12*ML,15*ML,15*ML 00491 }; 00492 #undef ML 00493 00494 /* TL_TAB_LEN is calculated as: 00495 00496 * (12+1)=13 - sinus amplitude bits (Y axis) 00497 * additional 1: to compensate for calculations of negative part of waveform 00498 * (if we don't add it then the greatest possible _negative_ value would be -2 00499 * and we really need -1 for waveform #7) 00500 * 2 - sinus sign bit (Y axis) 00501 * TL_RES_LEN - sinus resolution (X axis) 00502 */ 00503 #define TL_TAB_LEN (13*2*TL_RES_LEN) 00504 static signed int tl_tab[TL_TAB_LEN]; 00505 00506 #define ENV_QUIET (TL_TAB_LEN>>4) 00507 00508 /* sin waveform table in 'decibel' scale */ 00509 /* there are eight waveforms on OPL3 chips */ 00510 static unsigned int sin_tab[SIN_LEN * 8]; 00511 00512 00513 /* LFO Amplitude Modulation table (verified on real YM3812) 00514 27 output levels (triangle waveform); 1 level takes one of: 192, 256 or 448 samples 00515 00516 Length: 210 elements. 00517 00518 Each of the elements has to be repeated 00519 exactly 64 times (on 64 consecutive samples). 00520 The whole table takes: 64 * 210 = 13440 samples. 00521 00522 When AM = 1 data is used directly 00523 When AM = 0 data is divided by 4 before being used (losing precision is important) 00524 */ 00525 00526 #define LFO_AM_TAB_ELEMENTS 210 00527 00528 static const uint8_t lfo_am_table[LFO_AM_TAB_ELEMENTS] = { 00529 0,0,0,0,0,0,0, 00530 1,1,1,1, 00531 2,2,2,2, 00532 3,3,3,3, 00533 4,4,4,4, 00534 5,5,5,5, 00535 6,6,6,6, 00536 7,7,7,7, 00537 8,8,8,8, 00538 9,9,9,9, 00539 10,10,10,10, 00540 11,11,11,11, 00541 12,12,12,12, 00542 13,13,13,13, 00543 14,14,14,14, 00544 15,15,15,15, 00545 16,16,16,16, 00546 17,17,17,17, 00547 18,18,18,18, 00548 19,19,19,19, 00549 20,20,20,20, 00550 21,21,21,21, 00551 22,22,22,22, 00552 23,23,23,23, 00553 24,24,24,24, 00554 25,25,25,25, 00555 26,26,26, 00556 25,25,25,25, 00557 24,24,24,24, 00558 23,23,23,23, 00559 22,22,22,22, 00560 21,21,21,21, 00561 20,20,20,20, 00562 19,19,19,19, 00563 18,18,18,18, 00564 17,17,17,17, 00565 16,16,16,16, 00566 15,15,15,15, 00567 14,14,14,14, 00568 13,13,13,13, 00569 12,12,12,12, 00570 11,11,11,11, 00571 10,10,10,10, 00572 9,9,9,9, 00573 8,8,8,8, 00574 7,7,7,7, 00575 6,6,6,6, 00576 5,5,5,5, 00577 4,4,4,4, 00578 3,3,3,3, 00579 2,2,2,2, 00580 1,1,1,1 00581 }; 00582 00583 /* LFO Phase Modulation table (verified on real YM3812) */ 00584 static const int8_t lfo_pm_table[8*8*2] = { 00585 /* FNUM2/FNUM = 00 0xxxxxxx (0x0000) */ 00586 0, 0, 0, 0, 0, 0, 0, 0, /*LFO PM depth = 0*/ 00587 0, 0, 0, 0, 0, 0, 0, 0, /*LFO PM depth = 1*/ 00588 00589 /* FNUM2/FNUM = 00 1xxxxxxx (0x0080) */ 00590 0, 0, 0, 0, 0, 0, 0, 0, /*LFO PM depth = 0*/ 00591 1, 0, 0, 0,-1, 0, 0, 0, /*LFO PM depth = 1*/ 00592 00593 /* FNUM2/FNUM = 01 0xxxxxxx (0x0100) */ 00594 1, 0, 0, 0,-1, 0, 0, 0, /*LFO PM depth = 0*/ 00595 2, 1, 0,-1,-2,-1, 0, 1, /*LFO PM depth = 1*/ 00596 00597 /* FNUM2/FNUM = 01 1xxxxxxx (0x0180) */ 00598 1, 0, 0, 0,-1, 0, 0, 0, /*LFO PM depth = 0*/ 00599 3, 1, 0,-1,-3,-1, 0, 1, /*LFO PM depth = 1*/ 00600 00601 /* FNUM2/FNUM = 10 0xxxxxxx (0x0200) */ 00602 2, 1, 0,-1,-2,-1, 0, 1, /*LFO PM depth = 0*/ 00603 4, 2, 0,-2,-4,-2, 0, 2, /*LFO PM depth = 1*/ 00604 00605 /* FNUM2/FNUM = 10 1xxxxxxx (0x0280) */ 00606 2, 1, 0,-1,-2,-1, 0, 1, /*LFO PM depth = 0*/ 00607 5, 2, 0,-2,-5,-2, 0, 2, /*LFO PM depth = 1*/ 00608 00609 /* FNUM2/FNUM = 11 0xxxxxxx (0x0300) */ 00610 3, 1, 0,-1,-3,-1, 0, 1, /*LFO PM depth = 0*/ 00611 6, 3, 0,-3,-6,-3, 0, 3, /*LFO PM depth = 1*/ 00612 00613 /* FNUM2/FNUM = 11 1xxxxxxx (0x0380) */ 00614 3, 1, 0,-1,-3,-1, 0, 1, /*LFO PM depth = 0*/ 00615 7, 3, 0,-3,-7,-3, 0, 3 /*LFO PM depth = 1*/ 00616 }; 00617 00618 00619 /* lock level of common table */ 00620 static int num_lock = 0; 00621 00622 /* work table */ 00623 #define SLOT7_1 (&chip->P_CH[7].SLOT[SLOT1]) 00624 #define SLOT7_2 (&chip->P_CH[7].SLOT[SLOT2]) 00625 #define SLOT8_1 (&chip->P_CH[8].SLOT[SLOT1]) 00626 #define SLOT8_2 (&chip->P_CH[8].SLOT[SLOT2]) 00627 00628 00629 static inline void OPL3_SLOT_CONNECT(OPL3 *chip, OPL3_SLOT *slot) { 00630 if (slot->conn_enum == CONN_NULL) { 00631 slot->connect = 0; 00632 } else if (slot->conn_enum >= CONN_CHAN0 && slot->conn_enum < CONN_PHASEMOD) { 00633 slot->connect = &chip->chanout[slot->conn_enum]; 00634 } else if (slot->conn_enum == CONN_PHASEMOD) { 00635 slot->connect = &chip->phase_modulation; 00636 } else if (slot->conn_enum == CONN_PHASEMOD2) { 00637 slot->connect = &chip->phase_modulation2; 00638 } 00639 } 00640 00641 static inline int limit( int val, int max, int min ) { 00642 if ( val > max ) 00643 val = max; 00644 else if ( val < min ) 00645 val = min; 00646 00647 return val; 00648 } 00649 00650 00651 /* status set and IRQ handling */ 00652 static inline void OPL3_STATUS_SET(OPL3 *chip,int flag) 00653 { 00654 /* set status flag masking out disabled IRQs */ 00655 chip->status |= (flag & chip->statusmask); 00656 if(!(chip->status & 0x80)) 00657 { 00658 if(chip->status & 0x7f) 00659 { /* IRQ on */ 00660 chip->status |= 0x80; 00661 /* callback user interrupt handler (IRQ is OFF to ON) */ 00662 if(chip->IRQHandler) (chip->IRQHandler)(chip->IRQParam,1); 00663 } 00664 } 00665 } 00666 00667 /* status reset and IRQ handling */ 00668 static inline void OPL3_STATUS_RESET(OPL3 *chip,int flag) 00669 { 00670 /* reset status flag */ 00671 chip->status &= ~flag; 00672 if(chip->status & 0x80) 00673 { 00674 if (!(chip->status & 0x7f)) 00675 { 00676 chip->status &= 0x7f; 00677 /* callback user interrupt handler (IRQ is ON to OFF) */ 00678 if(chip->IRQHandler) (chip->IRQHandler)(chip->IRQParam,0); 00679 } 00680 } 00681 } 00682 00683 /* IRQ mask set */ 00684 static inline void OPL3_STATUSMASK_SET(OPL3 *chip,int flag) 00685 { 00686 chip->statusmask = flag; 00687 /* IRQ handling check */ 00688 OPL3_STATUS_SET(chip,0); 00689 OPL3_STATUS_RESET(chip,0); 00690 } 00691 00692 00693 /* advance LFO to next sample */ 00694 static inline void advance_lfo(OPL3 *chip) 00695 { 00696 uint8_t tmp; 00697 00698 /* LFO */ 00699 chip->lfo_am_cnt += chip->lfo_am_inc; 00700 if (chip->lfo_am_cnt >= ((uint32_t)LFO_AM_TAB_ELEMENTS<<LFO_SH) ) /* lfo_am_table is 210 elements long */ 00701 chip->lfo_am_cnt -= ((uint32_t)LFO_AM_TAB_ELEMENTS<<LFO_SH); 00702 00703 tmp = lfo_am_table[ chip->lfo_am_cnt >> LFO_SH ]; 00704 00705 if (chip->lfo_am_depth) 00706 chip->LFO_AM = tmp; 00707 else 00708 chip->LFO_AM = tmp>>2; 00709 00710 chip->lfo_pm_cnt += chip->lfo_pm_inc; 00711 chip->LFO_PM = ((chip->lfo_pm_cnt>>LFO_SH) & 7) | chip->lfo_pm_depth_range; 00712 } 00713 00714 /* advance to next sample */ 00715 static inline void advance(OPL3 *chip) 00716 { 00717 OPL3_CH *CH; 00718 OPL3_SLOT *op; 00719 int i; 00720 00721 chip->eg_timer += chip->eg_timer_add; 00722 00723 while (chip->eg_timer >= chip->eg_timer_overflow) 00724 { 00725 chip->eg_timer -= chip->eg_timer_overflow; 00726 00727 chip->eg_cnt++; 00728 00729 for (i=0; i<9*2*2; i++) 00730 { 00731 CH = &chip->P_CH[i/2]; 00732 op = &CH->SLOT[i&1]; 00733 #if 1 00734 /* Envelope Generator */ 00735 switch(op->state) 00736 { 00737 case EG_ATT: /* attack phase */ 00738 // if ( !(chip->eg_cnt & ((1<<op->eg_sh_ar)-1) ) ) 00739 if ( !(chip->eg_cnt & op->eg_m_ar) ) 00740 { 00741 op->volume += (~op->volume * 00742 (eg_inc[op->eg_sel_ar + ((chip->eg_cnt>>op->eg_sh_ar)&7)]) 00743 ) >>3; 00744 00745 if (op->volume <= MIN_ATT_INDEX) 00746 { 00747 op->volume = MIN_ATT_INDEX; 00748 op->state = EG_DEC; 00749 } 00750 00751 } 00752 break; 00753 00754 case EG_DEC: /* decay phase */ 00755 // if ( !(chip->eg_cnt & ((1<<op->eg_sh_dr)-1) ) ) 00756 if ( !(chip->eg_cnt & op->eg_m_dr) ) 00757 { 00758 op->volume += eg_inc[op->eg_sel_dr + ((chip->eg_cnt>>op->eg_sh_dr)&7)]; 00759 00760 if ( (uint32_t)op->volume >= op->sl ) 00761 op->state = EG_SUS; 00762 00763 } 00764 break; 00765 00766 case EG_SUS: /* sustain phase */ 00767 00768 /* this is important behaviour: 00769 one can change percusive/non-percussive modes on the fly and 00770 the chip will remain in sustain phase - verified on real YM3812 */ 00771 00772 if(op->eg_type) /* non-percussive mode */ 00773 { 00774 /* do nothing */ 00775 } 00776 else /* percussive mode */ 00777 { 00778 /* during sustain phase chip adds Release Rate (in percussive mode) */ 00779 // if ( !(chip->eg_cnt & ((1<<op->eg_sh_rr)-1) ) ) 00780 if ( !(chip->eg_cnt & op->eg_m_rr) ) 00781 { 00782 op->volume += eg_inc[op->eg_sel_rr + ((chip->eg_cnt>>op->eg_sh_rr)&7)]; 00783 00784 if ( op->volume >= MAX_ATT_INDEX ) 00785 op->volume = MAX_ATT_INDEX; 00786 } 00787 /* else do nothing in sustain phase */ 00788 } 00789 break; 00790 00791 case EG_REL: /* release phase */ 00792 // if ( !(chip->eg_cnt & ((1<<op->eg_sh_rr)-1) ) ) 00793 if ( !(chip->eg_cnt & op->eg_m_rr) ) 00794 { 00795 op->volume += eg_inc[op->eg_sel_rr + ((chip->eg_cnt>>op->eg_sh_rr)&7)]; 00796 00797 if ( op->volume >= MAX_ATT_INDEX ) 00798 { 00799 op->volume = MAX_ATT_INDEX; 00800 op->state = EG_OFF; 00801 } 00802 00803 } 00804 break; 00805 00806 default: 00807 break; 00808 } 00809 #endif 00810 } 00811 } 00812 00813 for (i=0; i<9*2*2; i++) 00814 { 00815 CH = &chip->P_CH[i/2]; 00816 op = &CH->SLOT[i&1]; 00817 00818 /* Phase Generator */ 00819 if(op->vib) 00820 { 00821 uint8_t block; 00822 unsigned int block_fnum = CH->block_fnum; 00823 00824 unsigned int fnum_lfo = (block_fnum&0x0380) >> 7; 00825 00826 signed int lfo_fn_table_index_offset = lfo_pm_table[chip->LFO_PM + 16*fnum_lfo ]; 00827 00828 if (lfo_fn_table_index_offset) /* LFO phase modulation active */ 00829 { 00830 block_fnum += lfo_fn_table_index_offset; 00831 block = (block_fnum&0x1c00) >> 10; 00832 op->Cnt += (chip->fn_tab[block_fnum&0x03ff] >> (7-block)) * op->mul; 00833 } 00834 else /* LFO phase modulation = zero */ 00835 { 00836 op->Cnt += op->Incr; 00837 } 00838 } 00839 else /* LFO phase modulation disabled for this operator */ 00840 { 00841 op->Cnt += op->Incr; 00842 } 00843 } 00844 00845 /* The Noise Generator of the YM3812 is 23-bit shift register. 00846 * Period is equal to 2^23-2 samples. 00847 * Register works at sampling frequency of the chip, so output 00848 * can change on every sample. 00849 * 00850 * Output of the register and input to the bit 22 is: 00851 * bit0 XOR bit14 XOR bit15 XOR bit22 00852 * 00853 * Simply use bit 22 as the noise output. 00854 */ 00855 00856 chip->noise_p += chip->noise_f; 00857 i = chip->noise_p >> FREQ_SH; /* number of events (shifts of the shift register) */ 00858 chip->noise_p &= FREQ_MASK; 00859 while (i) 00860 { 00861 /* 00862 uint32_t j; 00863 j = ( (chip->noise_rng) ^ (chip->noise_rng>>14) ^ (chip->noise_rng>>15) ^ (chip->noise_rng>>22) ) & 1; 00864 chip->noise_rng = (j<<22) | (chip->noise_rng>>1); 00865 */ 00866 00867 /* 00868 Instead of doing all the logic operations above, we 00869 use a trick here (and use bit 0 as the noise output). 00870 The difference is only that the noise bit changes one 00871 step ahead. This doesn't matter since we don't know 00872 what is real state of the noise_rng after the reset. 00873 */ 00874 00875 if (chip->noise_rng & 1) chip->noise_rng ^= 0x800302; 00876 chip->noise_rng >>= 1; 00877 00878 i--; 00879 } 00880 } 00881 00882 00883 static inline signed int op_calc(uint32_t phase, unsigned int env, signed int pm, unsigned int wave_tab) 00884 { 00885 uint32_t p; 00886 00887 p = (env<<4) + sin_tab[wave_tab + ((((signed int)((phase & ~FREQ_MASK) + (pm<<16))) >> FREQ_SH ) & SIN_MASK) ]; 00888 00889 if (p >= TL_TAB_LEN) 00890 return 0; 00891 return tl_tab[p]; 00892 } 00893 00894 static inline signed int op_calc1(uint32_t phase, unsigned int env, signed int pm, unsigned int wave_tab) 00895 { 00896 uint32_t p; 00897 00898 p = (env<<4) + sin_tab[wave_tab + ((((signed int)((phase & ~FREQ_MASK) + pm))>>FREQ_SH) & SIN_MASK)]; 00899 00900 if (p >= TL_TAB_LEN) 00901 return 0; 00902 return tl_tab[p]; 00903 } 00904 00905 00906 #define volume_calc(OP) ((OP)->TLL + ((uint32_t)(OP)->volume) + (chip->LFO_AM & (OP)->AMmask)) 00907 00908 /* calculate output of a standard 2 operator channel 00909 (or 1st part of a 4-op channel) */ 00910 static inline void chan_calc( OPL3 *chip, OPL3_CH *CH ) 00911 { 00912 OPL3_SLOT *SLOT; 00913 unsigned int env; 00914 signed int out; 00915 00916 chip->phase_modulation = 0; 00917 chip->phase_modulation2= 0; 00918 00919 /* SLOT 1 */ 00920 SLOT = &CH->SLOT[SLOT1]; 00921 env = volume_calc(SLOT); 00922 out = SLOT->op1_out[0] + SLOT->op1_out[1]; 00923 SLOT->op1_out[0] = SLOT->op1_out[1]; 00924 SLOT->op1_out[1] = 0; 00925 if (env < ENV_QUIET) 00926 { 00927 if (!SLOT->FB) 00928 out = 0; 00929 SLOT->op1_out[1] = op_calc1(SLOT->Cnt, env, (out<<SLOT->FB), SLOT->wavetable ); 00930 } 00931 if (SLOT->connect) { 00932 *SLOT->connect += SLOT->op1_out[1]; 00933 } 00934 //logerror("out0=%5i vol0=%4i ", SLOT->op1_out[1], env ); 00935 00936 /* SLOT 2 */ 00937 SLOT++; 00938 env = volume_calc(SLOT); 00939 if ((env < ENV_QUIET) && SLOT->connect) 00940 *SLOT->connect += op_calc(SLOT->Cnt, env, chip->phase_modulation, SLOT->wavetable); 00941 00942 //logerror("out1=%5i vol1=%4i\n", op_calc(SLOT->Cnt, env, chip->phase_modulation, SLOT->wavetable), env ); 00943 00944 } 00945 00946 /* calculate output of a 2nd part of 4-op channel */ 00947 static inline void chan_calc_ext( OPL3 *chip, OPL3_CH *CH ) 00948 { 00949 OPL3_SLOT *SLOT; 00950 unsigned int env; 00951 00952 chip->phase_modulation = 0; 00953 00954 /* SLOT 1 */ 00955 SLOT = &CH->SLOT[SLOT1]; 00956 env = volume_calc(SLOT); 00957 if (env < ENV_QUIET && SLOT->connect) 00958 *SLOT->connect += op_calc(SLOT->Cnt, env, chip->phase_modulation2, SLOT->wavetable ); 00959 00960 /* SLOT 2 */ 00961 SLOT++; 00962 env = volume_calc(SLOT); 00963 if (env < ENV_QUIET && SLOT->connect) 00964 *SLOT->connect += op_calc(SLOT->Cnt, env, chip->phase_modulation, SLOT->wavetable); 00965 00966 } 00967 00968 /* 00969 operators used in the rhythm sounds generation process: 00970 00971 Envelope Generator: 00972 00973 channel operator register number Bass High Snare Tom Top 00974 / slot number TL ARDR SLRR Wave Drum Hat Drum Tom Cymbal 00975 6 / 0 12 50 70 90 f0 + 00976 6 / 1 15 53 73 93 f3 + 00977 7 / 0 13 51 71 91 f1 + 00978 7 / 1 16 54 74 94 f4 + 00979 8 / 0 14 52 72 92 f2 + 00980 8 / 1 17 55 75 95 f5 + 00981 00982 Phase Generator: 00983 00984 channel operator register number Bass High Snare Tom Top 00985 / slot number MULTIPLE Drum Hat Drum Tom Cymbal 00986 6 / 0 12 30 + 00987 6 / 1 15 33 + 00988 7 / 0 13 31 + + + 00989 7 / 1 16 34 ----- n o t u s e d ----- 00990 8 / 0 14 32 + 00991 8 / 1 17 35 + + 00992 00993 channel operator register number Bass High Snare Tom Top 00994 number number BLK/FNUM2 FNUM Drum Hat Drum Tom Cymbal 00995 6 12,15 B6 A6 + 00996 00997 7 13,16 B7 A7 + + + 00998 00999 8 14,17 B8 A8 + + + 01000 01001 */ 01002 01003 /* calculate rhythm */ 01004 01005 static inline void chan_calc_rhythm( OPL3 *chip, OPL3_CH *CH, unsigned int noise ) 01006 { 01007 OPL3_SLOT *SLOT; 01008 signed int *chanout = chip->chanout; 01009 signed int out; 01010 unsigned int env; 01011 01012 01013 /* Bass Drum (verified on real YM3812): 01014 - depends on the channel 6 'connect' register: 01015 when connect = 0 it works the same as in normal (non-rhythm) mode (op1->op2->out) 01016 when connect = 1 _only_ operator 2 is present on output (op2->out), operator 1 is ignored 01017 - output sample always is multiplied by 2 01018 */ 01019 01020 chip->phase_modulation = 0; 01021 01022 /* SLOT 1 */ 01023 SLOT = &CH[6].SLOT[SLOT1]; 01024 env = volume_calc(SLOT); 01025 01026 out = SLOT->op1_out[0] + SLOT->op1_out[1]; 01027 SLOT->op1_out[0] = SLOT->op1_out[1]; 01028 01029 if (!SLOT->CON) 01030 chip->phase_modulation = SLOT->op1_out[0]; 01031 //else ignore output of operator 1 01032 01033 SLOT->op1_out[1] = 0; 01034 if( env < ENV_QUIET ) 01035 { 01036 if (!SLOT->FB) 01037 out = 0; 01038 SLOT->op1_out[1] = op_calc1(SLOT->Cnt, env, (out<<SLOT->FB), SLOT->wavetable ); 01039 } 01040 01041 /* SLOT 2 */ 01042 SLOT++; 01043 env = volume_calc(SLOT); 01044 if( env < ENV_QUIET ) 01045 chanout[6] += op_calc(SLOT->Cnt, env, chip->phase_modulation, SLOT->wavetable) * 2; 01046 01047 01048 /* Phase generation is based on: */ 01049 // HH (13) channel 7->slot 1 combined with channel 8->slot 2 (same combination as TOP CYMBAL but different output phases) 01050 // SD (16) channel 7->slot 1 01051 // TOM (14) channel 8->slot 1 01052 // TOP (17) channel 7->slot 1 combined with channel 8->slot 2 (same combination as HIGH HAT but different output phases) 01053 01054 /* Envelope generation based on: */ 01055 // HH channel 7->slot1 01056 // SD channel 7->slot2 01057 // TOM channel 8->slot1 01058 // TOP channel 8->slot2 01059 01060 01061 /* The following formulas can be well optimized. 01062 I leave them in direct form for now (in case I've missed something). 01063 */ 01064 01065 /* High Hat (verified on real YM3812) */ 01066 env = volume_calc(SLOT7_1); 01067 if( env < ENV_QUIET ) 01068 { 01069 /* high hat phase generation: 01070 phase = d0 or 234 (based on frequency only) 01071 phase = 34 or 2d0 (based on noise) 01072 */ 01073 01074 /* base frequency derived from operator 1 in channel 7 */ 01075 unsigned char bit7 = ((SLOT7_1->Cnt>>FREQ_SH)>>7)&1; 01076 unsigned char bit3 = ((SLOT7_1->Cnt>>FREQ_SH)>>3)&1; 01077 unsigned char bit2 = ((SLOT7_1->Cnt>>FREQ_SH)>>2)&1; 01078 01079 unsigned char res1 = (bit2 ^ bit7) | bit3; 01080 01081 /* when res1 = 0 phase = 0x000 | 0xd0; */ 01082 /* when res1 = 1 phase = 0x200 | (0xd0>>2); */ 01083 uint32_t phase = res1 ? (0x200|(0xd0>>2)) : 0xd0; 01084 01085 /* enable gate based on frequency of operator 2 in channel 8 */ 01086 unsigned char bit5e= ((SLOT8_2->Cnt>>FREQ_SH)>>5)&1; 01087 unsigned char bit3e= ((SLOT8_2->Cnt>>FREQ_SH)>>3)&1; 01088 01089 unsigned char res2 = (bit3e ^ bit5e); 01090 01091 /* when res2 = 0 pass the phase from calculation above (res1); */ 01092 /* when res2 = 1 phase = 0x200 | (0xd0>>2); */ 01093 if (res2) 01094 phase = (0x200|(0xd0>>2)); 01095 01096 01097 /* when phase & 0x200 is set and noise=1 then phase = 0x200|0xd0 */ 01098 /* when phase & 0x200 is set and noise=0 then phase = 0x200|(0xd0>>2), ie no change */ 01099 if (phase&0x200) 01100 { 01101 if (noise) 01102 phase = 0x200|0xd0; 01103 } 01104 else 01105 /* when phase & 0x200 is clear and noise=1 then phase = 0xd0>>2 */ 01106 /* when phase & 0x200 is clear and noise=0 then phase = 0xd0, ie no change */ 01107 { 01108 if (noise) 01109 phase = 0xd0>>2; 01110 } 01111 01112 chanout[7] += op_calc(phase<<FREQ_SH, env, 0, SLOT7_1->wavetable) * 2; 01113 } 01114 01115 /* Snare Drum (verified on real YM3812) */ 01116 env = volume_calc(SLOT7_2); 01117 if( env < ENV_QUIET ) 01118 { 01119 /* base frequency derived from operator 1 in channel 7 */ 01120 unsigned char bit8 = ((SLOT7_1->Cnt>>FREQ_SH)>>8)&1; 01121 01122 /* when bit8 = 0 phase = 0x100; */ 01123 /* when bit8 = 1 phase = 0x200; */ 01124 uint32_t phase = bit8 ? 0x200 : 0x100; 01125 01126 /* Noise bit XOR'es phase by 0x100 */ 01127 /* when noisebit = 0 pass the phase from calculation above */ 01128 /* when noisebit = 1 phase ^= 0x100; */ 01129 /* in other words: phase ^= (noisebit<<8); */ 01130 if (noise) 01131 phase ^= 0x100; 01132 01133 chanout[7] += op_calc(phase<<FREQ_SH, env, 0, SLOT7_2->wavetable) * 2; 01134 } 01135 01136 /* Tom Tom (verified on real YM3812) */ 01137 env = volume_calc(SLOT8_1); 01138 if( env < ENV_QUIET ) 01139 chanout[8] += op_calc(SLOT8_1->Cnt, env, 0, SLOT8_1->wavetable) * 2; 01140 01141 /* Top Cymbal (verified on real YM3812) */ 01142 env = volume_calc(SLOT8_2); 01143 if( env < ENV_QUIET ) 01144 { 01145 /* base frequency derived from operator 1 in channel 7 */ 01146 unsigned char bit7 = ((SLOT7_1->Cnt>>FREQ_SH)>>7)&1; 01147 unsigned char bit3 = ((SLOT7_1->Cnt>>FREQ_SH)>>3)&1; 01148 unsigned char bit2 = ((SLOT7_1->Cnt>>FREQ_SH)>>2)&1; 01149 01150 unsigned char res1 = (bit2 ^ bit7) | bit3; 01151 01152 /* when res1 = 0 phase = 0x000 | 0x100; */ 01153 /* when res1 = 1 phase = 0x200 | 0x100; */ 01154 uint32_t phase = res1 ? 0x300 : 0x100; 01155 01156 /* enable gate based on frequency of operator 2 in channel 8 */ 01157 unsigned char bit5e= ((SLOT8_2->Cnt>>FREQ_SH)>>5)&1; 01158 unsigned char bit3e= ((SLOT8_2->Cnt>>FREQ_SH)>>3)&1; 01159 01160 unsigned char res2 = (bit3e ^ bit5e); 01161 /* when res2 = 0 pass the phase from calculation above (res1); */ 01162 /* when res2 = 1 phase = 0x200 | 0x100; */ 01163 if (res2) 01164 phase = 0x300; 01165 01166 chanout[8] += op_calc(phase<<FREQ_SH, env, 0, SLOT8_2->wavetable) * 2; 01167 } 01168 01169 } 01170 01171 01172 /* generic table initialize */ 01173 static int init_tables(void) 01174 { 01175 signed int i,x; 01176 signed int n; 01177 double o,m; 01178 01179 01180 for (x=0; x<TL_RES_LEN; x++) 01181 { 01182 m = (1<<16) / pow(2, (x+1) * (ENV_STEP/4.0) / 8.0); 01183 m = floor(m); 01184 01185 /* we never reach (1<<16) here due to the (x+1) */ 01186 /* result fits within 16 bits at maximum */ 01187 01188 n = (int)m; /* 16 bits here */ 01189 n >>= 4; /* 12 bits here */ 01190 if (n&1) /* round to nearest */ 01191 n = (n>>1)+1; 01192 else 01193 n = n>>1; 01194 /* 11 bits here (rounded) */ 01195 n <<= 1; /* 12 bits here (as in real chip) */ 01196 tl_tab[ x*2 + 0 ] = n; 01197 tl_tab[ x*2 + 1 ] = ~tl_tab[ x*2 + 0 ]; /* this *is* different from OPL2 (verified on real YMF262) */ 01198 01199 for (i=1; i<13; i++) 01200 { 01201 tl_tab[ x*2+0 + i*2*TL_RES_LEN ] = tl_tab[ x*2+0 ]>>i; 01202 tl_tab[ x*2+1 + i*2*TL_RES_LEN ] = ~tl_tab[ x*2+0 + i*2*TL_RES_LEN ]; /* this *is* different from OPL2 (verified on real YMF262) */ 01203 } 01204 #if 0 01205 logerror("tl %04i", x*2); 01206 for (i=0; i<13; i++) 01207 logerror(", [%02i] %5i", i*2, tl_tab[ x*2 +0 + i*2*TL_RES_LEN ] ); /* positive */ 01208 logerror("\n"); 01209 01210 logerror("tl %04i", x*2); 01211 for (i=0; i<13; i++) 01212 logerror(", [%02i] %5i", i*2, tl_tab[ x*2 +1 + i*2*TL_RES_LEN ] ); /* negative */ 01213 logerror("\n"); 01214 #endif 01215 } 01216 01217 for (i=0; i<SIN_LEN; i++) 01218 { 01219 /* non-standard sinus */ 01220 m = sin( ((i*2)+1) * M_PI / SIN_LEN ); /* checked against the real chip */ 01221 01222 /* we never reach zero here due to ((i*2)+1) */ 01223 01224 if (m>0.0) 01225 o = 8*log(1.0/m)/log(2.0); /* convert to 'decibels' */ 01226 else 01227 o = 8*log(-1.0/m)/log(2.0); /* convert to 'decibels' */ 01228 01229 o = o / (ENV_STEP/4); 01230 01231 n = (int)(2.0*o); 01232 if (n&1) /* round to nearest */ 01233 n = (n>>1)+1; 01234 else 01235 n = n>>1; 01236 01237 sin_tab[ i ] = n*2 + (m>=0.0? 0: 1 ); 01238 01239 /*logerror("YMF262.C: sin [%4i (hex=%03x)]= %4i (tl_tab value=%5i)\n", i, i, sin_tab[i], tl_tab[sin_tab[i]] );*/ 01240 } 01241 01242 for (i=0; i<SIN_LEN; i++) 01243 { 01244 /* these 'pictures' represent _two_ cycles */ 01245 /* waveform 1: __ __ */ 01246 /* / \____/ \____*/ 01247 /* output only first half of the sinus waveform (positive one) */ 01248 01249 if (i & (1<<(SIN_BITS-1)) ) 01250 sin_tab[1*SIN_LEN+i] = TL_TAB_LEN; 01251 else 01252 sin_tab[1*SIN_LEN+i] = sin_tab[i]; 01253 01254 /* waveform 2: __ __ __ __ */ 01255 /* / \/ \/ \/ \*/ 01256 /* abs(sin) */ 01257 01258 sin_tab[2*SIN_LEN+i] = sin_tab[i & (SIN_MASK>>1) ]; 01259 01260 /* waveform 3: _ _ _ _ */ 01261 /* / |_/ |_/ |_/ |_*/ 01262 /* abs(output only first quarter of the sinus waveform) */ 01263 01264 if (i & (1<<(SIN_BITS-2)) ) 01265 sin_tab[3*SIN_LEN+i] = TL_TAB_LEN; 01266 else 01267 sin_tab[3*SIN_LEN+i] = sin_tab[i & (SIN_MASK>>2)]; 01268 01269 /* waveform 4: */ 01270 /* /\ ____/\ ____*/ 01271 /* \/ \/ */ 01272 /* output whole sinus waveform in half the cycle(step=2) and output 0 on the other half of cycle */ 01273 01274 if (i & (1<<(SIN_BITS-1)) ) 01275 sin_tab[4*SIN_LEN+i] = TL_TAB_LEN; 01276 else 01277 sin_tab[4*SIN_LEN+i] = sin_tab[i*2]; 01278 01279 /* waveform 5: */ 01280 /* /\/\____/\/\____*/ 01281 /* */ 01282 /* output abs(whole sinus) waveform in half the cycle(step=2) and output 0 on the other half of cycle */ 01283 01284 if (i & (1<<(SIN_BITS-1)) ) 01285 sin_tab[5*SIN_LEN+i] = TL_TAB_LEN; 01286 else 01287 sin_tab[5*SIN_LEN+i] = sin_tab[(i*2) & (SIN_MASK>>1) ]; 01288 01289 /* waveform 6: ____ ____ */ 01290 /* */ 01291 /* ____ ____*/ 01292 /* output maximum in half the cycle and output minimum on the other half of cycle */ 01293 01294 if (i & (1<<(SIN_BITS-1)) ) 01295 sin_tab[6*SIN_LEN+i] = 1; /* negative */ 01296 else 01297 sin_tab[6*SIN_LEN+i] = 0; /* positive */ 01298 01299 /* waveform 7: */ 01300 /* |\____ |\____ */ 01301 /* \| \|*/ 01302 /* output sawtooth waveform */ 01303 01304 if (i & (1<<(SIN_BITS-1)) ) 01305 x = ((SIN_LEN-1)-i)*16 + 1; /* negative: from 8177 to 1 */ 01306 else 01307 x = i*16; /*positive: from 0 to 8176 */ 01308 01309 if (x > TL_TAB_LEN) 01310 x = TL_TAB_LEN; /* clip to the allowed range */ 01311 01312 sin_tab[7*SIN_LEN+i] = x; 01313 01314 //logerror("YMF262.C: sin1[%4i]= %4i (tl_tab value=%5i)\n", i, sin_tab[1*SIN_LEN+i], tl_tab[sin_tab[1*SIN_LEN+i]] ); 01315 //logerror("YMF262.C: sin2[%4i]= %4i (tl_tab value=%5i)\n", i, sin_tab[2*SIN_LEN+i], tl_tab[sin_tab[2*SIN_LEN+i]] ); 01316 //logerror("YMF262.C: sin3[%4i]= %4i (tl_tab value=%5i)\n", i, sin_tab[3*SIN_LEN+i], tl_tab[sin_tab[3*SIN_LEN+i]] ); 01317 //logerror("YMF262.C: sin4[%4i]= %4i (tl_tab value=%5i)\n", i, sin_tab[4*SIN_LEN+i], tl_tab[sin_tab[4*SIN_LEN+i]] ); 01318 //logerror("YMF262.C: sin5[%4i]= %4i (tl_tab value=%5i)\n", i, sin_tab[5*SIN_LEN+i], tl_tab[sin_tab[5*SIN_LEN+i]] ); 01319 //logerror("YMF262.C: sin6[%4i]= %4i (tl_tab value=%5i)\n", i, sin_tab[6*SIN_LEN+i], tl_tab[sin_tab[6*SIN_LEN+i]] ); 01320 //logerror("YMF262.C: sin7[%4i]= %4i (tl_tab value=%5i)\n", i, sin_tab[7*SIN_LEN+i], tl_tab[sin_tab[7*SIN_LEN+i]] ); 01321 } 01322 /*logerror("YMF262.C: ENV_QUIET= %08x (dec*8=%i)\n", ENV_QUIET, ENV_QUIET*8 );*/ 01323 01324 #ifdef SAVE_SAMPLE 01325 sample[0]=fopen("sampsum.pcm","wb"); 01326 #endif 01327 01328 return 1; 01329 } 01330 01331 static void OPLCloseTable( void ) 01332 { 01333 #ifdef SAVE_SAMPLE 01334 fclose(sample[0]); 01335 #endif 01336 } 01337 01338 01339 01340 static void OPL3_initalize(OPL3 *chip) 01341 { 01342 int i; 01343 01344 /* frequency base */ 01345 chip->freqbase = (chip->rate) ? ((double)chip->clock / (8.0*36)) / chip->rate : 0; 01346 #if 0 01347 chip->rate = (double)chip->clock / (8.0*36); 01348 chip->freqbase = 1.0; 01349 #endif 01350 01351 /* logerror("YMF262: freqbase=%f\n", chip->freqbase); */ 01352 01353 /* Timer base time */ 01354 //chip->TimerBase = attotime::from_hz(chip->clock) * (8*36); 01355 01356 /* make fnumber -> increment counter table */ 01357 for( i=0 ; i < 1024 ; i++ ) 01358 { 01359 /* opn phase increment counter = 20bit */ 01360 chip->fn_tab[i] = (uint32_t)( (double)i * 64 * chip->freqbase * (1<<(FREQ_SH-10)) ); /* -10 because chip works with 10.10 fixed point, while we use 16.16 */ 01361 #if 0 01362 logerror("YMF262.C: fn_tab[%4i] = %08x (dec=%8i)\n", 01363 i, chip->fn_tab[i]>>6, chip->fn_tab[i]>>6 ); 01364 #endif 01365 } 01366 01367 #if 0 01368 for( i=0 ; i < 16 ; i++ ) 01369 { 01370 logerror("YMF262.C: sl_tab[%i] = %08x\n", 01371 i, sl_tab[i] ); 01372 } 01373 for( i=0 ; i < 8 ; i++ ) 01374 { 01375 int j; 01376 logerror("YMF262.C: ksl_tab[oct=%2i] =",i); 01377 for (j=0; j<16; j++) 01378 { 01379 logerror("%08x ", static_cast<uint32_t>(ksl_tab[i*16+j]) ); 01380 } 01381 logerror("\n"); 01382 } 01383 #endif 01384 01385 01386 /* Amplitude modulation: 27 output levels (triangle waveform); 1 level takes one of: 192, 256 or 448 samples */ 01387 /* One entry from LFO_AM_TABLE lasts for 64 samples */ 01388 chip->lfo_am_inc = (uint32_t)((1.0 / 64.0 ) * (1<<LFO_SH) * chip->freqbase); 01389 01390 /* Vibrato: 8 output levels (triangle waveform); 1 level takes 1024 samples */ 01391 chip->lfo_pm_inc = (uint32_t)((1.0 / 1024.0) * (1<<LFO_SH) * chip->freqbase); 01392 01393 /*logerror ("chip->lfo_am_inc = %8x ; chip->lfo_pm_inc = %8x\n", chip->lfo_am_inc, chip->lfo_pm_inc);*/ 01394 01395 /* Noise generator: a step takes 1 sample */ 01396 chip->noise_f = (uint32_t)((1.0 / 1.0) * (1<<FREQ_SH) * chip->freqbase); 01397 01398 chip->eg_timer_add = (uint32_t)((1<<EG_SH) * chip->freqbase); 01399 chip->eg_timer_overflow = ( 1 ) * (1<<EG_SH); 01400 /*logerror("YMF262init eg_timer_add=%8x eg_timer_overflow=%8x\n", chip->eg_timer_add, chip->eg_timer_overflow);*/ 01401 01402 } 01403 01404 static inline void FM_KEYON(OPL3_SLOT *SLOT, uint32_t key_set) 01405 { 01406 if( !SLOT->key ) 01407 { 01408 /* restart Phase Generator */ 01409 SLOT->Cnt = 0; 01410 /* phase -> Attack */ 01411 SLOT->state = EG_ATT; 01412 } 01413 SLOT->key |= key_set; 01414 } 01415 01416 static inline void FM_KEYOFF(OPL3_SLOT *SLOT, uint32_t key_clr) 01417 { 01418 if( SLOT->key ) 01419 { 01420 SLOT->key &= key_clr; 01421 01422 if( !SLOT->key ) 01423 { 01424 /* phase -> Release */ 01425 if (SLOT->state>EG_REL) 01426 SLOT->state = EG_REL; 01427 } 01428 } 01429 } 01430 01431 /* update phase increment counter of operator (also update the EG rates if necessary) */ 01432 static inline void CALC_FCSLOT(OPL3_CH *CH,OPL3_SLOT *SLOT) 01433 { 01434 int ksr; 01435 01436 /* (frequency) phase increment counter */ 01437 SLOT->Incr = CH->fc * SLOT->mul; 01438 ksr = CH->kcode >> SLOT->KSR; 01439 01440 if( SLOT->ksr != ksr ) 01441 { 01442 SLOT->ksr = ksr; 01443 01444 /* calculate envelope generator rates */ 01445 if ((SLOT->ar + SLOT->ksr) < 16+60) 01446 { 01447 SLOT->eg_sh_ar = eg_rate_shift [SLOT->ar + SLOT->ksr ]; 01448 SLOT->eg_m_ar = (1<<SLOT->eg_sh_ar)-1; 01449 SLOT->eg_sel_ar = eg_rate_select[SLOT->ar + SLOT->ksr ]; 01450 } 01451 else 01452 { 01453 SLOT->eg_sh_ar = 0; 01454 SLOT->eg_m_ar = (1<<SLOT->eg_sh_ar)-1; 01455 SLOT->eg_sel_ar = 13*RATE_STEPS; 01456 } 01457 SLOT->eg_sh_dr = eg_rate_shift [SLOT->dr + SLOT->ksr ]; 01458 SLOT->eg_m_dr = (1<<SLOT->eg_sh_dr)-1; 01459 SLOT->eg_sel_dr = eg_rate_select[SLOT->dr + SLOT->ksr ]; 01460 SLOT->eg_sh_rr = eg_rate_shift [SLOT->rr + SLOT->ksr ]; 01461 SLOT->eg_m_rr = (1<<SLOT->eg_sh_rr)-1; 01462 SLOT->eg_sel_rr = eg_rate_select[SLOT->rr + SLOT->ksr ]; 01463 } 01464 } 01465 01466 /* set multi,am,vib,EG-TYP,KSR,mul */ 01467 static inline void set_mul(OPL3 *chip,int slot,int v) 01468 { 01469 OPL3_CH *CH = &chip->P_CH[slot/2]; 01470 OPL3_SLOT *SLOT = &CH->SLOT[slot&1]; 01471 01472 SLOT->mul = mul_tab[v&0x0f]; 01473 SLOT->KSR = (v&0x10) ? 0 : 2; 01474 SLOT->eg_type = (v&0x20); 01475 SLOT->vib = (v&0x40); 01476 SLOT->AMmask = (v&0x80) ? ~0 : 0; 01477 01478 if (chip->OPL3_mode & 1) 01479 { 01480 int chan_no = slot/2; 01481 01482 /* in OPL3 mode */ 01483 //DO THIS: 01484 //if this is one of the slots of 1st channel forming up a 4-op channel 01485 //do normal operation 01486 //else normal 2 operator function 01487 //OR THIS: 01488 //if this is one of the slots of 2nd channel forming up a 4-op channel 01489 //update it using channel data of 1st channel of a pair 01490 //else normal 2 operator function 01491 switch(chan_no) 01492 { 01493 case 0: case 1: case 2: 01494 case 9: case 10: case 11: 01495 if (CH->extended) 01496 { 01497 /* normal */ 01498 CALC_FCSLOT(CH,SLOT); 01499 } 01500 else 01501 { 01502 /* normal */ 01503 CALC_FCSLOT(CH,SLOT); 01504 } 01505 break; 01506 case 3: case 4: case 5: 01507 case 12: case 13: case 14: 01508 if ((CH-3)->extended) 01509 { 01510 /* update this SLOT using frequency data for 1st channel of a pair */ 01511 CALC_FCSLOT(CH-3,SLOT); 01512 } 01513 else 01514 { 01515 /* normal */ 01516 CALC_FCSLOT(CH,SLOT); 01517 } 01518 break; 01519 default: 01520 /* normal */ 01521 CALC_FCSLOT(CH,SLOT); 01522 break; 01523 } 01524 } 01525 else 01526 { 01527 /* in OPL2 mode */ 01528 CALC_FCSLOT(CH,SLOT); 01529 } 01530 } 01531 01532 /* set ksl & tl */ 01533 static inline void set_ksl_tl(OPL3 *chip,int slot,int v) 01534 { 01535 OPL3_CH *CH = &chip->P_CH[slot/2]; 01536 OPL3_SLOT *SLOT = &CH->SLOT[slot&1]; 01537 01538 SLOT->ksl = ksl_shift[v >> 6]; 01539 SLOT->TL = (v&0x3f)<<(ENV_BITS-1-7); /* 7 bits TL (bit 6 = always 0) */ 01540 01541 if (chip->OPL3_mode & 1) 01542 { 01543 int chan_no = slot/2; 01544 01545 /* in OPL3 mode */ 01546 //DO THIS: 01547 //if this is one of the slots of 1st channel forming up a 4-op channel 01548 //do normal operation 01549 //else normal 2 operator function 01550 //OR THIS: 01551 //if this is one of the slots of 2nd channel forming up a 4-op channel 01552 //update it using channel data of 1st channel of a pair 01553 //else normal 2 operator function 01554 switch(chan_no) 01555 { 01556 case 0: case 1: case 2: 01557 case 9: case 10: case 11: 01558 if (CH->extended) 01559 { 01560 /* normal */ 01561 SLOT->TLL = SLOT->TL + (CH->ksl_base>>SLOT->ksl); 01562 } 01563 else 01564 { 01565 /* normal */ 01566 SLOT->TLL = SLOT->TL + (CH->ksl_base>>SLOT->ksl); 01567 } 01568 break; 01569 case 3: case 4: case 5: 01570 case 12: case 13: case 14: 01571 if ((CH-3)->extended) 01572 { 01573 /* update this SLOT using frequency data for 1st channel of a pair */ 01574 SLOT->TLL = SLOT->TL + ((CH-3)->ksl_base>>SLOT->ksl); 01575 } 01576 else 01577 { 01578 /* normal */ 01579 SLOT->TLL = SLOT->TL + (CH->ksl_base>>SLOT->ksl); 01580 } 01581 break; 01582 default: 01583 /* normal */ 01584 SLOT->TLL = SLOT->TL + (CH->ksl_base>>SLOT->ksl); 01585 break; 01586 } 01587 } 01588 else 01589 { 01590 /* in OPL2 mode */ 01591 SLOT->TLL = SLOT->TL + (CH->ksl_base>>SLOT->ksl); 01592 } 01593 01594 } 01595 01596 /* set attack rate & decay rate */ 01597 static inline void set_ar_dr(OPL3 *chip,int slot,int v) 01598 { 01599 OPL3_CH *CH = &chip->P_CH[slot/2]; 01600 OPL3_SLOT *SLOT = &CH->SLOT[slot&1]; 01601 01602 SLOT->ar = (v>>4) ? 16 + ((v>>4) <<2) : 0; 01603 01604 if ((SLOT->ar + SLOT->ksr) < 16+60) /* verified on real YMF262 - all 15 x rates take "zero" time */ 01605 { 01606 SLOT->eg_sh_ar = eg_rate_shift [SLOT->ar + SLOT->ksr ]; 01607 SLOT->eg_m_ar = (1<<SLOT->eg_sh_ar)-1; 01608 SLOT->eg_sel_ar = eg_rate_select[SLOT->ar + SLOT->ksr ]; 01609 } 01610 else 01611 { 01612 SLOT->eg_sh_ar = 0; 01613 SLOT->eg_m_ar = (1<<SLOT->eg_sh_ar)-1; 01614 SLOT->eg_sel_ar = 13*RATE_STEPS; 01615 } 01616 01617 SLOT->dr = (v&0x0f)? 16 + ((v&0x0f)<<2) : 0; 01618 SLOT->eg_sh_dr = eg_rate_shift [SLOT->dr + SLOT->ksr ]; 01619 SLOT->eg_m_dr = (1<<SLOT->eg_sh_dr)-1; 01620 SLOT->eg_sel_dr = eg_rate_select[SLOT->dr + SLOT->ksr ]; 01621 } 01622 01623 /* set sustain level & release rate */ 01624 static inline void set_sl_rr(OPL3 *chip,int slot,int v) 01625 { 01626 OPL3_CH *CH = &chip->P_CH[slot/2]; 01627 OPL3_SLOT *SLOT = &CH->SLOT[slot&1]; 01628 01629 SLOT->sl = sl_tab[ v>>4 ]; 01630 01631 SLOT->rr = (v&0x0f)? 16 + ((v&0x0f)<<2) : 0; 01632 SLOT->eg_sh_rr = eg_rate_shift [SLOT->rr + SLOT->ksr ]; 01633 SLOT->eg_m_rr = (1<<SLOT->eg_sh_rr)-1; 01634 SLOT->eg_sel_rr = eg_rate_select[SLOT->rr + SLOT->ksr ]; 01635 } 01636 01637 01638 static void update_channels(OPL3 *chip, OPL3_CH *CH) 01639 { 01640 (void)chip; 01641 /* update channel passed as a parameter and a channel at CH+=3; */ 01642 if (CH->extended) 01643 { /* we've just switched to combined 4 operator mode */ 01644 01645 } 01646 else 01647 { /* we've just switched to normal 2 operator mode */ 01648 01649 } 01650 01651 } 01652 01653 /* write a value v to register r on OPL chip */ 01654 static void OPL3WriteReg(OPL3 *chip, int r, int v) 01655 { 01656 OPL3_CH *CH; 01657 unsigned int ch_offset = 0; 01658 int slot; 01659 int block_fnum; 01660 01661 if(r&0x100) 01662 { 01663 switch(r) 01664 { 01665 case 0x101: /* test register */ 01666 return; 01667 01668 case 0x104: /* 6 channels enable */ 01669 { 01670 uint8_t prev; 01671 01672 CH = &chip->P_CH[0]; /* channel 0 */ 01673 prev = CH->extended; 01674 CH->extended = (v>>0) & 1; 01675 if(prev != CH->extended) 01676 update_channels(chip, CH); 01677 CH++; /* channel 1 */ 01678 prev = CH->extended; 01679 CH->extended = (v>>1) & 1; 01680 if(prev != CH->extended) 01681 update_channels(chip, CH); 01682 CH++; /* channel 2 */ 01683 prev = CH->extended; 01684 CH->extended = (v>>2) & 1; 01685 if(prev != CH->extended) 01686 update_channels(chip, CH); 01687 01688 01689 CH = &chip->P_CH[9]; /* channel 9 */ 01690 prev = CH->extended; 01691 CH->extended = (v>>3) & 1; 01692 if(prev != CH->extended) 01693 update_channels(chip, CH); 01694 CH++; /* channel 10 */ 01695 prev = CH->extended; 01696 CH->extended = (v>>4) & 1; 01697 if(prev != CH->extended) 01698 update_channels(chip, CH); 01699 CH++; /* channel 11 */ 01700 prev = CH->extended; 01701 CH->extended = (v>>5) & 1; 01702 if(prev != CH->extended) 01703 update_channels(chip, CH); 01704 01705 } 01706 return; 01707 01708 case 0x105: /* OPL3 extensions enable register */ 01709 01710 chip->OPL3_mode = v&0x01; /* OPL3 mode when bit0=1 otherwise it is OPL2 mode */ 01711 01712 /* following behaviour was tested on real YMF262, 01713 switching OPL3/OPL2 modes on the fly: 01714 - does not change the waveform previously selected (unless when ....) 01715 - does not update CH.A, CH.B, CH.C and CH.D output selectors (registers c0-c8) (unless when ....) 01716 - does not disable channels 9-17 on OPL3->OPL2 switch 01717 - does not switch 4 operator channels back to 2 operator channels 01718 */ 01719 01720 return; 01721 01722 default: 01723 if (r < 0x120) 01724 chip->device->logerror("YMF262: write to unknown register (set#2): %03x value=%02x\n",r,v); 01725 break; 01726 } 01727 01728 ch_offset = 9; /* register page #2 starts from channel 9 (counting from 0) */ 01729 } 01730 01731 /* adjust bus to 8 bits */ 01732 r &= 0xff; 01733 v &= 0xff; 01734 01735 01736 switch(r&0xe0) 01737 { 01738 case 0x00: /* 00-1f:control */ 01739 switch(r&0x1f) 01740 { 01741 case 0x01: /* test register */ 01742 break; 01743 case 0x02: /* Timer 1 */ 01744 chip->T[0] = (256-v)*4; 01745 break; 01746 case 0x03: /* Timer 2 */ 01747 chip->T[1] = (256-v)*16; 01748 break; 01749 #if 0 01750 case 0x04: /* IRQ clear / mask and Timer enable */ 01751 if(v&0x80) 01752 { /* IRQ flags clear */ 01753 OPL3_STATUS_RESET(chip,0x60); 01754 } 01755 else 01756 { /* set IRQ mask ,timer enable */ 01757 uint8_t st1 = v & 1; 01758 uint8_t st2 = (v>>1) & 1; 01759 01760 /* IRQRST,T1MSK,t2MSK,x,x,x,ST2,ST1 */ 01761 OPL3_STATUS_RESET(chip, v & 0x60); 01762 OPL3_STATUSMASK_SET(chip, (~v) & 0x60 ); 01763 01764 /* timer 2 */ 01765 if(chip->st[1] != st2) 01766 { 01767 attotime period = st2 ? chip->TimerBase * chip->T[1] : attotime::zero; 01768 chip->st[1] = st2; 01769 if (chip->timer_handler) (chip->timer_handler)(chip->TimerParam,1,period); 01770 } 01771 /* timer 1 */ 01772 if(chip->st[0] != st1) 01773 { 01774 attotime period = st1 ? chip->TimerBase * chip->T[0] : attotime::zero; 01775 chip->st[0] = st1; 01776 if (chip->timer_handler) (chip->timer_handler)(chip->TimerParam,0,period); 01777 } 01778 } 01779 #endif 01780 break; 01781 case 0x08: /* x,NTS,x,x, x,x,x,x */ 01782 chip->nts = v; 01783 break; 01784 01785 default: 01786 chip->device->logerror("YMF262: write to unknown register: %02x value=%02x\n",r,v); 01787 break; 01788 } 01789 break; 01790 case 0x20: /* am ON, vib ON, ksr, eg_type, mul */ 01791 slot = slot_array[r&0x1f]; 01792 if(slot < 0) return; 01793 set_mul(chip, slot + ch_offset*2, v); 01794 break; 01795 case 0x40: 01796 slot = slot_array[r&0x1f]; 01797 if(slot < 0) return; 01798 set_ksl_tl(chip, slot + ch_offset*2, v); 01799 break; 01800 case 0x60: 01801 slot = slot_array[r&0x1f]; 01802 if(slot < 0) return; 01803 set_ar_dr(chip, slot + ch_offset*2, v); 01804 break; 01805 case 0x80: 01806 slot = slot_array[r&0x1f]; 01807 if(slot < 0) return; 01808 set_sl_rr(chip, slot + ch_offset*2, v); 01809 break; 01810 case 0xa0: 01811 if (r == 0xbd) /* am depth, vibrato depth, r,bd,sd,tom,tc,hh */ 01812 { 01813 if (ch_offset != 0) /* 0xbd register is present in set #1 only */ 01814 return; 01815 01816 chip->lfo_am_depth = v & 0x80; 01817 chip->lfo_pm_depth_range = (v&0x40) ? 8 : 0; 01818 01819 chip->rhythm = v&0x3f; 01820 01821 if(chip->rhythm&0x20) 01822 { 01823 /* BD key on/off */ 01824 if(v&0x10) 01825 { 01826 FM_KEYON (&chip->P_CH[6].SLOT[SLOT1], 2); 01827 FM_KEYON (&chip->P_CH[6].SLOT[SLOT2], 2); 01828 } 01829 else 01830 { 01831 FM_KEYOFF(&chip->P_CH[6].SLOT[SLOT1],~2); 01832 FM_KEYOFF(&chip->P_CH[6].SLOT[SLOT2],~2); 01833 } 01834 /* HH key on/off */ 01835 if(v&0x01) FM_KEYON (&chip->P_CH[7].SLOT[SLOT1], 2); 01836 else FM_KEYOFF(&chip->P_CH[7].SLOT[SLOT1],~2); 01837 /* SD key on/off */ 01838 if(v&0x08) FM_KEYON (&chip->P_CH[7].SLOT[SLOT2], 2); 01839 else FM_KEYOFF(&chip->P_CH[7].SLOT[SLOT2],~2); 01840 /* TOM key on/off */ 01841 if(v&0x04) FM_KEYON (&chip->P_CH[8].SLOT[SLOT1], 2); 01842 else FM_KEYOFF(&chip->P_CH[8].SLOT[SLOT1],~2); 01843 /* TOP-CY key on/off */ 01844 if(v&0x02) FM_KEYON (&chip->P_CH[8].SLOT[SLOT2], 2); 01845 else FM_KEYOFF(&chip->P_CH[8].SLOT[SLOT2],~2); 01846 } 01847 else 01848 { 01849 /* BD key off */ 01850 FM_KEYOFF(&chip->P_CH[6].SLOT[SLOT1],~2); 01851 FM_KEYOFF(&chip->P_CH[6].SLOT[SLOT2],~2); 01852 /* HH key off */ 01853 FM_KEYOFF(&chip->P_CH[7].SLOT[SLOT1],~2); 01854 /* SD key off */ 01855 FM_KEYOFF(&chip->P_CH[7].SLOT[SLOT2],~2); 01856 /* TOM key off */ 01857 FM_KEYOFF(&chip->P_CH[8].SLOT[SLOT1],~2); 01858 /* TOP-CY off */ 01859 FM_KEYOFF(&chip->P_CH[8].SLOT[SLOT2],~2); 01860 } 01861 return; 01862 } 01863 01864 /* keyon,block,fnum */ 01865 if( (r&0x0f) > 8) return; 01866 CH = &chip->P_CH[(r&0x0f) + ch_offset]; 01867 01868 if(!(r&0x10)) 01869 { /* a0-a8 */ 01870 block_fnum = (CH->block_fnum&0x1f00) | v; 01871 } 01872 else 01873 { /* b0-b8 */ 01874 block_fnum = ((v&0x1f)<<8) | (CH->block_fnum&0xff); 01875 01876 if (chip->OPL3_mode & 1) 01877 { 01878 int chan_no = (r&0x0f) + ch_offset; 01879 01880 /* in OPL3 mode */ 01881 //DO THIS: 01882 //if this is 1st channel forming up a 4-op channel 01883 //ALSO keyon/off slots of 2nd channel forming up 4-op channel 01884 //else normal 2 operator function keyon/off 01885 //OR THIS: 01886 //if this is 2nd channel forming up 4-op channel just do nothing 01887 //else normal 2 operator function keyon/off 01888 switch(chan_no) 01889 { 01890 case 0: case 1: case 2: 01891 case 9: case 10: case 11: 01892 if (CH->extended) 01893 { 01894 //if this is 1st channel forming up a 4-op channel 01895 //ALSO keyon/off slots of 2nd channel forming up 4-op channel 01896 if(v&0x20) 01897 { 01898 FM_KEYON (&CH->SLOT[SLOT1], 1); 01899 FM_KEYON (&CH->SLOT[SLOT2], 1); 01900 FM_KEYON (&(CH+3)->SLOT[SLOT1], 1); 01901 FM_KEYON (&(CH+3)->SLOT[SLOT2], 1); 01902 } 01903 else 01904 { 01905 FM_KEYOFF(&CH->SLOT[SLOT1],~1); 01906 FM_KEYOFF(&CH->SLOT[SLOT2],~1); 01907 FM_KEYOFF(&(CH+3)->SLOT[SLOT1],~1); 01908 FM_KEYOFF(&(CH+3)->SLOT[SLOT2],~1); 01909 } 01910 } 01911 else 01912 { 01913 //else normal 2 operator function keyon/off 01914 if(v&0x20) 01915 { 01916 FM_KEYON (&CH->SLOT[SLOT1], 1); 01917 FM_KEYON (&CH->SLOT[SLOT2], 1); 01918 } 01919 else 01920 { 01921 FM_KEYOFF(&CH->SLOT[SLOT1],~1); 01922 FM_KEYOFF(&CH->SLOT[SLOT2],~1); 01923 } 01924 } 01925 break; 01926 01927 case 3: case 4: case 5: 01928 case 12: case 13: case 14: 01929 if ((CH-3)->extended) 01930 { 01931 //if this is 2nd channel forming up 4-op channel just do nothing 01932 } 01933 else 01934 { 01935 //else normal 2 operator function keyon/off 01936 if(v&0x20) 01937 { 01938 FM_KEYON (&CH->SLOT[SLOT1], 1); 01939 FM_KEYON (&CH->SLOT[SLOT2], 1); 01940 } 01941 else 01942 { 01943 FM_KEYOFF(&CH->SLOT[SLOT1],~1); 01944 FM_KEYOFF(&CH->SLOT[SLOT2],~1); 01945 } 01946 } 01947 break; 01948 01949 default: 01950 if(v&0x20) 01951 { 01952 FM_KEYON (&CH->SLOT[SLOT1], 1); 01953 FM_KEYON (&CH->SLOT[SLOT2], 1); 01954 } 01955 else 01956 { 01957 FM_KEYOFF(&CH->SLOT[SLOT1],~1); 01958 FM_KEYOFF(&CH->SLOT[SLOT2],~1); 01959 } 01960 break; 01961 } 01962 } 01963 else 01964 { 01965 if(v&0x20) 01966 { 01967 FM_KEYON (&CH->SLOT[SLOT1], 1); 01968 FM_KEYON (&CH->SLOT[SLOT2], 1); 01969 } 01970 else 01971 { 01972 FM_KEYOFF(&CH->SLOT[SLOT1],~1); 01973 FM_KEYOFF(&CH->SLOT[SLOT2],~1); 01974 } 01975 } 01976 } 01977 /* update */ 01978 if(CH->block_fnum != (unsigned int)block_fnum) 01979 { 01980 uint8_t block = block_fnum >> 10; 01981 01982 CH->block_fnum = block_fnum; 01983 01984 CH->ksl_base = static_cast<uint32_t>(ksl_tab[block_fnum>>6]); 01985 CH->fc = chip->fn_tab[block_fnum&0x03ff] >> (7-block); 01986 01987 /* BLK 2,1,0 bits -> bits 3,2,1 of kcode */ 01988 CH->kcode = (CH->block_fnum&0x1c00)>>9; 01989 01990 /* the info below is actually opposite to what is stated in the Manuals (verifed on real YMF262) */ 01991 /* if notesel == 0 -> lsb of kcode is bit 10 (MSB) of fnum */ 01992 /* if notesel == 1 -> lsb of kcode is bit 9 (MSB-1) of fnum */ 01993 if (chip->nts&0x40) 01994 CH->kcode |= (CH->block_fnum&0x100)>>8; /* notesel == 1 */ 01995 else 01996 CH->kcode |= (CH->block_fnum&0x200)>>9; /* notesel == 0 */ 01997 01998 if (chip->OPL3_mode & 1) 01999 { 02000 int chan_no = (r&0x0f) + ch_offset; 02001 /* in OPL3 mode */ 02002 //DO THIS: 02003 //if this is 1st channel forming up a 4-op channel 02004 //ALSO update slots of 2nd channel forming up 4-op channel 02005 //else normal 2 operator function keyon/off 02006 //OR THIS: 02007 //if this is 2nd channel forming up 4-op channel just do nothing 02008 //else normal 2 operator function keyon/off 02009 switch(chan_no) 02010 { 02011 case 0: case 1: case 2: 02012 case 9: case 10: case 11: 02013 if (CH->extended) 02014 { 02015 //if this is 1st channel forming up a 4-op channel 02016 //ALSO update slots of 2nd channel forming up 4-op channel 02017 02018 /* refresh Total Level in FOUR SLOTs of this channel and channel+3 using data from THIS channel */ 02019 CH->SLOT[SLOT1].TLL = CH->SLOT[SLOT1].TL + (CH->ksl_base>>CH->SLOT[SLOT1].ksl); 02020 CH->SLOT[SLOT2].TLL = CH->SLOT[SLOT2].TL + (CH->ksl_base>>CH->SLOT[SLOT2].ksl); 02021 (CH+3)->SLOT[SLOT1].TLL = (CH+3)->SLOT[SLOT1].TL + (CH->ksl_base>>(CH+3)->SLOT[SLOT1].ksl); 02022 (CH+3)->SLOT[SLOT2].TLL = (CH+3)->SLOT[SLOT2].TL + (CH->ksl_base>>(CH+3)->SLOT[SLOT2].ksl); 02023 02024 /* refresh frequency counter in FOUR SLOTs of this channel and channel+3 using data from THIS channel */ 02025 CALC_FCSLOT(CH,&CH->SLOT[SLOT1]); 02026 CALC_FCSLOT(CH,&CH->SLOT[SLOT2]); 02027 CALC_FCSLOT(CH,&(CH+3)->SLOT[SLOT1]); 02028 CALC_FCSLOT(CH,&(CH+3)->SLOT[SLOT2]); 02029 } 02030 else 02031 { 02032 //else normal 2 operator function 02033 /* refresh Total Level in both SLOTs of this channel */ 02034 CH->SLOT[SLOT1].TLL = CH->SLOT[SLOT1].TL + (CH->ksl_base>>CH->SLOT[SLOT1].ksl); 02035 CH->SLOT[SLOT2].TLL = CH->SLOT[SLOT2].TL + (CH->ksl_base>>CH->SLOT[SLOT2].ksl); 02036 02037 /* refresh frequency counter in both SLOTs of this channel */ 02038 CALC_FCSLOT(CH,&CH->SLOT[SLOT1]); 02039 CALC_FCSLOT(CH,&CH->SLOT[SLOT2]); 02040 } 02041 break; 02042 02043 case 3: case 4: case 5: 02044 case 12: case 13: case 14: 02045 if ((CH-3)->extended) 02046 { 02047 //if this is 2nd channel forming up 4-op channel just do nothing 02048 } 02049 else 02050 { 02051 //else normal 2 operator function 02052 /* refresh Total Level in both SLOTs of this channel */ 02053 CH->SLOT[SLOT1].TLL = CH->SLOT[SLOT1].TL + (CH->ksl_base>>CH->SLOT[SLOT1].ksl); 02054 CH->SLOT[SLOT2].TLL = CH->SLOT[SLOT2].TL + (CH->ksl_base>>CH->SLOT[SLOT2].ksl); 02055 02056 /* refresh frequency counter in both SLOTs of this channel */ 02057 CALC_FCSLOT(CH,&CH->SLOT[SLOT1]); 02058 CALC_FCSLOT(CH,&CH->SLOT[SLOT2]); 02059 } 02060 break; 02061 02062 default: 02063 /* refresh Total Level in both SLOTs of this channel */ 02064 CH->SLOT[SLOT1].TLL = CH->SLOT[SLOT1].TL + (CH->ksl_base>>CH->SLOT[SLOT1].ksl); 02065 CH->SLOT[SLOT2].TLL = CH->SLOT[SLOT2].TL + (CH->ksl_base>>CH->SLOT[SLOT2].ksl); 02066 02067 /* refresh frequency counter in both SLOTs of this channel */ 02068 CALC_FCSLOT(CH,&CH->SLOT[SLOT1]); 02069 CALC_FCSLOT(CH,&CH->SLOT[SLOT2]); 02070 break; 02071 } 02072 } 02073 else 02074 { 02075 /* in OPL2 mode */ 02076 02077 /* refresh Total Level in both SLOTs of this channel */ 02078 CH->SLOT[SLOT1].TLL = CH->SLOT[SLOT1].TL + (CH->ksl_base>>CH->SLOT[SLOT1].ksl); 02079 CH->SLOT[SLOT2].TLL = CH->SLOT[SLOT2].TL + (CH->ksl_base>>CH->SLOT[SLOT2].ksl); 02080 02081 /* refresh frequency counter in both SLOTs of this channel */ 02082 CALC_FCSLOT(CH,&CH->SLOT[SLOT1]); 02083 CALC_FCSLOT(CH,&CH->SLOT[SLOT2]); 02084 } 02085 } 02086 break; 02087 02088 case 0xc0: 02089 /* CH.D, CH.C, CH.B, CH.A, FB(3bits), C */ 02090 if( (r&0xf) > 8) return; 02091 02092 CH = &chip->P_CH[(r&0xf) + ch_offset]; 02093 02094 if( chip->OPL3_mode & 1 ) 02095 { 02096 int base = ((r&0xf) + ch_offset) * 4; 02097 02098 /* OPL3 mode */ 02099 chip->pan[ base ] = (v & 0x10) ? ~0 : 0; /* ch.A */ 02100 chip->pan[ base +1 ] = (v & 0x20) ? ~0 : 0; /* ch.B */ 02101 chip->pan[ base +2 ] = (v & 0x40) ? ~0 : 0; /* ch.C */ 02102 chip->pan[ base +3 ] = (v & 0x80) ? ~0 : 0; /* ch.D */ 02103 } 02104 else 02105 { 02106 int base = ((r&0xf) + ch_offset) * 4; 02107 02108 /* OPL2 mode - always enabled */ 02109 chip->pan[ base ] = ~0; /* ch.A */ 02110 chip->pan[ base +1 ] = ~0; /* ch.B */ 02111 chip->pan[ base +2 ] = ~0; /* ch.C */ 02112 chip->pan[ base +3 ] = ~0; /* ch.D */ 02113 } 02114 02115 chip->pan_ctrl_value[ (r&0xf) + ch_offset ] = v; /* store control value for OPL3/OPL2 mode switching on the fly */ 02116 02117 CH->SLOT[SLOT1].FB = (v>>1)&7 ? ((v>>1)&7) + 7 : 0; 02118 CH->SLOT[SLOT1].CON = v&1; 02119 02120 if( chip->OPL3_mode & 1 ) 02121 { 02122 int chan_no = (r&0x0f) + ch_offset; 02123 02124 switch(chan_no) 02125 { 02126 case 0: case 1: case 2: 02127 case 9: case 10: case 11: 02128 if (CH->extended) 02129 { 02130 uint8_t conn = (CH->SLOT[SLOT1].CON<<1) | ((CH+3)->SLOT[SLOT1].CON<<0); 02131 switch(conn) 02132 { 02133 case 0: 02134 /* 1 -> 2 -> 3 -> 4 - out */ 02135 02136 CH->SLOT[SLOT1].conn_enum = CONN_PHASEMOD; 02137 CH->SLOT[SLOT2].conn_enum = CONN_PHASEMOD2; 02138 (CH+3)->SLOT[SLOT1].conn_enum = CONN_PHASEMOD; 02139 (CH+3)->SLOT[SLOT2].conn_enum = CONN_CHAN0 + chan_no + 3; 02140 break; 02141 case 1: 02142 /* 1 -> 2 -\ 02143 3 -> 4 -+- out */ 02144 02145 CH->SLOT[SLOT1].conn_enum = CONN_PHASEMOD; 02146 CH->SLOT[SLOT2].conn_enum = CONN_CHAN0 + chan_no; 02147 (CH+3)->SLOT[SLOT1].conn_enum = CONN_PHASEMOD; 02148 (CH+3)->SLOT[SLOT2].conn_enum = CONN_CHAN0 + chan_no + 3; 02149 break; 02150 case 2: 02151 /* 1 -----------\ 02152 2 -> 3 -> 4 -+- out */ 02153 02154 CH->SLOT[SLOT1].conn_enum = CONN_CHAN0 + chan_no; 02155 CH->SLOT[SLOT2].conn_enum = CONN_PHASEMOD2; 02156 (CH+3)->SLOT[SLOT1].conn_enum = CONN_PHASEMOD; 02157 (CH+3)->SLOT[SLOT2].conn_enum = CONN_CHAN0 + chan_no + 3; 02158 break; 02159 case 3: 02160 /* 1 ------\ 02161 2 -> 3 -+- out 02162 4 ------/ */ 02163 CH->SLOT[SLOT1].conn_enum = CONN_CHAN0 + chan_no; 02164 CH->SLOT[SLOT2].conn_enum = CONN_PHASEMOD2; 02165 (CH+3)->SLOT[SLOT1].conn_enum = CONN_CHAN0 + chan_no + 3; 02166 (CH+3)->SLOT[SLOT2].conn_enum = CONN_CHAN0 + chan_no + 3; 02167 break; 02168 } 02169 OPL3_SLOT_CONNECT(chip, &CH->SLOT[SLOT1]); 02170 OPL3_SLOT_CONNECT(chip, &CH->SLOT[SLOT2]); 02171 OPL3_SLOT_CONNECT(chip, &(CH+3)->SLOT[SLOT1]); 02172 OPL3_SLOT_CONNECT(chip, &(CH+3)->SLOT[SLOT2]); 02173 } 02174 else 02175 { 02176 /* 2 operators mode */ 02177 CH->SLOT[SLOT1].conn_enum = CH->SLOT[SLOT1].CON ? CONN_CHAN0 + (r&0xf)+ch_offset : CONN_PHASEMOD; 02178 CH->SLOT[SLOT2].conn_enum = CONN_CHAN0 + (r&0xf)+ch_offset; 02179 OPL3_SLOT_CONNECT(chip, &CH->SLOT[SLOT1]); 02180 OPL3_SLOT_CONNECT(chip, &CH->SLOT[SLOT2]); 02181 } 02182 break; 02183 02184 case 3: case 4: case 5: 02185 case 12: case 13: case 14: 02186 if ((CH-3)->extended) 02187 { 02188 uint8_t conn = ((CH-3)->SLOT[SLOT1].CON<<1) | (CH->SLOT[SLOT1].CON<<0); 02189 switch(conn) 02190 { 02191 case 0: 02192 /* 1 -> 2 -> 3 -> 4 - out */ 02193 02194 (CH-3)->SLOT[SLOT1].conn_enum = CONN_PHASEMOD; 02195 (CH-3)->SLOT[SLOT2].conn_enum = CONN_PHASEMOD2; 02196 CH->SLOT[SLOT1].conn_enum = CONN_PHASEMOD; 02197 CH->SLOT[SLOT2].conn_enum = CONN_CHAN0 + chan_no; 02198 break; 02199 case 1: 02200 /* 1 -> 2 -\ 02201 3 -> 4 -+- out */ 02202 02203 (CH-3)->SLOT[SLOT1].conn_enum = CONN_PHASEMOD; 02204 (CH-3)->SLOT[SLOT2].conn_enum = CONN_CHAN0 + chan_no - 3; 02205 CH->SLOT[SLOT1].conn_enum = CONN_PHASEMOD; 02206 CH->SLOT[SLOT2].conn_enum = CONN_CHAN0 + chan_no; 02207 break; 02208 case 2: 02209 /* 1 -----------\ 02210 2 -> 3 -> 4 -+- out */ 02211 02212 (CH-3)->SLOT[SLOT1].conn_enum = CONN_CHAN0 + chan_no - 3; 02213 (CH-3)->SLOT[SLOT2].conn_enum = CONN_PHASEMOD2; 02214 CH->SLOT[SLOT1].conn_enum = CONN_PHASEMOD; 02215 CH->SLOT[SLOT2].conn_enum = CONN_CHAN0 + chan_no; 02216 break; 02217 case 3: 02218 /* 1 ------\ 02219 2 -> 3 -+- out 02220 4 ------/ */ 02221 (CH-3)->SLOT[SLOT1].conn_enum = CONN_CHAN0 + chan_no - 3; 02222 (CH-3)->SLOT[SLOT2].conn_enum = CONN_PHASEMOD2; 02223 CH->SLOT[SLOT1].conn_enum = CONN_CHAN0 + chan_no; 02224 CH->SLOT[SLOT2].conn_enum = CONN_CHAN0 + chan_no; 02225 break; 02226 } 02227 OPL3_SLOT_CONNECT(chip, &(CH-3)->SLOT[SLOT1]); 02228 OPL3_SLOT_CONNECT(chip, &(CH-3)->SLOT[SLOT2]); 02229 OPL3_SLOT_CONNECT(chip, &CH->SLOT[SLOT1]); 02230 OPL3_SLOT_CONNECT(chip, &CH->SLOT[SLOT2]); 02231 } 02232 else 02233 { 02234 /* 2 operators mode */ 02235 CH->SLOT[SLOT1].conn_enum = CH->SLOT[SLOT1].CON ? CONN_CHAN0 + (r&0xf)+ch_offset : CONN_PHASEMOD; 02236 CH->SLOT[SLOT2].conn_enum = CONN_CHAN0 + (r&0xf)+ch_offset; 02237 OPL3_SLOT_CONNECT(chip, &CH->SLOT[SLOT1]); 02238 OPL3_SLOT_CONNECT(chip, &CH->SLOT[SLOT2]); 02239 } 02240 break; 02241 02242 default: 02243 /* 2 operators mode */ 02244 CH->SLOT[SLOT1].conn_enum = CH->SLOT[SLOT1].CON ? CONN_CHAN0 + (r&0xf)+ch_offset : CONN_PHASEMOD; 02245 CH->SLOT[SLOT2].conn_enum = CONN_CHAN0 + (r&0xf)+ch_offset; 02246 OPL3_SLOT_CONNECT(chip, &CH->SLOT[SLOT1]); 02247 OPL3_SLOT_CONNECT(chip, &CH->SLOT[SLOT2]); 02248 break; 02249 } 02250 } 02251 else 02252 { 02253 /* OPL2 mode - always 2 operators mode */ 02254 CH->SLOT[SLOT1].conn_enum = CH->SLOT[SLOT1].CON ? CONN_CHAN0 + (r&0xf)+ch_offset : CONN_PHASEMOD; 02255 CH->SLOT[SLOT2].conn_enum = CONN_CHAN0 + (r&0xf)+ch_offset; 02256 OPL3_SLOT_CONNECT(chip, &CH->SLOT[SLOT1]); 02257 OPL3_SLOT_CONNECT(chip, &CH->SLOT[SLOT2]); 02258 } 02259 break; 02260 02261 case 0xe0: /* waveform select */ 02262 slot = slot_array[r&0x1f]; 02263 if(slot < 0) return; 02264 02265 slot += ch_offset*2; 02266 02267 CH = &chip->P_CH[slot/2]; 02268 02269 02270 /* store 3-bit value written regardless of current OPL2 or OPL3 mode... (verified on real YMF262) */ 02271 v &= 7; 02272 CH->SLOT[slot&1].waveform_number = v; 02273 02274 /* ... but select only waveforms 0-3 in OPL2 mode */ 02275 if( !(chip->OPL3_mode & 1) ) 02276 { 02277 v &= 3; /* we're in OPL2 mode */ 02278 } 02279 CH->SLOT[slot&1].wavetable = v * SIN_LEN; 02280 break; 02281 } 02282 } 02283 02284 /* lock/unlock for common table */ 02285 static int OPL3_LockTable(device_t *device) 02286 { 02287 (void)device; 02288 num_lock++; 02289 if(num_lock>1) return 0; 02290 02291 /* first time */ 02292 02293 if( !init_tables() ) 02294 { 02295 num_lock--; 02296 return -1; 02297 } 02298 02299 return 0; 02300 } 02301 02302 static void OPL3_UnLockTable(void) 02303 { 02304 if(num_lock) num_lock--; 02305 if(num_lock) return; 02306 02307 /* last time */ 02308 OPLCloseTable(); 02309 } 02310 02311 static void OPL3ResetChip(OPL3 *chip) 02312 { 02313 int c,s; 02314 02315 chip->eg_timer = 0; 02316 chip->eg_cnt = 0; 02317 02318 chip->noise_rng = 1; /* noise shift register */ 02319 chip->nts = 0; /* note split */ 02320 OPL3_STATUS_RESET(chip,0x60); 02321 02322 /* reset with register write */ 02323 OPL3WriteReg(chip,0x01,0); /* test register */ 02324 OPL3WriteReg(chip,0x02,0); /* Timer1 */ 02325 OPL3WriteReg(chip,0x03,0); /* Timer2 */ 02326 OPL3WriteReg(chip,0x04,0); /* IRQ mask clear */ 02327 02328 02329 //FIX IT registers 101, 104 and 105 02330 02331 02332 //FIX IT (dont change CH.D, CH.C, CH.B and CH.A in C0-C8 registers) 02333 for(c = 0xff ; c >= 0x20 ; c-- ) 02334 OPL3WriteReg(chip,c,0); 02335 //FIX IT (dont change CH.D, CH.C, CH.B and CH.A in C0-C8 registers) 02336 for(c = 0x1ff ; c >= 0x120 ; c-- ) 02337 OPL3WriteReg(chip,c,0); 02338 02339 02340 02341 /* reset operator parameters */ 02342 for( c = 0 ; c < 9*2 ; c++ ) 02343 { 02344 OPL3_CH *CH = &chip->P_CH[c]; 02345 for(s = 0 ; s < 2 ; s++ ) 02346 { 02347 CH->SLOT[s].state = EG_OFF; 02348 CH->SLOT[s].volume = MAX_ATT_INDEX; 02349 } 02350 } 02351 } 02352 02353 /* Create one of virtual YMF262 */ 02354 /* 'clock' is chip clock in Hz */ 02355 /* 'rate' is sampling rate */ 02356 static OPL3 *OPL3Create(device_t *device, int clock, int rate, int type) 02357 { 02358 OPL3 *chip; 02359 02360 if (OPL3_LockTable(device) == -1) return 0; 02361 02362 /* allocate memory block */ 02363 chip = auto_alloc_clear(device->machine(), OPL3 ); 02364 02365 chip->device = device; 02366 chip->type = type; 02367 chip->clock = clock; 02368 chip->rate = rate; 02369 02370 /* init global tables */ 02371 OPL3_initalize(chip); 02372 02373 /* reset chip */ 02374 OPL3ResetChip(chip); 02375 return chip; 02376 } 02377 02378 /* Destroy one of virtual YMF262 */ 02379 static void OPL3Destroy(OPL3 *chip) 02380 { 02381 OPL3_UnLockTable(); 02382 free(chip); 02383 } 02384 02385 02386 /* YMF262 I/O interface */ 02387 static int OPL3Write(OPL3 *chip, int a, int v) 02388 { 02389 /* data bus is 8 bits */ 02390 v &= 0xff; 02391 02392 02393 switch(a&3) 02394 { 02395 case 0: /* address port 0 (register set #1) */ 02396 chip->address = v; 02397 break; 02398 02399 case 1: /* data port - ignore A1 */ 02400 case 3: /* data port - ignore A1 */ 02401 if(chip->UpdateHandler) chip->UpdateHandler(chip->UpdateParam,0); 02402 OPL3WriteReg(chip,chip->address,v); 02403 break; 02404 02405 case 2: /* address port 1 (register set #2) */ 02406 02407 /* verified on real YMF262: 02408 in OPL3 mode: 02409 address line A1 is stored during *address* write and ignored during *data* write. 02410 02411 in OPL2 mode: 02412 register set#2 writes go to register set#1 (ignoring A1) 02413 verified on registers from set#2: 0x01, 0x04, 0x20-0xef 02414 The only exception is register 0x05. 02415 */ 02416 if( chip->OPL3_mode & 1 ) 02417 { 02418 /* OPL3 mode */ 02419 chip->address = v | 0x100; 02420 } 02421 else 02422 { 02423 /* in OPL2 mode the only accessible in set #2 is register 0x05 */ 02424 if( v==5 ) 02425 chip->address = v | 0x100; 02426 else 02427 chip->address = v; /* verified range: 0x01, 0x04, 0x20-0xef(set #2 becomes set #1 in opl2 mode) */ 02428 } 02429 break; 02430 } 02431 02432 return chip->status>>7; 02433 } 02434 02435 static unsigned char OPL3Read(OPL3 *chip,int a) 02436 { 02437 if( a==0 ) 02438 { 02439 /* status port */ 02440 return chip->status; 02441 } 02442 02443 return 0x00; /* verified on real YMF262 */ 02444 } 02445 02446 02447 02448 static int OPL3TimerOver(OPL3 *chip,int c) 02449 { 02450 if( c ) 02451 { /* Timer B */ 02452 OPL3_STATUS_SET(chip,0x20); 02453 } 02454 else 02455 { /* Timer A */ 02456 OPL3_STATUS_SET(chip,0x40); 02457 } 02458 /* reload timer */ 02459 // if (chip->timer_handler) (chip->timer_handler)(chip->TimerParam,c,chip->TimerBase * chip->T[c]); 02460 return chip->status>>7; 02461 } 02462 02463 static void OPL3_save_state(OPL3 *chip, device_t *device) { 02464 #if 0 02465 for (int ch=0; ch<18; ch++) { 02466 OPL3_CH *channel = &chip->P_CH[ch]; 02467 device->save_item(NAME(channel->block_fnum), ch); 02468 device->save_item(NAME(channel->fc), ch); 02469 device->save_item(NAME(channel->ksl_base), ch); 02470 device->save_item(NAME(channel->kcode), ch); 02471 device->save_item(NAME(channel->extended), ch); 02472 02473 for (int sl=0; sl<2; sl++) { 02474 OPL3_SLOT *slot = &channel->SLOT[sl]; 02475 device->save_item(NAME(slot->ar), ch*2+sl); 02476 device->save_item(NAME(slot->dr), ch*2+sl); 02477 device->save_item(NAME(slot->rr), ch*2+sl); 02478 device->save_item(NAME(slot->KSR), ch*2+sl); 02479 device->save_item(NAME(slot->ksl), ch*2+sl); 02480 device->save_item(NAME(slot->ksr), ch*2+sl); 02481 device->save_item(NAME(slot->mul), ch*2+sl); 02482 02483 device->save_item(NAME(slot->Cnt), ch*2+sl); 02484 device->save_item(NAME(slot->Incr), ch*2+sl); 02485 device->save_item(NAME(slot->FB), ch*2+sl); 02486 device->save_item(NAME(slot->conn_enum), ch*2+sl); 02487 device->save_item(NAME(slot->op1_out), ch*2+sl); 02488 device->save_item(NAME(slot->CON), ch*2+sl); 02489 02490 device->save_item(NAME(slot->eg_type), ch*2+sl); 02491 device->save_item(NAME(slot->state), ch*2+sl); 02492 device->save_item(NAME(slot->TL), ch*2+sl); 02493 device->save_item(NAME(slot->TLL), ch*2+sl); 02494 device->save_item(NAME(slot->volume), ch*2+sl); 02495 device->save_item(NAME(slot->sl), ch*2+sl); 02496 02497 device->save_item(NAME(slot->eg_m_ar), ch*2+sl); 02498 device->save_item(NAME(slot->eg_sh_ar), ch*2+sl); 02499 device->save_item(NAME(slot->eg_sel_ar), ch*2+sl); 02500 device->save_item(NAME(slot->eg_m_dr), ch*2+sl); 02501 device->save_item(NAME(slot->eg_sh_dr), ch*2+sl); 02502 device->save_item(NAME(slot->eg_sel_dr), ch*2+sl); 02503 device->save_item(NAME(slot->eg_m_rr), ch*2+sl); 02504 device->save_item(NAME(slot->eg_sh_rr), ch*2+sl); 02505 device->save_item(NAME(slot->eg_sel_rr), ch*2+sl); 02506 02507 device->save_item(NAME(slot->key), ch*2+sl); 02508 02509 device->save_item(NAME(slot->AMmask), ch*2+sl); 02510 device->save_item(NAME(slot->vib), ch*2+sl); 02511 02512 device->save_item(NAME(slot->waveform_number), ch*2+sl); 02513 device->save_item(NAME(slot->wavetable), ch*2+sl); 02514 } 02515 } 02516 02517 device->save_item(NAME(chip->pan)); 02518 device->save_item(NAME(chip->pan_ctrl_value)); 02519 02520 device->save_item(NAME(chip->lfo_am_depth)); 02521 device->save_item(NAME(chip->lfo_pm_depth_range)); 02522 02523 device->save_item(NAME(chip->OPL3_mode)); 02524 device->save_item(NAME(chip->rhythm)); 02525 02526 device->save_item(NAME(chip->address)); 02527 device->save_item(NAME(chip->status)); 02528 device->save_item(NAME(chip->statusmask)); 02529 #else 02530 (void)chip; 02531 (void)device; 02532 #endif 02533 } 02534 02535 void * ymf262_init(device_t *device, int clock, int rate) 02536 { 02537 void *chip = OPL3Create(device,clock,rate,OPL3_TYPE_YMF262); 02538 OPL3_save_state((OPL3 *)chip, device); 02539 02540 return chip; 02541 } 02542 02543 void ymf262_post_load(void *chip) { 02544 OPL3 *opl3 = (OPL3 *)chip; 02545 for (int ch=0; ch<18; ch++) { 02546 for (int sl=0; sl<2; sl++) { 02547 OPL3_SLOT_CONNECT(opl3, &(opl3->P_CH[ch].SLOT[sl])); 02548 } 02549 } 02550 } 02551 02552 void ymf262_shutdown(void *chip) 02553 { 02554 OPL3Destroy((OPL3 *)chip); 02555 } 02556 void ymf262_reset_chip(void *chip) 02557 { 02558 OPL3ResetChip((OPL3 *)chip); 02559 } 02560 02561 int ymf262_write(void *chip, int a, int v) 02562 { 02563 return OPL3Write((OPL3 *)chip, a, v); 02564 } 02565 02566 unsigned char ymf262_read(void *chip, int a) 02567 { 02568 /* Note on status register: */ 02569 02570 /* YM3526(OPL) and YM3812(OPL2) return bit2 and bit1 in HIGH state */ 02571 02572 /* YMF262(OPL3) always returns bit2 and bit1 in LOW state */ 02573 /* which can be used to identify the chip */ 02574 02575 /* YMF278(OPL4) returns bit2 in LOW and bit1 in HIGH state ??? info from manual - not verified */ 02576 02577 return OPL3Read((OPL3 *)chip, a); 02578 } 02579 int ymf262_timer_over(void *chip, int c) 02580 { 02581 return OPL3TimerOver((OPL3 *)chip, c); 02582 } 02583 02584 void ymf262_set_timer_handler(void *chip, OPL3_TIMERHANDLER timer_handler, device_t *device) 02585 { 02586 reinterpret_cast<OPL3 *>(chip)->SetTimerHandler(timer_handler, device); 02587 } 02588 void ymf262_set_irq_handler(void *chip, OPL3_IRQHANDLER IRQHandler, device_t *device) 02589 { 02590 reinterpret_cast<OPL3 *>(chip)->SetIRQHandler(IRQHandler, device); 02591 } 02592 void ymf262_set_update_handler(void *chip, OPL3_UPDATEHANDLER UpdateHandler, device_t *device) 02593 { 02594 reinterpret_cast<OPL3 *>(chip)->SetUpdateHandler(UpdateHandler, device); 02595 } 02596 02597 void SaveState_Channel(OPL3_CH *channel, std::ostream& stream) { 02598 WRITE_POD( &channel->block_fnum, channel->block_fnum ); 02599 WRITE_POD( &channel->fc, channel->fc ); 02600 WRITE_POD( &channel->ksl_base, channel->ksl_base ); 02601 WRITE_POD( &channel->kcode, channel->kcode ); 02602 WRITE_POD( &channel->extended, channel->extended ); 02603 } 02604 02605 void LoadState_Channel(OPL3_CH *channel, std::istream& stream) { 02606 READ_POD( &channel->block_fnum, channel->block_fnum ); 02607 READ_POD( &channel->fc, channel->fc ); 02608 READ_POD( &channel->ksl_base, channel->ksl_base ); 02609 READ_POD( &channel->kcode, channel->kcode ); 02610 READ_POD( &channel->extended, channel->extended ); 02611 } 02612 02613 void SaveState_Slot(OPL3_SLOT *slot, std::ostream& stream) { 02614 WRITE_POD( &slot->ar, slot->ar ); 02615 WRITE_POD( &slot->dr, slot->dr ); 02616 WRITE_POD( &slot->rr, slot->rr ); 02617 WRITE_POD( &slot->KSR, slot->KSR ); 02618 WRITE_POD( &slot->ksl, slot->ksl ); 02619 WRITE_POD( &slot->ksr, slot->ksr ); 02620 WRITE_POD( &slot->mul, slot->mul ); 02621 02622 WRITE_POD( &slot->Cnt, slot->Cnt ); 02623 WRITE_POD( &slot->Incr, slot->Incr ); 02624 WRITE_POD( &slot->FB, slot->FB ); 02625 WRITE_POD( &slot->conn_enum, slot->conn_enum ); 02626 WRITE_POD( &slot->op1_out, slot->op1_out ); 02627 WRITE_POD( &slot->CON, slot->CON ); 02628 02629 WRITE_POD( &slot->eg_type, slot->eg_type ); 02630 WRITE_POD( &slot->state, slot->state ); 02631 WRITE_POD( &slot->TL, slot->TL ); 02632 WRITE_POD( &slot->TLL, slot->TLL ); 02633 WRITE_POD( &slot->volume, slot->volume ); 02634 WRITE_POD( &slot->sl, slot->sl ); 02635 02636 WRITE_POD( &slot->eg_m_ar, slot->eg_m_ar ); 02637 WRITE_POD( &slot->eg_sh_ar, slot->eg_sh_ar ); 02638 WRITE_POD( &slot->eg_sel_ar, slot->eg_sel_ar ); 02639 WRITE_POD( &slot->eg_m_dr, slot->eg_m_dr ); 02640 WRITE_POD( &slot->eg_sh_dr, slot->eg_sh_dr ); 02641 WRITE_POD( &slot->eg_sel_dr, slot->eg_sel_dr ); 02642 WRITE_POD( &slot->eg_m_rr, slot->eg_m_rr ); 02643 WRITE_POD( &slot->eg_sh_rr, slot->eg_sh_rr ); 02644 WRITE_POD( &slot->eg_sel_rr, slot->eg_sel_rr ); 02645 02646 WRITE_POD( &slot->key, slot->key ); 02647 02648 WRITE_POD( &slot->AMmask, slot->AMmask ); 02649 WRITE_POD( &slot->vib, slot->vib ); 02650 02651 WRITE_POD( &slot->waveform_number, slot->waveform_number ); 02652 WRITE_POD( &slot->wavetable, slot->wavetable ); 02653 } 02654 02655 void LoadState_Slot(OPL3_SLOT *slot, std::istream& stream) { 02656 READ_POD( &slot->ar, slot->ar ); 02657 READ_POD( &slot->dr, slot->dr ); 02658 READ_POD( &slot->rr, slot->rr ); 02659 READ_POD( &slot->KSR, slot->KSR ); 02660 READ_POD( &slot->ksl, slot->ksl ); 02661 READ_POD( &slot->ksr, slot->ksr ); 02662 READ_POD( &slot->mul, slot->mul ); 02663 02664 READ_POD( &slot->Cnt, slot->Cnt ); 02665 READ_POD( &slot->Incr, slot->Incr ); 02666 READ_POD( &slot->FB, slot->FB ); 02667 READ_POD( &slot->conn_enum, slot->conn_enum ); 02668 READ_POD( &slot->op1_out, slot->op1_out ); 02669 READ_POD( &slot->CON, slot->CON ); 02670 02671 READ_POD( &slot->eg_type, slot->eg_type ); 02672 READ_POD( &slot->state, slot->state ); 02673 READ_POD( &slot->TL, slot->TL ); 02674 READ_POD( &slot->TLL, slot->TLL ); 02675 READ_POD( &slot->volume, slot->volume ); 02676 READ_POD( &slot->sl, slot->sl ); 02677 02678 READ_POD( &slot->eg_m_ar, slot->eg_m_ar ); 02679 READ_POD( &slot->eg_sh_ar, slot->eg_sh_ar ); 02680 READ_POD( &slot->eg_sel_ar, slot->eg_sel_ar ); 02681 READ_POD( &slot->eg_m_dr, slot->eg_m_dr ); 02682 READ_POD( &slot->eg_sh_dr, slot->eg_sh_dr ); 02683 READ_POD( &slot->eg_sel_dr, slot->eg_sel_dr ); 02684 READ_POD( &slot->eg_m_rr, slot->eg_m_rr ); 02685 READ_POD( &slot->eg_sh_rr, slot->eg_sh_rr ); 02686 READ_POD( &slot->eg_sel_rr, slot->eg_sel_rr ); 02687 02688 READ_POD( &slot->key, slot->key ); 02689 02690 READ_POD( &slot->AMmask, slot->AMmask ); 02691 READ_POD( &slot->vib, slot->vib ); 02692 02693 READ_POD( &slot->waveform_number, slot->waveform_number ); 02694 READ_POD( &slot->wavetable, slot->wavetable ); 02695 } 02696 02697 void YMF_SaveState( void *chip, std::ostream& stream ) { 02698 for (int ch=0; ch<18; ch++) { 02699 OPL3_CH *channel = &((OPL3 *)chip)->P_CH[ch]; 02700 02701 SaveState_Channel(channel, stream); 02702 02703 for (int sl=0; sl<2; sl++) { 02704 SaveState_Slot(&channel->SLOT[sl], stream); 02705 } 02706 } 02707 } 02708 02709 void YMF_LoadState( void *chip, std::istream& stream ) { 02710 for (int ch=0; ch<18; ch++) { 02711 OPL3_CH *channel = &((OPL3 *)chip)->P_CH[ch]; 02712 02713 LoadState_Channel(channel, stream); 02714 02715 for (int sl=0; sl<2; sl++) { 02716 LoadState_Slot(&channel->SLOT[sl], stream); 02717 } 02718 } 02719 } 02720 02721 /* 02722 ** Generate samples for one of the YMF262's 02723 ** 02724 ** 'which' is the virtual YMF262 number 02725 ** '**buffers' is table of 4 pointers to the buffers: CH.A, CH.B, CH.C and CH.D 02726 ** 'length' is the number of samples that should be generated 02727 */ 02728 void ymf262_update_one(void *_chip, OPL3SAMPLE **buffers, int length) 02729 { 02730 int i; 02731 OPL3 *chip = (OPL3 *)_chip; 02732 signed int *chanout = chip->chanout; 02733 uint8_t rhythm = chip->rhythm&0x20; 02734 02735 OPL3SAMPLE *ch_a = buffers[0]; 02736 OPL3SAMPLE *ch_b = buffers[1]; 02737 OPL3SAMPLE *ch_c = buffers[2]; 02738 OPL3SAMPLE *ch_d = buffers[3]; 02739 02740 for( i=0; i < length ; i++ ) 02741 { 02742 int a,b,c,d; 02743 02744 02745 advance_lfo(chip); 02746 02747 /* clear channel outputs */ 02748 memset(chip->chanout, 0, sizeof(chip->chanout)); 02749 02750 #if 1 02751 /* register set #1 */ 02752 chan_calc(chip, &chip->P_CH[0]); /* extended 4op ch#0 part 1 or 2op ch#0 */ 02753 if (chip->P_CH[0].extended) 02754 chan_calc_ext(chip, &chip->P_CH[3]); /* extended 4op ch#0 part 2 */ 02755 else 02756 chan_calc(chip, &chip->P_CH[3]); /* standard 2op ch#3 */ 02757 02758 02759 chan_calc(chip, &chip->P_CH[1]); /* extended 4op ch#1 part 1 or 2op ch#1 */ 02760 if (chip->P_CH[1].extended) 02761 chan_calc_ext(chip, &chip->P_CH[4]); /* extended 4op ch#1 part 2 */ 02762 else 02763 chan_calc(chip, &chip->P_CH[4]); /* standard 2op ch#4 */ 02764 02765 02766 chan_calc(chip, &chip->P_CH[2]); /* extended 4op ch#2 part 1 or 2op ch#2 */ 02767 if (chip->P_CH[2].extended) 02768 chan_calc_ext(chip, &chip->P_CH[5]); /* extended 4op ch#2 part 2 */ 02769 else 02770 chan_calc(chip, &chip->P_CH[5]); /* standard 2op ch#5 */ 02771 02772 02773 if(!rhythm) 02774 { 02775 chan_calc(chip, &chip->P_CH[6]); 02776 chan_calc(chip, &chip->P_CH[7]); 02777 chan_calc(chip, &chip->P_CH[8]); 02778 } 02779 else /* Rhythm part */ 02780 { 02781 chan_calc_rhythm(chip, &chip->P_CH[0], (chip->noise_rng>>0)&1 ); 02782 } 02783 02784 /* register set #2 */ 02785 chan_calc(chip, &chip->P_CH[ 9]); 02786 if (chip->P_CH[9].extended) 02787 chan_calc_ext(chip, &chip->P_CH[12]); 02788 else 02789 chan_calc(chip, &chip->P_CH[12]); 02790 02791 02792 chan_calc(chip, &chip->P_CH[10]); 02793 if (chip->P_CH[10].extended) 02794 chan_calc_ext(chip, &chip->P_CH[13]); 02795 else 02796 chan_calc(chip, &chip->P_CH[13]); 02797 02798 02799 chan_calc(chip, &chip->P_CH[11]); 02800 if (chip->P_CH[11].extended) 02801 chan_calc_ext(chip, &chip->P_CH[14]); 02802 else 02803 chan_calc(chip, &chip->P_CH[14]); 02804 02805 02806 /* channels 15,16,17 are fixed 2-operator channels only */ 02807 chan_calc(chip, &chip->P_CH[15]); 02808 chan_calc(chip, &chip->P_CH[16]); 02809 chan_calc(chip, &chip->P_CH[17]); 02810 #endif 02811 02812 /* accumulator register set #1 */ 02813 a = chanout[0] & chip->pan[0]; 02814 b = chanout[0] & chip->pan[1]; 02815 c = chanout[0] & chip->pan[2]; 02816 d = chanout[0] & chip->pan[3]; 02817 #if 1 02818 a += chanout[1] & chip->pan[4]; 02819 b += chanout[1] & chip->pan[5]; 02820 c += chanout[1] & chip->pan[6]; 02821 d += chanout[1] & chip->pan[7]; 02822 a += chanout[2] & chip->pan[8]; 02823 b += chanout[2] & chip->pan[9]; 02824 c += chanout[2] & chip->pan[10]; 02825 d += chanout[2] & chip->pan[11]; 02826 02827 a += chanout[3] & chip->pan[12]; 02828 b += chanout[3] & chip->pan[13]; 02829 c += chanout[3] & chip->pan[14]; 02830 d += chanout[3] & chip->pan[15]; 02831 a += chanout[4] & chip->pan[16]; 02832 b += chanout[4] & chip->pan[17]; 02833 c += chanout[4] & chip->pan[18]; 02834 d += chanout[4] & chip->pan[19]; 02835 a += chanout[5] & chip->pan[20]; 02836 b += chanout[5] & chip->pan[21]; 02837 c += chanout[5] & chip->pan[22]; 02838 d += chanout[5] & chip->pan[23]; 02839 02840 a += chanout[6] & chip->pan[24]; 02841 b += chanout[6] & chip->pan[25]; 02842 c += chanout[6] & chip->pan[26]; 02843 d += chanout[6] & chip->pan[27]; 02844 a += chanout[7] & chip->pan[28]; 02845 b += chanout[7] & chip->pan[29]; 02846 c += chanout[7] & chip->pan[30]; 02847 d += chanout[7] & chip->pan[31]; 02848 a += chanout[8] & chip->pan[32]; 02849 b += chanout[8] & chip->pan[33]; 02850 c += chanout[8] & chip->pan[34]; 02851 d += chanout[8] & chip->pan[35]; 02852 02853 /* accumulator register set #2 */ 02854 a += chanout[9] & chip->pan[36]; 02855 b += chanout[9] & chip->pan[37]; 02856 c += chanout[9] & chip->pan[38]; 02857 d += chanout[9] & chip->pan[39]; 02858 a += chanout[10] & chip->pan[40]; 02859 b += chanout[10] & chip->pan[41]; 02860 c += chanout[10] & chip->pan[42]; 02861 d += chanout[10] & chip->pan[43]; 02862 a += chanout[11] & chip->pan[44]; 02863 b += chanout[11] & chip->pan[45]; 02864 c += chanout[11] & chip->pan[46]; 02865 d += chanout[11] & chip->pan[47]; 02866 02867 a += chanout[12] & chip->pan[48]; 02868 b += chanout[12] & chip->pan[49]; 02869 c += chanout[12] & chip->pan[50]; 02870 d += chanout[12] & chip->pan[51]; 02871 a += chanout[13] & chip->pan[52]; 02872 b += chanout[13] & chip->pan[53]; 02873 c += chanout[13] & chip->pan[54]; 02874 d += chanout[13] & chip->pan[55]; 02875 a += chanout[14] & chip->pan[56]; 02876 b += chanout[14] & chip->pan[57]; 02877 c += chanout[14] & chip->pan[58]; 02878 d += chanout[14] & chip->pan[59]; 02879 02880 a += chanout[15] & chip->pan[60]; 02881 b += chanout[15] & chip->pan[61]; 02882 c += chanout[15] & chip->pan[62]; 02883 d += chanout[15] & chip->pan[63]; 02884 a += chanout[16] & chip->pan[64]; 02885 b += chanout[16] & chip->pan[65]; 02886 c += chanout[16] & chip->pan[66]; 02887 d += chanout[16] & chip->pan[67]; 02888 a += chanout[17] & chip->pan[68]; 02889 b += chanout[17] & chip->pan[69]; 02890 c += chanout[17] & chip->pan[70]; 02891 d += chanout[17] & chip->pan[71]; 02892 #endif 02893 a >>= FINAL_SH; 02894 b >>= FINAL_SH; 02895 c >>= FINAL_SH; 02896 d >>= FINAL_SH; 02897 02898 /* limit check */ 02899 a = limit( a , MAXOUT, MINOUT ); 02900 b = limit( b , MAXOUT, MINOUT ); 02901 c = limit( c , MAXOUT, MINOUT ); 02902 d = limit( d , MAXOUT, MINOUT ); 02903 02904 #ifdef SAVE_SAMPLE 02905 if (which==0) 02906 { 02907 SAVE_ALL_CHANNELS 02908 } 02909 #endif 02910 02911 /* store to sound buffer */ 02912 ch_a[i] = a; 02913 ch_b[i] = b; 02914 ch_c[i] = c; 02915 ch_d[i] = d; 02916 02917 advance(chip); 02918 } 02919 02920 }
1.8.0
