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include/pc98_gdc.h
00001 
00002 #define PC98_GDC_FIFO_SIZE      32      /* taken from Neko Project II, but what is it really? */
00003 #define GDC_COMMAND_BYTE        0x100
00004 
00005 enum {
00006     GDC_MASTER=0,
00007     GDC_SLAVE=1
00008 };
00009 
00010 // VOPBIT_* source: Neko Project II
00011 
00012 // operate:             bit0    access page
00013 //                              bit1    egc enable
00014 //                              bit2    grcg bit6
00015 //                              bit3    grcg bit7
00016 //                              bit4    analog enable (16/256-color mode). 8-color mode if not.
00017 //                              bit5    pc9821 vga
00018 
00019 enum {
00020         VOPBIT_ACCESS   = 0,
00021         VOPBIT_EGC              = 1,
00022         VOPBIT_GRCG             = 2,
00023         VOPBIT_ANALOG   = 4,
00024         VOPBIT_VGA              = 5
00025 };
00026 
00027 union pc98_tile {
00028     uint8_t                 b[2];
00029     uint16_t                w;
00030 };
00031 
00032 struct PC98_GDC_state {
00033     PC98_GDC_state();
00034     void reset_fifo(void);
00035     void reset_rfifo(void);
00036     void flush_fifo_old(void);
00037     bool write_fifo(const uint16_t c);
00038     bool write_fifo_command(const unsigned char c);
00039     bool write_fifo_param(const unsigned char c);
00040     bool rfifo_has_content(void);
00041     uint8_t read_status(void);
00042     uint8_t rfifo_read_data(void);
00043     void idle_proc(void);
00044 
00045     void force_fifo_complete(void);
00046     void take_cursor_char_setup(unsigned char bi);
00047     void take_cursor_pos(unsigned char bi);
00048     void take_reset_sync_parameters(void);
00049     void cursor_advance(void);
00050 
00051     void begin_frame(void);
00052     void next_line(void);
00053 
00054     void load_display_partition(void);
00055     void next_display_partition(void);
00056 
00057     size_t fifo_can_read(void);
00058     bool fifo_empty(void);
00059     Bit16u read_fifo(void);
00060 
00061     /* NTS:
00062      *
00063      * We're following the Neko Project II method of FIFO emulation BUT
00064      * I wonder if the GDC maintains two FIFOs and allows stacking params
00065      * in one and commands in another....? */
00066 
00067     uint8_t                 cmd_parm_tmp[8];            /* temp storage before accepting params */
00068 
00069     uint8_t                 rfifo[PC98_GDC_FIFO_SIZE];
00070     uint8_t                 rfifo_read,rfifo_write;
00071 
00072     uint16_t                fifo[PC98_GDC_FIFO_SIZE];   /* NTS: Neko Project II uses one big FIFO for command and data, which makes sense to me */
00073     uint8_t                 fifo_read,fifo_write;
00074 
00075     uint8_t                 param_ram[16];
00076     uint8_t                 param_ram_wptr;
00077 
00078     uint16_t                scan_address;
00079     uint8_t                 row_height;
00080     uint8_t                 row_line;
00081 
00082     uint8_t                 display_partition;
00083     uint16_t                display_partition_rem_lines;
00084     uint8_t                 display_partition_mask;
00085 
00086     uint16_t                active_display_lines;       /* AL (translated) */
00087     uint16_t                active_display_words_per_line;/* AW bits (translated) */
00088     uint16_t                display_pitch;
00089     uint8_t                 horizontal_sync_width;      /* HS (translated) */
00090     uint8_t                 vertical_sync_width;        /* VS (translated) */
00091     uint8_t                 horizontal_front_porch_width;/* HFP (translated) */
00092     uint8_t                 horizontal_back_porch_width;/* HBP (translated) */
00093     uint8_t                 vertical_front_porch_width; /* VFP (translated) */
00094     uint8_t                 vertical_back_porch_width;  /* VBP (translated) */
00095     uint8_t                 display_mode;               /* CG bits */
00096             /* CG = 00 = mixed graphics & character
00097              * CG = 01 = graphics mode
00098              * CG = 10 = character mode
00099              * CG = 11 = invalid */
00100     uint8_t                 video_framing;              /* IS bits */
00101             /* IS = 00 = non-interlaced
00102              * IS = 01 = invalid
00103              * IS = 10 = interlaced repeat field for character displays
00104              * IS = 11 = interlaced */
00105     uint8_t                 current_command;
00106     uint8_t                 proc_step;
00107     uint8_t                 cursor_blink_state;
00108     uint8_t                 cursor_blink_count;         /* count from 0 to BR - 1 */
00109     uint8_t                 cursor_blink_rate;          /* BR */
00110     bool                    draw_only_during_retrace;   /* F bits */
00111     bool                    dynamic_ram_refresh;        /* D bits */
00112     bool                    master_sync;                /* master source generation */
00113     bool                    display_enable;
00114     bool                    cursor_enable;
00115     bool                    cursor_blink;
00116     bool                    idle;
00117 
00118     bool                    doublescan;                 /* 200-line as 400-line */
00119 };
00120 
00121 typedef union pc98_tile             egc_quad[4];
00122 
00123 extern bool                         gdc_analog;
00124 
00125 extern uint32_t                     pc98_text_palette[8];
00126 
00127 extern struct PC98_GDC_state        pc98_gdc[2];
00128 extern egc_quad                     pc98_gdc_tiles;
00129 extern uint8_t                      pc98_gdc_vramop;
00130 extern uint8_t                      pc98_gdc_modereg;
00131